In special purpose processing node

Industry

CPC
G06F2212/301

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures

Current Industry

G06F2212/301In special purpose processing node

Industries

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 12,072,814
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,007,907
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache that supports draining write-miss entries
- Patent number 12,001,345
- Issue date Jun 4, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch kill and revival in an instruction cache
- Patent number 11,977,491
- Issue date May 7, 2024
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware interconnect with memory coherence
- Patent number 11,966,335
- Issue date Apr 23, 2024
- Google LLC
- Kiran Suresh Puranik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce read-modify-write cycles for non-al...
- Patent number 11,940,929
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 11,940,930
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 11,886,353
- Issue date Jan 30, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 11,868,272
- Issue date Jan 9, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 11,803,486
- Issue date Oct 31, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic compare and swap in cach...
- Patent number 11,775,446
- Issue date Oct 3, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different tags
- Patent number 11,762,780
- Issue date Sep 19, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate fully pipelined read-modify-wri...
- Patent number 11,741,020
- Issue date Aug 29, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 11,714,760
- Issue date Aug 1, 2023
- Texas Instmments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate write miss caching in cache system
- Patent number 11,693,790
- Issue date Jul 4, 2023
- Texas Instmments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache that supports draining write-miss entries
- Patent number 11,693,791
- Issue date Jul 4, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 11,640,357
- Issue date May 2, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for inflight data forwarding and invalidation...
- Patent number 11,636,040
- Issue date Apr 25, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 11,620,230
- Issue date Apr 4, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch kill and revival in an instruction cache
- Patent number 11,620,236
- Issue date Apr 4, 2023
- Texas Instruments Incorporated
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate an atomic operation and/or a hi...
- Patent number 11,507,513
- Issue date Nov 22, 2022
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 11,461,236
- Issue date Oct 4, 2022
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 11,449,432
- Issue date Sep 20, 2022
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 11,442,868
- Issue date Sep 13, 2022
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 11,403,229
- Issue date Aug 2, 2022
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 11,360,905
- Issue date Jun 14, 2022
- Texas Instmments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20240264952
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
- Publication number 20240256464
- Publication date Aug 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...
- Publication number 20240232100
- Publication date Jul 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE
- Publication number 20240193098
- Publication date Jun 13, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20240143516
- Publication date May 2, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20240104026
- Publication date Mar 28, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS
- Publication number 20240078190
- Publication date Mar 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20240028523
- Publication date Jan 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20240020242
- Publication date Jan 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE MERGING ON STORES WITH DIFFERENT TAGS
- Publication number 20240004800
- Publication date Jan 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20230401162
- Publication date Dec 14, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20230342305
- Publication date Oct 26, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE WRITE MISS CACHING IN CACHE SYSTEM
- Publication number 20230333991
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20230281126
- Publication date Sep 7, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
- Publication number 20230251975
- Publication date Aug 10, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20230236974
- Publication date Jul 27, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20230108306
- Publication date Apr 6, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20230032348
- Publication date Feb 2, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM FOR ACCELERATING GRAPH NEURAL NETWORK PROCESSING
- Publication number 20230026824
- Publication date Jan 26, 2023
- T-head (Shanghai) Semiconductor Co., Ltd.
- Fei XUE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20230004500
- Publication date Jan 5, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE
- Publication number 20220374362
- Publication date Nov 24, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS
- Publication number 20220309004
- Publication date Sep 29, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20220292023
- Publication date Sep 15, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE MERGING ON STORES WITH DIFFERENT TAGS
- Publication number 20220276965
- Publication date Sep 1, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
- Publication number 20220245069
- Publication date Aug 4, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH
- Publication number 20220206949
- Publication date Jun 30, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR ISSUING REQUESTS TO AN ACCELERATOR FROM MULTIPLE THREADS
- Publication number 20200218568
- Publication date Jul 9, 2020
- Intel Corporation
- Ronny Ronen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING LOW-LEVEL INSTRUCTIONS AND CORE INTERACTIONS IN MULTI-CORE...
- Publication number 20200097292
- Publication date Mar 26, 2020
- Marvell International Ltd.
- David Albert Carlson
- G06 - COMPUTING CALCULATING COUNTING

In special purpose processing node

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Methods and apparatus for read-modify-write support in multi-banked...

Victim cache with dynamic allocation of entries

Atomic operations and histogram operations in a cache pipeline

Methods and apparatus for eviction in dual datapath victim cache sy...

Methods and apparatus to facilitate read-modify-write support in a...

Victim cache with write miss merging

Victim cache that supports draining write-miss entries

Prefetch kill and revival in an instruction cache

Hardware interconnect with memory coherence

Methods and apparatus to reduce read-modify-write cycles for non-al...

Methods and apparatus to facilitate atomic operations in victim cache

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus for allocation in a victim cache system

Write merging on stores with different privilege levels

Methods and apparatus to facilitate atomic compare and swap in cach...

Write merging on stores with different tags

Methods and apparatus to facilitate fully pipelined read-modify-wri...

Methods and apparatus to reduce bank pressure using aggressive writ...

Methods and apparatus to facilitate write miss caching in cache system

Victim cache that supports draining write-miss entries

Methods and apparatus to facilitate read-modify-write support in a...

Methods and apparatus for inflight data forwarding and invalidation...

Methods and apparatus to facilitate read-modify-write support in a...

Prefetch kill and revival in an instruction cache

Methods and apparatus to facilitate an atomic operation and/or a hi...

Methods and apparatus for allocation in a victim cache system

Methods and apparatus for eviction in dual datapath victim cache sy...

Aggressive write flush scheme for a victim cache

Methods and apparatus to facilitate atomic operations in victim cache

Write merging on stores with different privilege levels

Patents Applicationslast 30 patents

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

VICTIM CACHE WITH WRITE MISS MERGING

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE

METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...

METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

WRITE MERGING ON STORES WITH DIFFERENT TAGS

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

METHODS AND APPARATUS TO FACILITATE WRITE MISS CACHING IN CACHE SYSTEM

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

MEMORY SYSTEM FOR ACCELERATING GRAPH NEURAL NETWORK PROCESSING

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE

WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS

VICTIM CACHE WITH WRITE MISS MERGING

WRITE MERGING ON STORES WITH DIFFERENT TAGS

PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE

METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH

MECHANISM FOR ISSUING REQUESTS TO AN ACCELERATOR FROM MULTIPLE THREADS

MANAGING LOW-LEVEL INSTRUCTIONS AND CORE INTERACTIONS IN MULTI-CORE...