Instruction prefetching

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G06F9/3802

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/3802Instruction prefetching

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Patents Grantslast 30 patents

Information Patent Grant
System with dynamically selectable firmware image sequencing for pr...
- Patent number 12,169,720
- Issue date Dec 17, 2024
- Cirrus Logic, Inc.
- Nariankadu D. Hemkumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor system with dynamically selectable multi-stage firm...
- Patent number 12,164,925
- Issue date Dec 10, 2024
- Cirrus Logic, Inc.
- Nariankadu D. Hemkumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector dataflow architecture for embedded systems
- Patent number 12,164,926
- Issue date Dec 10, 2024
- Carnegie Mellon University
- Brandon Lucia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tracking streaming engine vector predicates to control processor ex...
- Patent number 12,164,438
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Duc Quang Bui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware autoloader
- Patent number 12,164,637
- Issue date Dec 10, 2024
- Graphcore Limited
- Daniel John Pelham Wilkinson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive matrix multiplication accelerator for machine learning and...
- Patent number 12,153,646
- Issue date Nov 26, 2024
- Samsung Electronics Co., Ltd.
- Dongyan Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive matrix multiplication accelerator for machine learning and...
- Patent number 12,141,227
- Issue date Nov 12, 2024
- Samsung Electronics Co., Ltd.
- Dongyan Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ISA opcode parameterization and opcode space layout randomization
- Patent number 12,131,159
- Issue date Oct 29, 2024
- Intel Corporation
- Jason Agron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for performing instructions to convert to 16-bi...
- Patent number 12,131,154
- Issue date Oct 29, 2024
- Intel Corporation
- Alexander F. Heinecke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction prefetch based on thread dispatch commands
- Patent number 12,124,852
- Issue date Oct 22, 2024
- Intel Corporation
- James Valerio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
One-dimensional zero padding in a stream of matrix elements
- Patent number 12,118,358
- Issue date Oct 15, 2024
- Texas Instruments Incorporated
- Son Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Central processing unit with asynchronous registers
- Patent number 12,111,788
- Issue date Oct 8, 2024
- UNO Laboratories, Ltd.
- Hideki Ishihara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for vector permutation
- Patent number 12,105,635
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple interfaces for multiple threads of a hardware multi-thread...
- Patent number 12,106,110
- Issue date Oct 1, 2024
- Ceremorphic, Inc.
- Heonchul Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for sum of square differences
- Patent number 12,099,838
- Issue date Sep 24, 2024
- Intel Corporation
- Deepti Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,099,461
- Issue date Sep 24, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for power virus protection in a processor
- Patent number 12,099,597
- Issue date Sep 24, 2024
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression techniques
- Patent number 12,093,210
- Issue date Sep 17, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for permuting streamed data elements
- Patent number 12,086,074
- Issue date Sep 10, 2024
- Texas Instruments Incorporated
- Soujanya Narnur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for hardware-assisted pre-execution
- Patent number 12,079,631
- Issue date Sep 3, 2024
- Hewlett Packard Enterprise Development LP
- Sanyam Mehta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor operation scheduling for deterministic latency
- Patent number 12,079,155
- Issue date Sep 3, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with fetch ahead hysteresis
- Patent number 12,079,470
- Issue date Sep 3, 2024
- Texas Instruments Incorporated
- Matthew Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Highly integrated scalable, flexible DSP megamodule architecture
- Patent number 12,072,812
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,066,975
- Issue date Aug 20, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable latency instructions
- Patent number 12,067,396
- Issue date Aug 20, 2024
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual data streams sharing dual level two cache access ports to maxi...
- Patent number 12,061,908
- Issue date Aug 13, 2024
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel slice processor having a recirculating load-store queue fo...
- Patent number 12,061,909
- Issue date Aug 13, 2024
- International Business Machines Corporation
- Salma Ayub
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Livelock detection in a hardware design using formal evaluation logic
- Patent number 12,050,849
- Issue date Jul 30, 2024
- Imagination Technologies Limited
- Ashish Darbari
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR VECTOR PERMUTATION
- Publication number 20240419606
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL SIGNAL PROCESSOR (DSP) AND ELECTRONIC DEVICE USING THE SAME
- Publication number 20240419628
- Publication date Dec 19, 2024
- Samsung Electronics Co., Ltd.
- Hyungwoo LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS
- Publication number 20240419324
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Matthew Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT
- Publication number 20240411703
- Publication date Dec 12, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE LATENCY INSTRUCTIONS
- Publication number 20240411559
- Publication date Dec 12, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. ANDERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION TECHNIQUES
- Publication number 20240403259
- Publication date Dec 5, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS
- Publication number 20240403055
- Publication date Dec 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor having Switch Instruction Circuit
- Publication number 20240394062
- Publication date Nov 28, 2024
- Microchip Technology Inc.
- Christopher I. W. NORRIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSOR CORE, DATA PROCESSOR, ELECTRONIC DEVICE, AND STORAGE...
- Publication number 20240393856
- Publication date Nov 28, 2024
- Kunlunxin Technology (Beijing) Company Limited
- Hui ZHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE
- Publication number 20240385840
- Publication date Nov 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Raymond Michael Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS
- Publication number 20240378158
- Publication date Nov 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Soujanya Narnur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME T...
- Publication number 20240378056
- Publication date Nov 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS
- Publication number 20240378058
- Publication date Nov 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- William Franklin Leven
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE ORGANIZATION FOR TRANSPOSING A MATRIX USING A STREAMING ENGINE
- Publication number 20240370264
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Jonathan (Son) Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS, APPARATUS, AND ARTICLES OF MANUFACTURE TO ALIGN DATA TO AD...
- Publication number 20240362023
- Publication date Oct 31, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Saya Goud Langadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Re-use of Speculative Load Instruction Results from Wrong Path
- Publication number 20240354109
- Publication date Oct 24, 2024
- Apple Inc.
- Yuan C. Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RUNTIME ADAPTIVE PREFETCHING IN A MANY-CORE SYSTEM
- Publication number 20240354110
- Publication date Oct 24, 2024
- Ampere Computing LLC
- Erika Susana ALCORTA LOZANO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Vector Based Matrix Multiplication
- Publication number 20240354259
- Publication date Oct 24, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SORTING VECTOR ELEMENTS USING A COUNT VALUE
- Publication number 20240354260
- Publication date Oct 24, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURING A PREFETCHER ASSOCIATED WITH A PROCESSOR CORE
- Publication number 20240338219
- Publication date Oct 10, 2024
- SiFive, Inc.
- Paul Walmsley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MUL...
- Publication number 20240330203
- Publication date Oct 3, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mujibur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing of Synchronization Barrier Instructions
- Publication number 20240329990
- Publication date Oct 3, 2024
- Apple Inc.
- Deepankar Duggal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING ARCHITECTURE SUPPORT FOR BLOCK SPARSITY
- Publication number 20240330402
- Publication date Oct 3, 2024
- Intel Corporation
- Omid Azizi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAVE LEVEL MATRIX MULTIPLY INSTRUCTIONS
- Publication number 20240329998
- Publication date Oct 3, 2024
- ADVANCED MICRO DEVICES, INC.
- Bin He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION PREFETCH THROTTLING
- Publication number 20240329999
- Publication date Oct 3, 2024
- ARM Limited
- Chang Joo LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LIVELOCK DETECTION IN A HARDWARE DESIGN USING FORMAL EVALUATION LOGIC
- Publication number 20240330553
- Publication date Oct 3, 2024
- Imagination Technologies Limited
- Ashish Darbari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20240320184
- Publication date Sep 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING

Instruction prefetching

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

System with dynamically selectable firmware image sequencing for pr...

Multi-processor system with dynamically selectable multi-stage firm...

Vector dataflow architecture for embedded systems

Tracking streaming engine vector predicates to control processor ex...

Hardware autoloader

Adaptive matrix multiplication accelerator for machine learning and...

Cache structure and utilization

Adaptive matrix multiplication accelerator for machine learning and...

Systolic disaggregation within a matrix accelerator architecture

ISA opcode parameterization and opcode space layout randomization

Systems and methods for performing instructions to convert to 16-bi...

Instruction prefetch based on thread dispatch commands

One-dimensional zero padding in a stream of matrix elements

Central processing unit with asynchronous registers

Method and apparatus for vector permutation

Multiple interfaces for multiple threads of a hardware multi-thread...

Instruction and logic for sum of square differences

Multi-tile memory management

Apparatus and method for power virus protection in a processor

Compression techniques

Method and apparatus for permuting streamed data elements

Method and system for hardware-assisted pre-execution

Graphics processor operation scheduling for deterministic latency

Streaming engine with fetch ahead hysteresis

Highly integrated scalable, flexible DSP megamodule architecture

Cache structure and utilization

Variable latency instructions

Dual data streams sharing dual level two cache access ports to maxi...

Parallel slice processor having a recirculating load-store queue fo...

Livelock detection in a hardware design using formal evaluation logic

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR VECTOR PERMUTATION

DIGITAL SIGNAL PROCESSOR (DSP) AND ELECTRONIC DEVICE USING THE SAME

CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS

PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT

CACHE STRUCTURE AND UTILIZATION

VARIABLE LATENCY INSTRUCTIONS

COMPRESSION TECHNIQUES

DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS

Processor having Switch Instruction Circuit

DATA PROCESSOR CORE, DATA PROCESSOR, ELECTRONIC DEVICE, AND STORAGE...

CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE

METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS

STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME T...

TWO-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS

STORAGE ORGANIZATION FOR TRANSPOSING A MATRIX USING A STREAMING ENGINE

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

METHODS, APPARATUS, AND ARTICLES OF MANUFACTURE TO ALIGN DATA TO AD...

Re-use of Speculative Load Instruction Results from Wrong Path

RUNTIME ADAPTIVE PREFETCHING IN A MANY-CORE SYSTEM

Vector Based Matrix Multiplication

SORTING VECTOR ELEMENTS USING A COUNT VALUE

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

CONFIGURING A PREFETCHER ASSOCIATED WITH A PROCESSOR CORE

METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MUL...

Processing of Synchronization Barrier Instructions

MACHINE LEARNING ARCHITECTURE SUPPORT FOR BLOCK SPARSITY

WAVE LEVEL MATRIX MULTIPLY INSTRUCTIONS

INSTRUCTION PREFETCH THROTTLING

LIVELOCK DETECTION IN A HARDWARE DESIGN USING FORMAL EVALUATION LOGIC

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS