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G06F2217/66

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2217/00Indexing scheme relating to computer aided design [CAD]

Current Industry

G06F2217/66IP blocks

Industries

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit security
- Patent number 10,573,606
- Issue date Feb 25, 2020
- International Business Machines Corporation
- Kafai Lai
- B65 - CONVEYING PACKING STORING HANDLING THIN OR FILAMENTARY MATERIAL
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,534,884
- Issue date Jan 14, 2020
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reuse of extracted layout-dependent effects for circuit design usin...
- Patent number 10,521,535
- Issue date Dec 31, 2019
- Synopsys, Inc.
- Donald John Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for system design automation (SDA) of mixed sig...
- Patent number 10,503,855
- Issue date Dec 10, 2019
- Robert Charles Ledzius
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for application specific integrated circuit design
- Patent number 10,467,367
- Issue date Nov 5, 2019
- CHRONOS TECH LLC
- Stefano Giaconi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,417,366
- Issue date Sep 17, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design using generation and instantiation of cir...
- Patent number 10,380,297
- Issue date Aug 13, 2019
- Synopsys, Inc.
- Friedrich Gunter Kurt Sendig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuring a programmable device using high-level language
- Patent number 10,366,189
- Issue date Jul 30, 2019
- Altera Corporation
- Doris Tzu-Lang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,366,191
- Issue date Jul 30, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing an integrated circuit (IC) design comprising at least on...
- Patent number 10,354,032
- Issue date Jul 16, 2019
- Synopsys, Inc.
- Eyal Odiz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal verification driven power modeling and design verification
- Patent number 10,354,028
- Issue date Jul 16, 2019
- International Business Machines Corporation
- Anand Haridass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Effective substitution of global distributed head switch cells with...
- Patent number 10,346,574
- Issue date Jul 9, 2019
- QUALCOMM Incorporated
- Rajesh Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor LSI design device and design method
- Patent number 10,339,242
- Issue date Jul 2, 2019
- Hitachi, Ltd.
- Takumi Uezono
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive multi-tier power distribution grids for integrated circuits
- Patent number 10,318,694
- Issue date Jun 11, 2019
- QUALCOMM Incorporated
- Joon Hyung Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit security
- Patent number 10,312,200
- Issue date Jun 4, 2019
- International Business Machines Corporation
- Kafai Lai
- B65 - CONVEYING PACKING STORING HANDLING THIN OR FILAMENTARY MATERIAL
Information Patent Grant
Integrated circuit simulation with data persistency for efficient m...
- Patent number 10,248,747
- Issue date Apr 2, 2019
- Cadence Design Systems, Inc.
- Jaideep Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,242,140
- Issue date Mar 26, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,235,487
- Issue date Mar 19, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus of a three dimensional integrated circuit
- Patent number 10,157,252
- Issue date Dec 18, 2018
- Taiwan Semiconductor Manufacturing Company
- Chi-Wen Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power consumption estimation method for system on chip (SOC), syste...
- Patent number 10,108,764
- Issue date Oct 23, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shereef Shehata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reuse of extracted layout-dependent effects for circuit design usin...
- Patent number 10,102,324
- Issue date Oct 16, 2018
- Synopsys, Inc.
- Donald John Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a scalable test engine
- Patent number 10,042,729
- Issue date Aug 7, 2018
- Intel Corporation
- Lakshminarayana Pappu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for modeling multi-terminal MOS device for LVS...
- Patent number 9,984,196
- Issue date May 29, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chau-Wen Wei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-project wafer with IP protection by reticle mask pattern modi...
- Patent number 9,947,645
- Issue date Apr 17, 2018
- International Business Machines Corporation
- Soon Yoeng Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System on chip
- Patent number 9,904,802
- Issue date Feb 27, 2018
- NXP USA, INC.
- Michael Rohleder
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System, method and computer-accessible medium for facilitating logi...
- Patent number 9,817,980
- Issue date Nov 14, 2017
- New York University
- Jeyavijayan Rajendran
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Formal verification driven power modeling and design verification
- Patent number 9,697,306
- Issue date Jul 4, 2017
- International Business Machines Corporation
- Anand Haridass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rectilinear macros having non-uniform channel spacing
- Patent number 9,697,320
- Issue date Jul 4, 2017
- QUALCOMM Incorporated
- Sreedhar Gudala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System-on-chip intellectual property block discovery
- Patent number 9,639,646
- Issue date May 2, 2017
- Xilinx, Inc.
- Graham F. Schelle
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Third party component debugging for integrated circuit design
- Patent number 9,619,600
- Issue date Apr 11, 2017
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR IMPLEMENTING VERIFICATION IP FOR PRE-SILICON...
- Publication number 20200311225
- Publication date Oct 1, 2020
- SILICONCH SYSTEMS PVT LTD
- Kaustubh KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN
- Publication number 20200065437
- Publication date Feb 27, 2020
- CHRONOS TECH LLC
- Stefano Giaconi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190294739
- Publication date Sep 26, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK-ON-CHIP FOR INTER-DIE AND INTRA-DIE COMMUNICATION IN MODULA...
- Publication number 20190227963
- Publication date Jul 25, 2019
- Intel Corporation
- George Chong Hean Ooi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE MULTI-TIER POWER DISTRIBUTION GRIDS FOR INTEGRATED CIRCUITS
- Publication number 20190220571
- Publication date Jul 18, 2019
- QUALCOMM Incorporated
- Joon Hyung Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE TO DIE INTERCONNECT STRUCTURE FOR MODULARIZED INTEGRATED CIRCUI...
- Publication number 20190220566
- Publication date Jul 18, 2019
- Intel Corporation
- Lai Guan Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT SECURITY
- Publication number 20190172798
- Publication date Jun 6, 2019
- International Business Machines Corporation
- Kafai Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN
- Publication number 20190095553
- Publication date Mar 28, 2019
- CHRONOS TECH LLC
- Stefano Giaconi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190065635
- Publication date Feb 28, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190065636
- Publication date Feb 28, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A SCALABLE TEST ENGINE
- Publication number 20170286247
- Publication date Oct 5, 2017
- LAKSHMINARAYANA PAPPU
- G01 - MEASURING TESTING
Information Patent Application
Method and Apparatus for Modeling Multi-terminal MOS Device for LVS...
- Publication number 20160267218
- Publication date Sep 15, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chau-Wen Wei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus of a Three Dimensional Integrated Circuit
- Publication number 20160259877
- Publication date Sep 8, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Wen Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND DEVICE FOR SOLID DESIGN OF A SYSTEM
- Publication number 20140350907
- Publication date Nov 27, 2014
- Armand Nachef
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRIC MESH NOC TOPOLOGIES
- Publication number 20140331027
- Publication date Nov 6, 2014
- Joji Philip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF GLOBAL DESIGN CLOSURE AT TOP LEVEL AND DRIVING OF DOWNSTR...
- Publication number 20140298281
- Publication date Oct 2, 2014
- ATRENTA, INC.
- Ravi Varadarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IDENTIFYING HIERARCHICAL CHIP DESIGN INTELLECTUAL PROPERTY THROUGH...
- Publication number 20140181764
- Publication date Jun 26, 2014
- Oasis Tooling, Inc.
- David Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Isolating and/or Debugging Defects in Inte...
- Publication number 20140173539
- Publication date Jun 19, 2014
- Cadence Design Systems, Inc.
- David Guoqing Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D FLOORPLANNING USING 2D AND 3D BLOCKS
- Publication number 20140149958
- Publication date May 29, 2014
- QUALCOMM Incorporated
- Kambiz Samadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRIC MESH NoC TOPOLOGIES
- Publication number 20140115298
- Publication date Apr 24, 2014
- NETSPEED SYSTEMS
- Joji PHILIP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRIC MESH NoC TOPOLOGIES
- Publication number 20140115218
- Publication date Apr 24, 2014
- NETSPEED SYSTEMS
- Joji PHILIP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MIXED SIGNAL IP CORE PROTOTYPING SYSTEM
- Publication number 20140109029
- Publication date Apr 17, 2014
- Haifeng Bai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CORE WRAPPING IN THE PRESENCE OF AN EMBEDDED WRAPPED CORE
- Publication number 20140096097
- Publication date Apr 3, 2014
- LSI Corporation
- Narendra B. Devta Prasanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Verification module apparatus for debugging software and timing of...
- Publication number 20140013163
- Publication date Jan 9, 2014
- S2C INC.
- Mon-Ren Chene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROELECTROMECHANICAL SYSTEM DESIGN AND LAYOUT
- Publication number 20130339918
- Publication date Dec 19, 2013
- Jason V. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Third Party Component Debugging For Integrated Circuit Design
- Publication number 20130318484
- Publication date Nov 28, 2013
- Mentor Graphics Corporation
- Charles Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for the Automatic Generation of RTL from an Un...
- Publication number 20130290693
- Publication date Oct 31, 2013
- Esencia Technologies Inc.
- MIguel A. GUERRERO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL BOTTOM-UP CLOCK DOMAIN CROSSING VERIFICATION
- Publication number 20130239080
- Publication date Sep 12, 2013
- ATRENTA, INC.
- Mohamed Shaker SARWARY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE
- Publication number 20130212366
- Publication date Aug 15, 2013
- Altera Corporation
- Doris Tzu-Lang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE
- Publication number 20130212365
- Publication date Aug 15, 2013
- Altera Corporation
- Doris Tzu-Lang Chen
- G06 - COMPUTING CALCULATING COUNTING

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Integrated circuit security

Layout of large block synthesis blocks in integrated circuits

Reuse of extracted layout-dependent effects for circuit design usin...

Methods and systems for system design automation (SDA) of mixed sig...

System and method for application specific integrated circuit design

Layout of large block synthesis blocks in integrated circuits

Integrated circuit design using generation and instantiation of cir...

Configuring a programmable device using high-level language

Layout of large block synthesis blocks in integrated circuits

Optimizing an integrated circuit (IC) design comprising at least on...

Formal verification driven power modeling and design verification

Effective substitution of global distributed head switch cells with...

Semiconductor LSI design device and design method

Adaptive multi-tier power distribution grids for integrated circuits

Integrated circuit security

Integrated circuit simulation with data persistency for efficient m...

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Method and apparatus of a three dimensional integrated circuit

Power consumption estimation method for system on chip (SOC), syste...

Reuse of extracted layout-dependent effects for circuit design usin...

Apparatus and method for a scalable test engine

Method and apparatus for modeling multi-terminal MOS device for LVS...

Multi-project wafer with IP protection by reticle mask pattern modi...

System on chip

System, method and computer-accessible medium for facilitating logi...

Formal verification driven power modeling and design verification

Rectilinear macros having non-uniform channel spacing

System-on-chip intellectual property block discovery

Third party component debugging for integrated circuit design

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR IMPLEMENTING VERIFICATION IP FOR PRE-SILICON...

SYSTEM AND METHOD FOR APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

NETWORK-ON-CHIP FOR INTER-DIE AND INTRA-DIE COMMUNICATION IN MODULA...

ADAPTIVE MULTI-TIER POWER DISTRIBUTION GRIDS FOR INTEGRATED CIRCUITS

DIE TO DIE INTERCONNECT STRUCTURE FOR MODULARIZED INTEGRATED CIRCUI...

INTEGRATED CIRCUIT SECURITY

SYSTEM AND METHOD FOR APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

APPARATUS AND METHOD FOR A SCALABLE TEST ENGINE

Method and Apparatus for Modeling Multi-terminal MOS Device for LVS...

Method and Apparatus of a Three Dimensional Integrated Circuit

METHOD AND DEVICE FOR SOLID DESIGN OF A SYSTEM

ASYMMETRIC MESH NOC TOPOLOGIES

METHOD OF GLOBAL DESIGN CLOSURE AT TOP LEVEL AND DRIVING OF DOWNSTR...

IDENTIFYING HIERARCHICAL CHIP DESIGN INTELLECTUAL PROPERTY THROUGH...

Method and Apparatus for Isolating and/or Debugging Defects in Inte...

3D FLOORPLANNING USING 2D AND 3D BLOCKS

ASYMMETRIC MESH NoC TOPOLOGIES

ASYMMETRIC MESH NoC TOPOLOGIES

MIXED SIGNAL IP CORE PROTOTYPING SYSTEM

CORE WRAPPING IN THE PRESENCE OF AN EMBEDDED WRAPPED CORE

Verification module apparatus for debugging software and timing of...

MICROELECTROMECHANICAL SYSTEM DESIGN AND LAYOUT

Third Party Component Debugging For Integrated Circuit Design

Method and Apparatus for the Automatic Generation of RTL from an Un...

HIERARCHICAL BOTTOM-UP CLOCK DOMAIN CROSSING VERIFICATION

CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE

CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE