Layout analysis

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G06F17/5081

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions

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G06F17/5081Layout analysis

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Patents Grantslast 30 patents

Information Patent Grant
Defense techniques for split manufacturing
- Patent number 10,867,937
- Issue date Dec 15, 2020
- Board of Regents, The University of Texas System
- Jeyavijayan Rajendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for obfuscating a circuit design
- Patent number 10,671,700
- Issue date Jun 2, 2020
- efavless corporation
- Bertrand Irissou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bandwidth test in networking System-on-Chip verification
- Patent number 10,664,566
- Issue date May 26, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for inter-die block level design
- Patent number 10,664,564
- Issue date May 26, 2020
- Xcelsis Corporation
- Javier A Delacruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electromagnetic shielding metal-insulator-metal capacitor structure
- Patent number 10,665,550
- Issue date May 26, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hui Yu Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inter-cell bridge defect diagnosis
- Patent number 10,657,207
- Issue date May 19, 2020
- Mentor Graphics Corporation
- Huaxing Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency test in networking system-on-chip verification
- Patent number 10,657,217
- Issue date May 19, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying circuits based on timing reports for critical paths
- Patent number 10,650,113
- Issue date May 12, 2020
- International Business Machines Corporation
- Rina Kipnis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multilayer ceramic electronic package with modulated mesh topology
- Patent number 10,652,998
- Issue date May 12, 2020
- International Business Machines Corporation
- Jinwoo Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register pull-out for sequential circuit blocks in circuit designs
- Patent number 10,642,951
- Issue date May 5, 2020
- Xilinx, Inc.
- Govinda Keshavdas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying planarization performance using electrical measures
- Patent number 10,642,950
- Issue date May 5, 2020
- International Business Machines Corporation
- Romain Lallement
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for parasitic-aware capacitor sizing and layout generation
- Patent number 10,635,771
- Issue date Apr 28, 2020
- AnaGlobe Technology, Inc.
- Po-Hung Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Producing mask layouts with rounded corners
- Patent number 10,635,776
- Issue date Apr 28, 2020
- Synopsys, Inc.
- Qiliang Yan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus comprising conductive traces configured to transmit diffe...
- Patent number 10,638,601
- Issue date Apr 28, 2020
- Seagate Technology LLC
- Vinod Arjun Huddar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware and software event tracing for a system-on-chip
- Patent number 10,635,769
- Issue date Apr 28, 2020
- Xilinx, Inc.
- Samuel A. Skalicky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit including filler cell
- Patent number 10,635,775
- Issue date Apr 28, 2020
- Samsung Electronics Co., Ltd.
- Hoi-jin Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for designing an integrated circuit, and method of manufactu...
- Patent number 10,628,550
- Issue date Apr 21, 2020
- Samsung Electronics Co., Ltd.
- Min-su Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Checking minimum width, minimum distance and maximum curvature of p...
- Patent number 10,627,713
- Issue date Apr 21, 2020
- Cadence Design Systems, Inc.
- Janez Jaklic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flow control in networking system-on-chip verification
- Patent number 10,628,548
- Issue date Apr 21, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automation generation of test layouts for verifying a DRC deck
- Patent number 10,628,549
- Issue date Apr 21, 2020
- SAGE DESIGN AUTOMATION LTD
- Martinus Maria Berkens
- G01 - MEASURING TESTING
Information Patent Grant
Optimizing integrated circuit designs based on interactions between...
- Patent number 10,628,544
- Issue date Apr 21, 2020
- International Business Machines Corporation
- Dureseti Chidambarrao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preventing corner violations in fill region of layout using exclusi...
- Patent number 10,628,551
- Issue date Apr 21, 2020
- GLOBALFOUNDRIES Inc.
- Gazi M. Huda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing system for performing colorless routing for quadruple pat...
- Patent number 10,621,300
- Issue date Apr 14, 2020
- Samsung Electronics Co., Ltd.
- Hyo-Sig Won
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Classification and localization of hotspots in integrated physical...
- Patent number 10,621,302
- Issue date Apr 14, 2020
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying a source of nuisance defects on a wafer
- Patent number 10,620,135
- Issue date Apr 14, 2020
- KLA-Tencor Corp.
- Bjorn Brauer
- G01 - MEASURING TESTING
Information Patent Grant
Initial-state and next-state value folding
- Patent number 10,621,297
- Issue date Apr 14, 2020
- International Business Machines Coporation
- Jason R. Baumgartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coordinates-based variational autoencoder for generating synthetic...
- Patent number 10,621,301
- Issue date Apr 14, 2020
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deep trench floorplan distribution design methodology for semicondu...
- Patent number 10,614,190
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Dureseti Chidambarrao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ranking combinations of mutants, test cases and random seeds in mut...
- Patent number 10,614,192
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Peng Fei Gou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor process and performance sensor
- Patent number 10,614,184
- Issue date Apr 7, 2020
- ATLAZO, INC.
- Shahin Solki
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FEOL INTERCONNECT USED AS CAPACITANCE OVER FINS INSTEAD OF GATES
- Publication number 20210143095
- Publication date May 13, 2021
- International Business Machines Corporation
- Michael Sperling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN-RULE CHECKING FOR CURVILINEAR DEVICE FEATURES
- Publication number 20210133293
- Publication date May 6, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Ahmed Hassan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH CONSTRAINED METAL LINE ARRANGEMENT
- Publication number 20210110000
- Publication date Apr 15, 2021
- Taiwan Semiconductor Manufacturing company Ltd.
- XinYong WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USE OF A SPACER BETWEEN LAYERED COIL SECTIONS IN A SUPERCONDUCTING...
- Publication number 20210109175
- Publication date Apr 15, 2021
- GENERAL ELECTRIC COMPANY
- Anbo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Via Coloring Methods and Systems
- Publication number 20210109999
- Publication date Apr 15, 2021
- ARM Limited
- Abhilash Velluridathil Thazhathidathil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMUM LAYOUT OF DIES ON A WAFER
- Publication number 20210103223
- Publication date Apr 8, 2021
- Systems on Silicon Manufacturing Co. PTE. LTD.
- Seng Jian TEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND ASSOCIATED SYSTEM FOR CIRCUIT DESIGN
- Publication number 20210089630
- Publication date Mar 25, 2021
- Taiwan Semiconductor Manufacturing company Ltd.
- CHIA CHENG CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT LAYOUT VALIDATION USING MACHINE LEARNING
- Publication number 20210081509
- Publication date Mar 18, 2021
- Taiwan Semiconductor Manufacturing Company Limited
- Rachid Salik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SRAM HAVING IRREGULARLY SHAPED METAL LINES
- Publication number 20210082475
- Publication date Mar 18, 2021
- Taiwan Semiconductor Manufacturing Co., LTD
- Jui-Lin Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pre-Characterization Mixed-Signal Design, Placement, and Routing Us...
- Publication number 20210081510
- Publication date Mar 18, 2021
- Taiwan Semiconductor Manufacturing Company Limited
- Wen-Shen Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NET ROUTING FOR INTEGRATED CIRCUIT (IC) DESIGN
- Publication number 20210073347
- Publication date Mar 11, 2021
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METAL FILL SHAPE REMOVAL FROM SELECTED NETS
- Publication number 20210073348
- Publication date Mar 11, 2021
- International Business Machines Corporation
- Jesse SURPRISE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENEALOGY DRIVEN IC LAYOUT GENERATOR AND CLASSIFICATION METHOD
- Publication number 20210064714
- Publication date Mar 4, 2021
- Mentor Graphics Corporation
- Mohamed-Nabil Sabry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Edge-Based Camera for Characterizing Semiconductor Layout Designs
- Publication number 20210064717
- Publication date Mar 4, 2021
- Mentor Graphics Corporation
- Hazem Hegazy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPERCONDUCTING CIRCUIT WITH VIRTUAL TIMING ELEMENTS AND RELATED ME...
- Publication number 20210064718
- Publication date Mar 4, 2021
- Microsoft Technology Licensing, LLC
- Janet L. Schneider
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FILL TECHNIQUES FOR AVOIDING BOOLEAN DRC FAILURES DURING CELL PLACE...
- Publication number 20210064719
- Publication date Mar 4, 2021
- International Business Machines Corporation
- David WOLPERT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for improved Circuit Structure Thermal Reliabi...
- Publication number 20210066209
- Publication date Mar 4, 2021
- NXP B.V.
- Leo van Gemert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNERGISTIC DESIGN METHOD FOR FABRICATING INTEGRATED CIRCUIT
- Publication number 20210056175
- Publication date Feb 25, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Katherine H. CHIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Deterministic System for Device Layout Optimization
- Publication number 20210049246
- Publication date Feb 18, 2021
- Taiwan Semiconductor Manufacturing Company Limited
- Chin-Chang Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR PRE-SILICON TESTING INTEGRATED CIRCUIT DESIGNS THAT...
- Publication number 20210019377
- Publication date Jan 21, 2021
- NVIDIA Corporation
- Tezaswi RAJA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR CIRCUIT TIMING FIXING USING EXTENSION META...
- Publication number 20200401668
- Publication date Dec 24, 2020
- Samsung Electronics Co., Ltd.
- Hongda LU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL CLOCK TREE CONSTRUCTION BASED ON CONSTRAINTS
- Publication number 20200401179
- Publication date Dec 24, 2020
- Samsung Electronics Co., Ltd.
- Sridhar SUBRAMANIAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR FABRICATING INTEGRATED CIRCUIT WITH AID OF PR...
- Publication number 20200394279
- Publication date Dec 17, 2020
- Taiwan Semiconductor Manufacturing company Ltd.
- YUNG-HSU CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIAS WITH MULTICONNECTION VIA STRUCTURES
- Publication number 20200387581
- Publication date Dec 10, 2020
- Avatar Integrated Systems, Inc.
- Ping-San Tzeng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CURVILINEAR MASK MODELS
- Publication number 20200380089
- Publication date Dec 3, 2020
- GLOBALFOUNDRIES INC.
- Mohamed Elsayed Mohamed Lotfy GHEITH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREDICTING LOCAL LAYOUT EFFECTS IN CIRCUIT DESIGN PATTERNS
- Publication number 20200380088
- Publication date Dec 3, 2020
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT LAYOUT SIMILARITY METRIC FOR SEMICONDUCTOR TESTSITE COVERAGE
- Publication number 20200364316
- Publication date Nov 19, 2020
- International Business Machines Corporation
- Rasit Onur Topaloglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEARNING-BASED ANALYZER FOR MITIGATING LATCH-UP IN INTEGRATED CIRCUITS
- Publication number 20200342070
- Publication date Oct 29, 2020
- Silicon Space Technologies Corporation D.B.A. Vorago Technologies, Inc.
- Patrice M. Parris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTICAL PROXIMITY CORRECTION (OPC) MODELING METHODS AND METHODS FOR...
- Publication number 20200342071
- Publication date Oct 29, 2020
- Samsung Electronics Co., Ltd.
- Sang Chul YEO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF USING SIMULATION SOFTWARE TO GENERATE CIRCUIT LAYOUT
- Publication number 20200334339
- Publication date Oct 22, 2020
- Realtek Semiconductor Corp.
- Chien-Cheng Liu
- G06 - COMPUTING CALCULATING COUNTING

Layout analysis

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Defense techniques for split manufacturing

Systems and methods for obfuscating a circuit design

Bandwidth test in networking System-on-Chip verification

Systems and methods for inter-die block level design

Electromagnetic shielding metal-insulator-metal capacitor structure

Inter-cell bridge defect diagnosis

Latency test in networking system-on-chip verification

Modifying circuits based on timing reports for critical paths

Multilayer ceramic electronic package with modulated mesh topology

Register pull-out for sequential circuit blocks in circuit designs

Verifying planarization performance using electrical measures

Method for parasitic-aware capacitor sizing and layout generation

Producing mask layouts with rounded corners

Apparatus comprising conductive traces configured to transmit diffe...

Hardware and software event tracing for a system-on-chip

Integrated circuit including filler cell

Method for designing an integrated circuit, and method of manufactu...

Checking minimum width, minimum distance and maximum curvature of p...

Flow control in networking system-on-chip verification

Automation generation of test layouts for verifying a DRC deck

Optimizing integrated circuit designs based on interactions between...

Preventing corner violations in fill region of layout using exclusi...

Computing system for performing colorless routing for quadruple pat...

Classification and localization of hotspots in integrated physical...

Identifying a source of nuisance defects on a wafer

Initial-state and next-state value folding

Coordinates-based variational autoencoder for generating synthetic...

Deep trench floorplan distribution design methodology for semicondu...

Ranking combinations of mutants, test cases and random seeds in mut...

Semiconductor process and performance sensor

Patents Applicationslast 30 patents

FEOL INTERCONNECT USED AS CAPACITANCE OVER FINS INSTEAD OF GATES

DESIGN-RULE CHECKING FOR CURVILINEAR DEVICE FEATURES

INTEGRATED CIRCUIT WITH CONSTRAINED METAL LINE ARRANGEMENT

USE OF A SPACER BETWEEN LAYERED COIL SECTIONS IN A SUPERCONDUCTING...

Via Coloring Methods and Systems

OPTIMUM LAYOUT OF DIES ON A WAFER

METHOD AND ASSOCIATED SYSTEM FOR CIRCUIT DESIGN

INTEGRATED CIRCUIT LAYOUT VALIDATION USING MACHINE LEARNING

SRAM HAVING IRREGULARLY SHAPED METAL LINES

Pre-Characterization Mixed-Signal Design, Placement, and Routing Us...

NET ROUTING FOR INTEGRATED CIRCUIT (IC) DESIGN

METAL FILL SHAPE REMOVAL FROM SELECTED NETS

GENEALOGY DRIVEN IC LAYOUT GENERATOR AND CLASSIFICATION METHOD

Edge-Based Camera for Characterizing Semiconductor Layout Designs

SUPERCONDUCTING CIRCUIT WITH VIRTUAL TIMING ELEMENTS AND RELATED ME...

FILL TECHNIQUES FOR AVOIDING BOOLEAN DRC FAILURES DURING CELL PLACE...

Method and Apparatus for improved Circuit Structure Thermal Reliabi...

SYNERGISTIC DESIGN METHOD FOR FABRICATING INTEGRATED CIRCUIT

Deterministic System for Device Layout Optimization

TECHNIQUES FOR PRE-SILICON TESTING INTEGRATED CIRCUIT DESIGNS THAT...

APPARATUS AND METHOD FOR CIRCUIT TIMING FIXING USING EXTENSION META...

HIERARCHICAL CLOCK TREE CONSTRUCTION BASED ON CONSTRAINTS

METHOD AND SYSTEM FOR FABRICATING INTEGRATED CIRCUIT WITH AID OF PR...

VIAS WITH MULTICONNECTION VIA STRUCTURES

CURVILINEAR MASK MODELS

PREDICTING LOCAL LAYOUT EFFECTS IN CIRCUIT DESIGN PATTERNS

CIRCUIT LAYOUT SIMILARITY METRIC FOR SEMICONDUCTOR TESTSITE COVERAGE

LEARNING-BASED ANALYZER FOR MITIGATING LATCH-UP IN INTEGRATED CIRCUITS

OPTICAL PROXIMITY CORRECTION (OPC) MODELING METHODS AND METHODS FOR...

METHOD OF USING SIMULATION SOFTWARE TO GENERATE CIRCUIT LAYOUT