Location of test circuitry on chip or wafer

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G11C2029/1206Location of test circuitry on chip or wafer

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Patents Grantslast 30 patents

Information Patent Grant
Memory test circuit, memory array, and testing method of memory array
- Patent number 12,170,123
- Issue date Dec 17, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jui-Jen Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
ATPG testing method for latch based memories, for area reduction
- Patent number 12,020,760
- Issue date Jun 25, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit and memory system
- Patent number 11,996,156
- Issue date May 28, 2024
- Kioxia Corporation
- Atsushi Tanaka
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing method, testing system, and testing apparatus for semicondu...
- Patent number 11,929,132
- Issue date Mar 12, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Cheng-Jer Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing method for packaged chip, testing system for packaged chip,...
- Patent number 11,862,269
- Issue date Jan 2, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Cheng-Jer Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory module with reduced ECC overhead and memory system
- Patent number 11,756,646
- Issue date Sep 12, 2023
- Samsung Electronics Co., Ltd.
- Taekwoon Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Quick configurable universal register for a configurable integrated...
- Patent number 11,749,368
- Issue date Sep 5, 2023
- Intel Corporation
- Bee Yee Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metal isolation testing in the context of memory cells
- Patent number 11,631,682
- Issue date Apr 18, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Te-Hsin Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip testing apparatus and system with sharing test interface
- Patent number 11,630,153
- Issue date Apr 18, 2023
- Winbond Electronics Corp.
- Chih-Chiang Lai
- G11 - INFORMATION STORAGE
Information Patent Grant
ATPG testing method for latch based memories, for area reduction
- Patent number 11,557,364
- Issue date Jan 17, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Test key structure
- Patent number 11,404,425
- Issue date Aug 2, 2022
- United Microelectronics Corp.
- Fang-Sheng Chou
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory device, method of operating nonvolatile memory d...
- Patent number 11,334,250
- Issue date May 17, 2022
- Samsung Electronics Co., Ltd.
- Seung-Bum Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nonvolatile memory device
- Patent number 11,294,580
- Issue date Apr 5, 2022
- Samsung Electronics Co., Ltd.
- Seung-Bum Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-chip package and method of testing the same
- Patent number 11,282,584
- Issue date Mar 22, 2022
- SK Hynix Inc.
- Seung Yeol Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in-self-test circuits and methods using pipeline registers
- Patent number 11,257,562
- Issue date Feb 22, 2022
- Intel Corporation
- Tze Sin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module with reduced ECC overhead and memory system
- Patent number 11,222,709
- Issue date Jan 11, 2022
- Samsung Electronics Co., Ltd.
- Taekwoon Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Anti-hacking mechanisms for flash memory device
- Patent number 11,188,237
- Issue date Nov 30, 2021
- Silicon Storage Technology, Inc.
- Hieu Van Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and test operation method thereof
- Patent number 11,133,080
- Issue date Sep 28, 2021
- SK hynix Inc.
- Chang Kyun Park
- G11 - INFORMATION STORAGE
Information Patent Grant
At-risk memory location identification and management
- Patent number 11,107,549
- Issue date Aug 31, 2021
- Microsoft Technology Licensing, LLC
- Timothy B. Cowles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Peripheral logic circuits under DRAM memory arrays
- Patent number 11,031,405
- Issue date Jun 8, 2021
- Micron Technology, Inc.
- Mansour Fardad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for testing three-dimensional memory device
- Patent number 10,998,079
- Issue date May 4, 2021
- Yangtze Memory Technologies Co., Ltd.
- Jong Jun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Tiered read reference calibration
- Patent number 10,991,444
- Issue date Apr 27, 2021
- Western Digital Technologies, Inc.
- Alexander Bazarsky
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and manufacturing method therefor
- Patent number 10,748,915
- Issue date Aug 18, 2020
- TOSHIBA MEMORY CORPORATION
- Kazuhiro Nojima
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nonvolatile memory device, method of operating nonvolatile memory d...
- Patent number 10,712,954
- Issue date Jul 14, 2020
- Samsung Electronics Co., Ltd.
- Seung-Bum Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure and method for testing three-dimensional memory device
- Patent number 10,679,721
- Issue date Jun 9, 2020
- Yangtze Memory Technologies Co., Ltd.
- Jong Jun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of self-testing and reusing of reference cells in a memory a...
- Patent number 10,672,455
- Issue date Jun 2, 2020
- GYRFALCON TECHNOLOGY INC.
- Chyu-Jiuh Torng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metal isolation testing in the context of memory cells
- Patent number 10,665,595
- Issue date May 26, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Te-Hsin Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device and system including the same
- Patent number 10,650,908
- Issue date May 12, 2020
- SK hynix Inc.
- Young Mok Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test circuit block, variable resistance memory device including the...
- Patent number 10,553,644
- Issue date Feb 4, 2020
- SK hynix Inc.
- Seok Joon Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device
- Patent number 10,483,236
- Issue date Nov 19, 2019
- TOSHIBA MEMORY CORPORATION
- Masaji Iwamoto
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ATPG TESTING METHOD FOR LATCH BASED MEMORIES, FOR AREA REDUCTION
- Publication number 20240296899
- Publication date Sep 5, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM
- Publication number 20230386597
- Publication date Nov 30, 2023
- Samsung Electronics Co., LTD
- TAEKWOON KIM
- G11 - INFORMATION STORAGE
Information Patent Application
METAL ISOLATION TESTING IN THE CONTEXT OF MEMORY CELLS
- Publication number 20230255012
- Publication date Aug 10, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Te-Hsin Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING METHOD FOR PACKAGED CHIP, TESTING SYSTEM FOR PACKAGED CHIP,...
- Publication number 20230187005
- Publication date Jun 15, 2023
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Cheng-Jer YANG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT AND MEMORY SYSTEM
- Publication number 20230121722
- Publication date Apr 20, 2023
- KIOXIA Corporation
- Atsushi TANAKA
- G11 - INFORMATION STORAGE
Information Patent Application
ATPG TESTING METHOD FOR LATCH BASED MEMORIES, FOR AREA REDUCTION
- Publication number 20230105305
- Publication date Apr 6, 2023
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING METHOD, TESTING SYSTEM, AND TESTING APPARATUS FOR SEMICONDU...
- Publication number 20220399068
- Publication date Dec 15, 2022
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Cheng-Jer YANG
- G11 - INFORMATION STORAGE
Information Patent Application
CHIP TESTING APPARATUS AND SYSTEM
- Publication number 20220341991
- Publication date Oct 27, 2022
- WINBOND ELECTRONICS CORP.
- Chih-Chiang Lai
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM
- Publication number 20220093203
- Publication date Mar 24, 2022
- Samsung Electronics Co., Ltd.
- TAEKWOON KIM
- G11 - INFORMATION STORAGE
Information Patent Application
TEST KEY STRUCTURE
- Publication number 20210320109
- Publication date Oct 14, 2021
- UNITED MICROELECTRONICS CORP.
- Fang-Sheng Chou
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-CHIP PACKAGE AND METHOD OF TESTING THE SAME
- Publication number 20210304836
- Publication date Sep 30, 2021
- SK HYNIX INC.
- Seung Yeol LEE
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM
- Publication number 20210210156
- Publication date Jul 8, 2021
- Samsung Electronics Co., Ltd.
- TAEKWOON KIM
- G11 - INFORMATION STORAGE
Information Patent Application
AT-RISK MEMORY LOCATION IDENTIFICATION AND MANAGEMENT
- Publication number 20210183463
- Publication date Jun 17, 2021
- Microsoft Technology Licensing, LLC
- Timothy B. COWLES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE AND TEST OPERATION METHOD THEREOF
- Publication number 20200381070
- Publication date Dec 3, 2020
- SK hynix Inc.
- Chang Kyun PARK
- G11 - INFORMATION STORAGE
Information Patent Application
METAL ISOLATION TESTING IN THE CONTEXT OF MEMORY CELLS
- Publication number 20200258892
- Publication date Aug 13, 2020
- Taiwan Semiconductor Manufacturing Co., LTD
- Te-Hsin Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quick Configurable Universal Register for a Configurable Integrated...
- Publication number 20200135289
- Publication date Apr 30, 2020
- Intel Corporation
- Bee Yee Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE AND SYSTEM INCLUDING THE SAME
- Publication number 20190164624
- Publication date May 30, 2019
- SK HYNIX INC.
- Young Mok JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20180277514
- Publication date Sep 27, 2018
- Toshiba Memory Corporation
- Masaji IWAMOTO.
- G11 - INFORMATION STORAGE
Information Patent Application
STACK TYPE SEMICONDUCTOR MEMORY AND SEMICONDUCTOR SYSTEM USING THE...
- Publication number 20170133103
- Publication date May 11, 2017
- SK HYNIX INC.
- Ki Hun KWON
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR PACKAGES AND DATA STORAGE DEVICES INCLUDING THE SAME
- Publication number 20150262708
- Publication date Sep 17, 2015
- Samsung Electronics Co., Ltd.
- EungChang Lee
- G01 - MEASURING TESTING
Information Patent Application
TEST PARTITIONING FOR A NON-VOLATILE MEMORY
- Publication number 20140192599
- Publication date Jul 10, 2014
- Apple Inc.
- Matthew J. Byom
- G11 - INFORMATION STORAGE
Information Patent Application
EMBEDDED PROCESSOR
- Publication number 20130346820
- Publication date Dec 26, 2013
- Micron Technology, Inc.
- Joe M. Jeddeloh
- G01 - MEASURING TESTING
Information Patent Application
BUILT-IN SELF-TEST METHOD AND STRUCTURE
- Publication number 20130265068
- Publication date Oct 10, 2013
- International Business Machines Corporation
- Yoba Amoah
- G01 - MEASURING TESTING
Information Patent Application
FABRICATION AND TESTING METHOD FOR NONVOLATILE MEMORY DEVICES
- Publication number 20130155796
- Publication date Jun 20, 2013
- Samsung Electronics Co., Ltd.
- Hiroshi Sugawara
- G01 - MEASURING TESTING
Information Patent Application
CONTROL SCHEME FOR 3D MEMORY IC
- Publication number 20130148402
- Publication date Jun 13, 2013
- Meng-Fan CHANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM WITH A LAYER COMPRISING A DEDICATED REDUNDANCY AREA
- Publication number 20130070547
- Publication date Mar 21, 2013
- MOSAID Technologies Incorporated
- Hong Beom Pyeon
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD FOR DRIVING MEMORY DEVICE
- Publication number 20120294080
- Publication date Nov 22, 2012
- Semiconductor Energy Laboratory Co., Ltd.
- Masami Endo
- G11 - INFORMATION STORAGE
Information Patent Application
EMBEDDED PROCESSOR
- Publication number 20120221911
- Publication date Aug 30, 2012
- Joe M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING A COUPLING EFFECT OF A...
- Publication number 20120001175
- Publication date Jan 5, 2012
- Jeong-Yoon AHN
- G11 - INFORMATION STORAGE
Information Patent Application
EMBEDDED PROCESSOR
- Publication number 20110185240
- Publication date Jul 28, 2011
- Joe M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING

Location of test circuitry on chip or wafer

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Memory test circuit, memory array, and testing method of memory array

ATPG testing method for latch based memories, for area reduction

Semiconductor integrated circuit and memory system

Testing method, testing system, and testing apparatus for semicondu...

Testing method for packaged chip, testing system for packaged chip,...

Memory module with reduced ECC overhead and memory system

Quick configurable universal register for a configurable integrated...

Metal isolation testing in the context of memory cells

Chip testing apparatus and system with sharing test interface

ATPG testing method for latch based memories, for area reduction

Test key structure

Nonvolatile memory device, method of operating nonvolatile memory d...

Nonvolatile memory device

Multi-chip package and method of testing the same

Built-in-self-test circuits and methods using pipeline registers

Memory module with reduced ECC overhead and memory system

Anti-hacking mechanisms for flash memory device

Memory device and test operation method thereof

At-risk memory location identification and management

Peripheral logic circuits under DRAM memory arrays

Structure and method for testing three-dimensional memory device

Tiered read reference calibration

Memory device and manufacturing method therefor

Nonvolatile memory device, method of operating nonvolatile memory d...

Structure and method for testing three-dimensional memory device

Method of self-testing and reusing of reference cells in a memory a...

Metal isolation testing in the context of memory cells

Semiconductor device and system including the same

Test circuit block, variable resistance memory device including the...

Semiconductor device

Patents Applicationslast 30 patents

ATPG TESTING METHOD FOR LATCH BASED MEMORIES, FOR AREA REDUCTION

MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM

METAL ISOLATION TESTING IN THE CONTEXT OF MEMORY CELLS

TESTING METHOD FOR PACKAGED CHIP, TESTING SYSTEM FOR PACKAGED CHIP,...

SEMICONDUCTOR INTEGRATED CIRCUIT AND MEMORY SYSTEM

ATPG TESTING METHOD FOR LATCH BASED MEMORIES, FOR AREA REDUCTION

TESTING METHOD, TESTING SYSTEM, AND TESTING APPARATUS FOR SEMICONDU...

CHIP TESTING APPARATUS AND SYSTEM

MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM

TEST KEY STRUCTURE

MULTI-CHIP PACKAGE AND METHOD OF TESTING THE SAME

MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM

AT-RISK MEMORY LOCATION IDENTIFICATION AND MANAGEMENT

MEMORY DEVICE AND TEST OPERATION METHOD THEREOF

METAL ISOLATION TESTING IN THE CONTEXT OF MEMORY CELLS

Quick Configurable Universal Register for a Configurable Integrated...

SEMICONDUCTOR DEVICE AND SYSTEM INCLUDING THE SAME

SEMICONDUCTOR DEVICE

STACK TYPE SEMICONDUCTOR MEMORY AND SEMICONDUCTOR SYSTEM USING THE...

SEMICONDUCTOR PACKAGES AND DATA STORAGE DEVICES INCLUDING THE SAME

TEST PARTITIONING FOR A NON-VOLATILE MEMORY

EMBEDDED PROCESSOR

BUILT-IN SELF-TEST METHOD AND STRUCTURE

FABRICATION AND TESTING METHOD FOR NONVOLATILE MEMORY DEVICES

CONTROL SCHEME FOR 3D MEMORY IC

MEMORY SYSTEM WITH A LAYER COMPRISING A DEDICATED REDUNDANCY AREA

MEMORY DEVICE AND METHOD FOR DRIVING MEMORY DEVICE

EMBEDDED PROCESSOR

SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING A COUPLING EFFECT OF A...

EMBEDDED PROCESSOR