Logic emulation using reprogrammable logic devices

Industry

CPC
G06F17/5027

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions

Current Industry

G06F17/5027Logic emulation using reprogrammable logic devices

Industries

Patents Grantslast 30 patents

Information Patent Grant
Bandwidth test in networking System-on-Chip verification
- Patent number 10,664,566
- Issue date May 26, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic pipelining of memory circuits
- Patent number 10,664,561
- Issue date May 26, 2020
- Xilinx, Inc.
- Pradip K. Kar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent testbench and software driven verification
- Patent number 10,664,563
- Issue date May 26, 2020
- Mentor Graphics Corporation
- Debdutta Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slack time recycling
- Patent number 10,657,210
- Issue date May 19, 2020
- Mentor Graphics Corporation
- Brian Etscheid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency test in networking system-on-chip verification
- Patent number 10,657,217
- Issue date May 19, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flow control in networking system-on-chip verification
- Patent number 10,628,548
- Issue date Apr 21, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power mode-based operational capability-aware code coverage
- Patent number 10,614,193
- Issue date Apr 7, 2020
- Mentor Graphics Corporation
- Pankaj Kumar Dwivedi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient power analysis
- Patent number 10,599,794
- Issue date Mar 24, 2020
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer architecture for emulating a binary correlithm object flip...
- Patent number 10,599,795
- Issue date Mar 24, 2020
- Bank of America Corporation
- Patrick N. Lawrence
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Force/release support in emulation and formal verification
- Patent number 10,579,760
- Issue date Mar 3, 2020
- Synopsys, Inc.
- Ionut Silviu Cirjan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementation of user logic in a field progr...
- Patent number 10,579,758
- Issue date Mar 3, 2020
- Wipro Limited
- Kodavalla Vijay Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event-driven design simulation
- Patent number 10,565,335
- Issue date Feb 18, 2020
- Montana Systems Inc.
- Vivian Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Equivalency verification for hierarchical references
- Patent number 10,565,338
- Issue date Feb 18, 2020
- International Business Machines Corporation
- Ali S. El-Zein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning a system graph for circuit simulation to obtain an exa...
- Patent number 10,558,772
- Issue date Feb 11, 2020
- Worldwide Pro Ltd.
- William Wai Yan Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Array clocking in emulation
- Patent number 10,558,477
- Issue date Feb 11, 2020
- International Business Machines Corporation
- Michael J. Becht
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling real time during embedded system development
- Patent number 10,552,560
- Issue date Feb 4, 2020
- Mentor Graphics Corporation
- Lance S. P. Brooks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Array clocking in emulation
- Patent number 10,552,184
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Michael J. Becht
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Full memory logical erase for circuit verification
- Patent number 10,546,081
- Issue date Jan 28, 2020
- Mentor Graphics Corporation
- Khaled Salah Mohamed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for speeding up gate-level simulation
- Patent number 10,540,462
- Issue date Jan 21, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chih-Yuan Stephen Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock jitter emulation
- Patent number 10,528,686
- Issue date Jan 7, 2020
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power computation logic
- Patent number 10,528,690
- Issue date Jan 7, 2020
- Synopsys, Inc.
- Ching-Ping Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing-closure methodology involving clock network in hardware designs
- Patent number 10,528,697
- Issue date Jan 7, 2020
- Xilinx, Inc.
- Wei Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Traffic shaping in networking system-on-chip verification
- Patent number 10,521,544
- Issue date Dec 31, 2019
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data-dependent delay circuits
- Patent number 10,521,530
- Issue date Dec 31, 2019
- Bar-Ilan University
- Itamar Levi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
State visibility and manipulation in integrated circuits
- Patent number 10,515,165
- Issue date Dec 24, 2019
- Altera Corporation
- Michael Hutton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with reconfigurable pipelined core and algorithmic compiler
- Patent number 10,515,041
- Issue date Dec 24, 2019
- ICAT LLC
- Robert Catiller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deep insight for debug using internal equivalence visualization and...
- Patent number 10,515,170
- Issue date Dec 24, 2019
- Synopsys, Inc.
- Sudipta Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimum stage number calculation method, information processing app...
- Patent number 10,509,879
- Issue date Dec 17, 2019
- Fujitsu Limited
- Michitaka Hashimoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for reducing latency when transferring I/O betw...
- Patent number 10,509,877
- Issue date Dec 17, 2019
- Cadence Design Systems, Inc.
- Mitchell G. Poplack
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Target capture and replay in emulation
- Patent number 10,503,848
- Issue date Dec 10, 2019
- Mentor Graphics Corporation
- Krishnamurthy Suresh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HETEROGENEOUS-COMPUTING BASED EMULATOR
- Publication number 20210141868
- Publication date May 13, 2021
- International Business Machines Corporation
- Yan Heng Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPOSITIONS AND METHODS FOR IMPROVED CALIBRATION ACCURACY OF CREAT...
- Publication number 20200319210
- Publication date Oct 8, 2020
- INSTRUMENTATION LABORATORY COMPANY
- Clarke Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MAPPING FOR MEMORY, MEMORY MODULES, AND NON-VOLATILE MEMORY
- Publication number 20200278864
- Publication date Sep 3, 2020
- Micron Technology, Inc.
- Frank F. Ross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUITRY DEVELOPMENT SYSTEM, INTEGRATED CIRCUITRY DEVEL...
- Publication number 20200210534
- Publication date Jul 2, 2020
- REALTEK SEMICONDUCTOR CORPORATION
- Chihtung CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TENANT STORAGE FOR ANALYTICS WITH PUSH DOWN FILTERING
- Publication number 20200192898
- Publication date Jun 18, 2020
- AMAZON TECHNOLOGIES, INC.
- Andrew Edward CALDWELL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit capable of being automatically programmed by way...
- Publication number 20200184032
- Publication date Jun 11, 2020
- Mingling HUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE INCREMENTAL MODEL CHECKING VERIFICATION
- Publication number 20200175128
- Publication date Jun 4, 2020
- International Business Machines Corporation
- YAN HENG LU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Structural Matching for Fast Re-synthesis of Electronic Circuits
- Publication number 20200134108
- Publication date Apr 30, 2020
- The Regents of the University of California
- Rafael Possignolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COHERENT OBSERVABILITY AND CONTROLLABILITY OF OVERLAID CLOCK AND DA...
- Publication number 20200097625
- Publication date Mar 26, 2020
- Synopsys, Inc.
- Alex Rabinovitch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATION OF UNIT OPERATIONS OF A CHEMICAL PLANT FOR ACID GAS REMOVAL
- Publication number 20200089827
- Publication date Mar 19, 2020
- BASF SE
- Agnes Dittel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CYCLE ACCURATE AND CYCLE REPRODUCIBLE MEMORY FOR AN FPGA BASED HARD...
- Publication number 20200049764
- Publication date Feb 13, 2020
- International Business Machines Corporation
- Sameh W. Asaad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR OPTIMIZING CIRCUIT PERFORMANCE VIA CONFIGURABLE CLOCK S...
- Publication number 20200042033
- Publication date Feb 6, 2020
- Altera Corporation
- Mark Bourgeault
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FORCE/RELEASE SUPPORT IN EMULATION AND FORMAL VERIFICATION
- Publication number 20200034499
- Publication date Jan 30, 2020
- Synopsys, Inc.
- Ionut Silviu Cirjan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARRAY CLOCKING IN EMULATION
- Publication number 20200019422
- Publication date Jan 16, 2020
- International Business Machines Corporation
- Michael J. Becht
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING SOC WITH PORTABLE SCENARIO MODELS AND AT DIFFERENT LEVELS
- Publication number 20190391204
- Publication date Dec 26, 2019
- Breker Verification Systems
- Adnan Hamid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIFIED GEOMETRIES FOR DYNAMIC HIGH-PERFORMANCE COMPUTING
- Publication number 20190392102
- Publication date Dec 26, 2019
- Xplicit Computing, Inc.
- Graham Jaffe Orr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVENT-DRIVEN DESIGN SIMULATION
- Publication number 20190384598
- Publication date Dec 19, 2019
- Montana Systems Inc.
- VIVIAN CHOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL SOLID STATE STORAGE SYSTEM WITH SOLID STATE STORAGE ERROR E...
- Publication number 20190347047
- Publication date Nov 14, 2019
- SEAGATE TECHNOLOGY LLC
- Swapnil Rameshrao Khandare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR LSI DESIGN DEVICE AND DESIGN METHOD
- Publication number 20190332727
- Publication date Oct 31, 2019
- Hitachi, Ltd
- Takumi UEZONO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduling Of Scenario Models For Execution Within Different Comput...
- Publication number 20190317147
- Publication date Oct 17, 2019
- Breker Verification Systems
- Adnan Hamid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETEROGENEOUS MINIATURIZATION PLATFORM
- Publication number 20190311082
- Publication date Oct 10, 2019
- International Business Machines Corporation
- Qianwen Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IMPLEMENTATION OF USER LOGIC IN A FIELD PROGR...
- Publication number 20190303519
- Publication date Oct 3, 2019
- Wipro Limited
- Kodavalla Vijay Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adjustable Integrated Circuits and Methods for Designing the Same
- Publication number 20190286772
- Publication date Sep 19, 2019
- Ambient Scientific Inc.
- Gajendra Prasad SINGH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVENT-DRIVEN DESIGN SIMULATION
- Publication number 20190286775
- Publication date Sep 19, 2019
- Montana Systems Inc.
- VIVIAN CHOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION MAPPING ON HARDENED NETWORK-ON-CHIP (NOC) OF FIELD-PROG...
- Publication number 20190266089
- Publication date Aug 29, 2019
- NetSpeed Systems, Inc.
- Sailesh KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BACKBONE NETWORK-ON-CHIP (NOC) FOR FIELD-PROGRAMMABLE GATE ARRAY (F...
- Publication number 20190266088
- Publication date Aug 29, 2019
- NetSpeed Systems, Inc.
- Sailesh KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT
- Publication number 20190253057
- Publication date Aug 15, 2019
- NEC Corporation
- Xu BAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
JUST-IN-TIME HARDWARE FOR FIELD PROGRAMMABLE GATE ARRAYS
- Publication number 20190236231
- Publication date Aug 1, 2019
- VMware, Inc.
- Eric SCHKUFZA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
JUST-IN-TIME HARDWARE FOR FIELD PROGRAMMABLE GATE ARRAYS
- Publication number 20190235893
- Publication date Aug 1, 2019
- VMware, Inc.
- Eric SCHKUFZA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
JUST-IN-TIME HARDWARE FOR FIELD PROGRAMMABLE GATE ARRAYS
- Publication number 20190236229
- Publication date Aug 1, 2019
- VMware, Inc.
- Eric SCHKUFZA
- G06 - COMPUTING CALCULATING COUNTING

Logic emulation using reprogrammable logic devices

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Bandwidth test in networking System-on-Chip verification

Automatic pipelining of memory circuits

Concurrent testbench and software driven verification

Slack time recycling

Latency test in networking system-on-chip verification

Flow control in networking system-on-chip verification

Power mode-based operational capability-aware code coverage

Efficient power analysis

Computer architecture for emulating a binary correlithm object flip...

Force/release support in emulation and formal verification

Method and system for implementation of user logic in a field progr...

Event-driven design simulation

Equivalency verification for hierarchical references

Partitioning a system graph for circuit simulation to obtain an exa...

Array clocking in emulation

Controlling real time during embedded system development

Array clocking in emulation

Full memory logical erase for circuit verification

Method and apparatus for speeding up gate-level simulation

Clock jitter emulation

Power computation logic

Timing-closure methodology involving clock network in hardware designs

Traffic shaping in networking system-on-chip verification

Data-dependent delay circuits

State visibility and manipulation in integrated circuits

Processor with reconfigurable pipelined core and algorithmic compiler

Deep insight for debug using internal equivalence visualization and...

Optimum stage number calculation method, information processing app...

Systems and methods for reducing latency when transferring I/O betw...

Target capture and replay in emulation

Patents Applicationslast 30 patents

HETEROGENEOUS-COMPUTING BASED EMULATOR

COMPOSITIONS AND METHODS FOR IMPROVED CALIBRATION ACCURACY OF CREAT...

MEMORY MAPPING FOR MEMORY, MEMORY MODULES, AND NON-VOLATILE MEMORY

INTEGRATED CIRCUITRY DEVELOPMENT SYSTEM, INTEGRATED CIRCUITRY DEVEL...

MULTI-TENANT STORAGE FOR ANALYTICS WITH PUSH DOWN FILTERING

Integrated circuit capable of being automatically programmed by way...

HARDWARE INCREMENTAL MODEL CHECKING VERIFICATION

Structural Matching for Fast Re-synthesis of Electronic Circuits

COHERENT OBSERVABILITY AND CONTROLLABILITY OF OVERLAID CLOCK AND DA...

SIMULATION OF UNIT OPERATIONS OF A CHEMICAL PLANT FOR ACID GAS REMOVAL

CYCLE ACCURATE AND CYCLE REPRODUCIBLE MEMORY FOR AN FPGA BASED HARD...

METHODS FOR OPTIMIZING CIRCUIT PERFORMANCE VIA CONFIGURABLE CLOCK S...

FORCE/RELEASE SUPPORT IN EMULATION AND FORMAL VERIFICATION

ARRAY CLOCKING IN EMULATION

TESTING SOC WITH PORTABLE SCENARIO MODELS AND AT DIFFERENT LEVELS

UNIFIED GEOMETRIES FOR DYNAMIC HIGH-PERFORMANCE COMPUTING

EVENT-DRIVEN DESIGN SIMULATION

VIRTUAL SOLID STATE STORAGE SYSTEM WITH SOLID STATE STORAGE ERROR E...

SEMICONDUCTOR LSI DESIGN DEVICE AND DESIGN METHOD

Scheduling Of Scenario Models For Execution Within Different Comput...

HETEROGENEOUS MINIATURIZATION PLATFORM

METHOD AND SYSTEM FOR IMPLEMENTATION OF USER LOGIC IN A FIELD PROGR...

Adjustable Integrated Circuits and Methods for Designing the Same

EVENT-DRIVEN DESIGN SIMULATION

APPLICATION MAPPING ON HARDENED NETWORK-ON-CHIP (NOC) OF FIELD-PROG...

BACKBONE NETWORK-ON-CHIP (NOC) FOR FIELD-PROGRAMMABLE GATE ARRAY (F...

INTEGRATED CIRCUIT

JUST-IN-TIME HARDWARE FOR FIELD PROGRAMMABLE GATE ARRAYS

JUST-IN-TIME HARDWARE FOR FIELD PROGRAMMABLE GATE ARRAYS

JUST-IN-TIME HARDWARE FOR FIELD PROGRAMMABLE GATE ARRAYS