of variable length instructions

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CPC
G06F9/30149

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/30149of variable length instructions

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Patents Grantslast 30 patents

Information Patent Grant
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- G06 - COMPUTING CALCULATING COUNTING

of variable length instructions

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Tracking streaming engine vector predicates to control processor ex...

Systems, methods, and apparatuses for tile matrix multiplication an...

Systems, methods, and apparatuses for tile transpose

Method and apparatus for vector permutation

Systems, methods, and apparatuses for matrix operations

Method and apparatus for permuting streamed data elements

Vector friendly instruction format and execution thereof

Highly integrated scalable, flexible DSP megamodule architecture

Method and apparatus for implied bit handling in floating point mul...

Systems, methods, and apparatus for matrix move

Method and apparatus for vector sorting

Method and apparatus for dual issue multiply instructions

Method and apparatus for vector based matrix multiplication

Processor having a register file, processing unit, and instruction...

Systems, methods, and apparatuses for tile store

Reconfigurable crypto-processor

Stateful microcode branching

Systems and methods for performing instructions to transform matric...

Stream data unit with multiple head registers

Method and apparatus for dual multiplication units in a data path

Encoding and decoding variable length instructions

Systems, methods, and apparatus for tile configuration

Method and apparatus for vector sorting using vector permutation logic

Dynamic fragmented address space layout randomization

Method and system for executing new instructions

Speculative usage of parallel decode units

Tracking streaming engine vector predicates to control processor ex...

Computing machine using a matrix space and matrix pointer registers...

Vector friendly instruction format and execution thereof

Address generation method, related apparatus, and storage medium

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR VECTOR PERMUTATION

PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT

METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS

Vector Based Matrix Multiplication

SORTING VECTOR ELEMENTS USING A COUNT VALUE

METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MUL...

SYSTEMS, METHODS, AND APPPARATUS FOR MATRIX MOVE

Method and Apparatus for Dual Issue Multiply Instructions

Parallel Decode Instruction Set Computer Architecture with Variable...

EFFICIENT FORWARD-ERROR-CORRECTION PROTOCOL BASED ON XOR OPERATIONS...

SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE

STREAM DATA UNIT WITH MULTIPLE HEAD REGISTERS

Multiple Multiplication Units in a Data Path

SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX OPERATIONS

Predicting a Vector Length Associated with a Configuration Instruction

SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX ADD, SUBTRACT, AND MUL...

SYSTEMS, METHODS, AND APPARATUS FOR TILE CONFIGURATION

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

Method and Apparatus for Vector Sorting using Vector Permutation Logic

Computing Machine Using a Matrix Space And Matrix Pointer Registers...

Computing System with Hardware and Methods for Handling Immediate O...

TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EX...

PARALLEL PROCESSING ARCHITECTURE WITH MEMORY BLOCK TRANSFERS

Method and Apparatus for Dual Issue Multiply Instructions

SYSTEMS AND METHODS FOR PERFORMING INSTRUCTIONS TO TRANSFORM MATRIC...

Method and Apparatus for Vector Based Finite Impulse Response (FIR)...

DATA PROCESSING APPARATUS HAVING STREAMING ENGINE WITH READ AND REA...

VARIABLE-LENGTH INSTRUCTION STEERING TO INSTRUCTION DECODE CLUSTERS

METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS

SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD