On-chip cache and off-chip main memory

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F15/00Digital computers in general Data processing equipment in general

Current Industry

G06F15/7846On-chip cache and off-chip main memory

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Patents Grantslast 30 patents

Information Patent Grant
Architecture to support color scheme-based synchronization for mach...
- Patent number 11,995,463
- Issue date May 28, 2024
- MARVELL ASIA PTE. LTD.
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture to support color scheme-based synchronization for mach...
- Patent number 11,934,863
- Issue date Mar 19, 2024
- MARVELL ASIA PTE. LTD.
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture to support synchronization between core and inference...
- Patent number 11,687,837
- Issue date Jun 27, 2023
- MARVELL ASIA PTE. LTD.
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture to support synchronization between core and inference...
- Patent number 11,403,561
- Issue date Aug 2, 2022
- MARVELL ASIA PTE. LTD.
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture to support color scheme-based synchronization for mach...
- Patent number 11,016,801
- Issue date May 25, 2021
- Marvell Asia Pte, Ltd.
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Caching for heterogeneous processors
- Patent number 11,016,895
- Issue date May 25, 2021
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture to support synchronization between core and inference...
- Patent number 10,929,779
- Issue date Feb 23, 2021
- Marvell Asia Pte, Ltd.
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data read-write scheduler and reservation station for vector operat...
- Patent number 10,521,228
- Issue date Dec 31, 2019
- Cambricon Technologies Corporation Limited
- Dong Han
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Caching for heterogeneous processors
- Patent number 10,339,061
- Issue date Jul 2, 2019
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-layer memory for a computing platform
- Patent number 10,019,361
- Issue date Jul 10, 2018
- Imec VZW
- Francky Catthoor
- G11 - INFORMATION STORAGE
Information Patent Grant
Caching for heterogeneous processors
- Patent number 9,965,393
- Issue date May 8, 2018
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Authenticated control stacks
- Patent number 9,672,351
- Issue date Jun 6, 2017
- QUALCOMM Incorporated
- Arvind Krishnaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dense hyper IO digital retention
- Patent number 9,628,108
- Issue date Apr 18, 2017
- Symbolic IO Corporation
- Brian M. Ignomirello
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Caching for heterogeneous processors
- Patent number 9,235,550
- Issue date Jan 12, 2016
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread optimized multiprocessor architecture
- Patent number 8,984,256
- Issue date Mar 17, 2015
- Russell Fish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread optimized multiprocessor architecture
- Patent number 8,977,836
- Issue date Mar 10, 2015
- Russell H. Fish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Caching for heterogeneous processors
- Patent number 8,402,222
- Issue date Mar 19, 2013
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deterministic finite automata (DFA) processing
- Patent number 8,392,590
- Issue date Mar 5, 2013
- Cavium, Inc.
- Gregg A. Bouchard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Heterogeneous processors sharing a common cache
- Patent number 8,156,285
- Issue date Apr 10, 2012
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous processors sharing a common cache
- Patent number 7,577,792
- Issue date Aug 18, 2009
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Proximity communication-based off-chip cache memory architectures
- Patent number 7,496,712
- Issue date Feb 24, 2009
- Sun Microsystems, Inc.
- Brian W. O'Krafka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for parallel execution of data generation tasks
- Patent number 7,333,114
- Issue date Feb 19, 2008
- Microsoft Corporation
- Jeffrey A. Andrews
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable memory system for embedded processors
- Patent number 7,281,228
- Issue date Oct 9, 2007
- Infineon Technologies AG
- Klaus J. Oberlaender
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of enhancing efficiency and utilization of memory...
- Patent number 7,149,867
- Issue date Dec 12, 2006
- SRC Computers, Inc.
- Daniel Poznanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microcomputer
- Patent number 7,136,965
- Issue date Nov 14, 2006
- NEC Corporation
- Manabu Koga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of hierarchical caching of configuration data having dataflo...
- Patent number 6,990,555
- Issue date Jan 24, 2006
- Pact XPP Technologies AG
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method frame storage using multiple memory circuits
- Patent number 6,961,843
- Issue date Nov 1, 2005
- Sun Microsystems, Inc.
- James Michael O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method frame storage using multiple memory circuits
- Patent number 6,950,923
- Issue date Sep 27, 2005
- Sun Microsystems, Inc.
- James Michael O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus arbitration method employing a table of slots suitably distribu...
- Patent number 6,895,459
- Issue date May 17, 2005
- Analog Devices, Inc.
- Rainer R. Hadwiger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for parallel execution of data generation tasks
- Patent number 6,862,027
- Issue date Mar 1, 2005
- Microsoft Corp.
- Jeffrey A. Andrews
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ARCHITECTURE TO SUPPORT SYNCHRONIZATION BETWEEN CORE AND INFERENCE...
- Publication number 20220374774
- Publication date Nov 24, 2022
- Marvell Asia Pte Ltd.
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHING FOR HETEROGENEOUS PROCESSORS
- Publication number 20190114261
- Publication date Apr 18, 2019
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DENSE HYPER IO DIGITAL RETENTION
- Publication number 20160218737
- Publication date Jul 28, 2016
- Symbolic IO Corporation
- Brian M. Ignomirello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHING FOR HETEROGENEOUS PROCESSORS
- Publication number 20150081976
- Publication date Mar 19, 2015
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHING FOR HETEROGENEOUS PROCESSORS
- Publication number 20130275681
- Publication date Oct 17, 2013
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETEROGENEOUS PROCESSORS SHARING A COMMON CACHE
- Publication number 20120215984
- Publication date Aug 23, 2012
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Heterogeneous processors sharing a common cache
- Publication number 20100011167
- Publication date Jan 14, 2010
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Thread Optimized Multiprocessor Architecture
- Publication number 20080320277
- Publication date Dec 25, 2008
- Russell H. Fish, III
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION FOLDING FOR A STACK-BASED MACHINE
- Publication number 20070277021
- Publication date Nov 29, 2007
- SUN MICROSYSTEMS, INC.
- James Michael O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Thread optimized multiprocessor architecture
- Publication number 20070192568
- Publication date Aug 16, 2007
- Russell H. Fish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Superior cache processor landing zone to support multiple processors
- Publication number 20070067571
- Publication date Mar 22, 2007
- Claus Pribbernow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Correlated logic micro cache
- Publication number 20070005893
- Publication date Jan 4, 2007
- Intel Corporation
- John W. Mates
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Heterogeneous processors sharing a common cache
- Publication number 20060112227
- Publication date May 25, 2006
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Heterogeneous processors sharing a common cache
- Publication number 20060112226
- Publication date May 25, 2006
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for parallel execution of data generation tasks
- Publication number 20060095672
- Publication date May 4, 2006
- Microsoft Corporation
- Jeffrey A. Andrews
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Deterministic finite automata (DFA) processing
- Publication number 20060069872
- Publication date Mar 30, 2006
- Gregg A. Bouchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method frame storage using multiple memory circuits
- Publication number 20050267996
- Publication date Dec 1, 2005
- James Michael O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF HIERARCHICAL CACHING OF CONFIGURATION DATA HAVING DATAFLO...
- Publication number 20050257009
- Publication date Nov 17, 2005
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable memory system for embedded processors
- Publication number 20050177697
- Publication date Aug 11, 2005
- Infineon Technologies, Inc.
- Klaus J. Oberlaender
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for parallel execution of data generation tasks
- Publication number 20050122339
- Publication date Jun 9, 2005
- Microsoft Corporation
- Jeffrey A. Andrews
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache bank interface unit
- Publication number 20050044320
- Publication date Feb 24, 2005
- SUN MICROSYSTEMS, INC.
- Kunle A. Olukotun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for parallel execution of data generation tasks
- Publication number 20040263519
- Publication date Dec 30, 2004
- Microsoft Corporation
- Jeffrey A. Andrews
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method of enhancing efficiency and utilization of memory...
- Publication number 20040260884
- Publication date Dec 23, 2004
- Daniel Poznanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and methods for linking a processor and cache
- Publication number 20040225830
- Publication date Nov 11, 2004
- Eric DeLano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of hierarchical caching of configuration data having dataflo...
- Publication number 20040153608
- Publication date Aug 5, 2004
- Martin Vorbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bus architecture and shared bus arbitration method for a communicat...
- Publication number 20040049293
- Publication date Mar 11, 2004
- Analog Devices, Inc.
- Rainer R. Hadwiger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method frame storage using multiple memory circuits
- Publication number 20030200351
- Publication date Oct 23, 2003
- Sun Microsystems, Inc.
- James Michael O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital signal processor architecture for high computation speed
- Publication number 20030196072
- Publication date Oct 16, 2003
- Murali S. Chinnakonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and methods for interfacing with cache memory
- Publication number 20030167379
- Publication date Sep 4, 2003
- Donald Charles Soltis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method frame storage using multiple memory circuits
- Publication number 20030115238
- Publication date Jun 19, 2003
- Sun Microsystems, Inc.
- James Michael O'Connor
- G06 - COMPUTING CALCULATING COUNTING

On-chip cache and off-chip main memory

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Architecture to support color scheme-based synchronization for mach...

Architecture to support color scheme-based synchronization for mach...

Architecture to support synchronization between core and inference...

Architecture to support synchronization between core and inference...

Architecture to support color scheme-based synchronization for mach...

Caching for heterogeneous processors

Architecture to support synchronization between core and inference...

Data read-write scheduler and reservation station for vector operat...

Caching for heterogeneous processors

Low-layer memory for a computing platform

Caching for heterogeneous processors

Authenticated control stacks

Method and apparatus for dense hyper IO digital retention

Caching for heterogeneous processors

Thread optimized multiprocessor architecture

Thread optimized multiprocessor architecture

Caching for heterogeneous processors

Deterministic finite automata (DFA) processing

Heterogeneous processors sharing a common cache

Heterogeneous processors sharing a common cache

Proximity communication-based off-chip cache memory architectures

System and method for parallel execution of data generation tasks

Configurable memory system for embedded processors

System and method of enhancing efficiency and utilization of memory...

Microcomputer

Method of hierarchical caching of configuration data having dataflo...

Method frame storage using multiple memory circuits

Method frame storage using multiple memory circuits

Bus arbitration method employing a table of slots suitably distribu...

System and method for parallel execution of data generation tasks

Patents Applicationslast 30 patents

ARCHITECTURE TO SUPPORT SYNCHRONIZATION BETWEEN CORE AND INFERENCE...

CACHING FOR HETEROGENEOUS PROCESSORS

METHOD AND APPARATUS FOR DENSE HYPER IO DIGITAL RETENTION

CACHING FOR HETEROGENEOUS PROCESSORS

CACHING FOR HETEROGENEOUS PROCESSORS

HETEROGENEOUS PROCESSORS SHARING A COMMON CACHE

Heterogeneous processors sharing a common cache

Thread Optimized Multiprocessor Architecture

INSTRUCTION FOLDING FOR A STACK-BASED MACHINE

Thread optimized multiprocessor architecture

Superior cache processor landing zone to support multiple processors

Correlated logic micro cache

Heterogeneous processors sharing a common cache

Heterogeneous processors sharing a common cache

System and method for parallel execution of data generation tasks

Deterministic finite automata (DFA) processing

Method frame storage using multiple memory circuits

METHOD OF HIERARCHICAL CACHING OF CONFIGURATION DATA HAVING DATAFLO...

Configurable memory system for embedded processors

System and method for parallel execution of data generation tasks

Cache bank interface unit

System and method for parallel execution of data generation tasks

System and method of enhancing efficiency and utilization of memory...

Apparatus and methods for linking a processor and cache

Method of hierarchical caching of configuration data having dataflo...

Bus architecture and shared bus arbitration method for a communicat...

Method frame storage using multiple memory circuits

Digital signal processor architecture for high computation speed

Apparatus and methods for interfacing with cache memory

Method frame storage using multiple memory circuits