overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation

Industry

CPC
G06F7/5336

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F7/5336overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation

Industries

Patents Grantslast 30 patents

Information Patent Grant
High radix subset code multiplier architecture
- Patent number 11,010,134
- Issue date May 18, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor for neural network computing and processing method o...
- Patent number 11,003,445
- Issue date May 11, 2021
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Jing Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with booth multiplication
- Patent number 10,776,108
- Issue date Sep 15, 2020
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Jing Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with dynamically adjustable bit width for processing...
- Patent number 10,776,109
- Issue date Sep 15, 2020
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Jing Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with booth multiplication
- Patent number 10,754,646
- Issue date Aug 25, 2020
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Jing Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplication of first and second operands using redundant represe...
- Patent number 9,703,531
- Issue date Jul 11, 2017
- ARM Limited
- David Raymond Lutz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing apparatus and method for multiplying floating point...
- Patent number 9,483,232
- Issue date Nov 1, 2016
- ARM Limited
- David Raymond Lutz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementation of negation in a multiplication operation without po...
- Patent number 8,892,621
- Issue date Nov 18, 2014
- LSI Corporation
- Leonid Dubrovin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel redundant decimal fused-multiply-add circuit
- Patent number 8,805,917
- Issue date Aug 12, 2014
- SilMinds, LLC, Egypt
- Amira Mohamed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Negative two's complement processor for windowing in harmonic analysis
- Patent number 8,099,447
- Issue date Jan 17, 2012
- Earl Eugene Swartzlander, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Montgomery modular multiplier
- Patent number 7,805,478
- Issue date Sep 28, 2010
- Samsung Electronics Co., Ltd.
- Hee Kwan Son
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encoder for a multiplier
- Patent number 7,519,648
- Issue date Apr 14, 2009
- Samsung Electronics Co., Ltd.
- Young-chul Rhee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extendable squarer and operation method for processing digital signals
- Patent number 7,373,370
- Issue date May 13, 2008
- Chung Shan Institute of Science and Technology, Armaments Bureau, M.N.D.
- Shi-Ho Tien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Smaller and lower power static mux circuitry in generating multipli...
- Patent number 7,308,470
- Issue date Dec 11, 2007
- Intel Corporation
- Kenneth Y. Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and device for performing operations involving multiplicatio...
- Patent number 7,308,471
- Issue date Dec 11, 2007
- Arithmatica Limited
- Dmitriy Rumynin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast multiplication circuits
- Patent number 7,296,049
- Issue date Nov 13, 2007
- Intel Corporation
- Erik Højsted
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Higher radix multiplier with simplified partial product generator
- Patent number 7,194,498
- Issue date Mar 20, 2007
- Southern Methodist University
- David William Matula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switching activity reduced coding for low-power digital signal proc...
- Patent number 7,177,894
- Issue date Feb 13, 2007
- Broadcom Corporation
- Christian Lutkemeyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for variable radix scalable modular multiplic...
- Patent number 7,174,015
- Issue date Feb 6, 2007
- State of Oregon Acting by and through the State Board of Higher Education on...
- Çetin K. Koç
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noise invariant circuits, systems and methods
- Patent number 6,950,840
- Issue date Sep 27, 2005
- Cirrus Logic, Inc.
- Edwin De Angel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noise invariant circuits, systems and methods
- Patent number 6,901,423
- Issue date May 31, 2005
- Cirrus Logic, Inc.
- Edwin De Angel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for digital multiplication using redundant binary arithmetic
- Patent number 6,816,877
- Issue date Nov 9, 2004
- Chang University of Science and Technology Foundation
- Hong-june Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for increasing performance of multipliers util...
- Patent number 6,742,011
- Issue date May 25, 2004
- Hewlett-Packard Development Company, L.P.
- Glenn T Colon-Bonet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Complex number multiplier circuit
- Patent number 6,411,979
- Issue date Jun 25, 2002
- Agere Systems Guardian Corp.
- Alan Joel Greenberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast determination of carry inputs from lower order product for rad...
- Patent number 6,131,107
- Issue date Oct 10, 2000
- Digital Equipment Corporation
- Gilbert M. Wolrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast carry-sum form booth encoder
- Patent number 5,944,776
- Issue date Aug 31, 1999
- Sun Microsystems, Inc.
- Song Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast determination of carry inputs from lower order product for rad...
- Patent number 5,889,692
- Issue date Mar 30, 1999
- Digital Equipment Corporation
- Gilbert M. Wolrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Table compression using bipartite tables
- Patent number 5,862,059
- Issue date Jan 19, 1999
- National Semiconductor Corporation
- David William Matula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-timed multiplier array
- Patent number 5,740,094
- Issue date Apr 14, 1998
- International Business Machines Corporation
- Peter Juergen Klim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Polynomial multiplier apparatus and method
- Patent number 5,734,600
- Issue date Mar 31, 1998
- International Business Machines Corporation
- James N. Dieffenderfer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
COMMUTATIVE 1ULP HARDWARE MULTIPLIER
- Publication number 20240311083
- Publication date Sep 19, 2024
- Intel Corporation
- Theo Alan Drane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE AND COMPUTING DEVICE USING THE SAME
- Publication number 20200257500
- Publication date Aug 13, 2020
- Samsung Electronics Co., Ltd.
- GA RAM KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROPROCESSOR WITH BOOTH MULTIPLICATION
- Publication number 20190227770
- Publication date Jul 25, 2019
- Shanghai Zhaoxin Semiconductor Co., Ltd.
- Jing CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementation of Negation in a Multiplication Operation Without Po...
- Publication number 20130159367
- Publication date Jun 20, 2013
- LSI Corporation
- Leonid Dubrovin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL REDUNDANT DECIMAL FUSED-MULTIPLY-ADD CIRCUIT
- Publication number 20120011187
- Publication date Jan 12, 2012
- SILMINDS, LLC, EGYPT
- Amira Mohamed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH RADIX DIGITAL MULTIPLIER
- Publication number 20110264719
- Publication date Oct 27, 2011
- Audioasics A/S
- Mikael Mortensen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Negative two's complement processor for windowing in harmonic analysis
- Publication number 20110040816
- Publication date Feb 17, 2011
- Earl Eugene Swartzlander, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Negative two's complement numbering system
- Publication number 20070214204
- Publication date Sep 13, 2007
- Earl Swartzlander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Extendable squarer and method of square operation
- Publication number 20060020652
- Publication date Jan 26, 2006
- Shi-Ho Tien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modular-multiplication computing unit and information processing unit
- Publication number 20060008080
- Publication date Jan 12, 2006
- NEC Electronics Corporation
- Kunihiko Higashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiplier sign extension method and architecture
- Publication number 20050223054
- Publication date Oct 6, 2005
- Yu-Cheng Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Montgomery modular multiplier
- Publication number 20050198093
- Publication date Sep 8, 2005
- Hee-Kwan Son
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Encoder for a multiplier
- Publication number 20050182814
- Publication date Aug 18, 2005
- Young-chul Rhee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Smaller and lower power static mux circuitry in generating multipli...
- Publication number 20050125478
- Publication date Jun 9, 2005
- Intel Corporation
- Kenneth Y. Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Switching activity reduced coding for low-power digital signal proc...
- Publication number 20050050133
- Publication date Mar 3, 2005
- Christian Lutkemeyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Montgomery modular multiplier and method thereof using carry save a...
- Publication number 20040252829
- Publication date Dec 16, 2004
- Hee-Kwan Son
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and device for performing operations involving multiplicatio...
- Publication number 20040225705
- Publication date Nov 11, 2004
- Dmitriy Rumynin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Noise invariant circuits, systems and methods
- Publication number 20040199563
- Publication date Oct 7, 2004
- Edwin De Angel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelined multiplicative division with IEEE rounding
- Publication number 20040128338
- Publication date Jul 1, 2004
- Guy Even
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fast multiplication circuits
- Publication number 20030182343
- Publication date Sep 25, 2003
- Erik Hojsted
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Higher radix multiplier with simplified partial product generator
- Publication number 20030018678
- Publication date Jan 23, 2003
- David William Matula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for digital multiplication using redundant bin...
- Publication number 20020103840
- Publication date Aug 1, 2002
- Hong-June Park
- G06 - COMPUTING CALCULATING COUNTING

overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

High radix subset code multiplier architecture

Microprocessor for neural network computing and processing method o...

Microprocessor with booth multiplication

Microprocessor with dynamically adjustable bit width for processing...

Microprocessor with booth multiplication

Multiplication of first and second operands using redundant represe...

Data processing apparatus and method for multiplying floating point...

Implementation of negation in a multiplication operation without po...

Parallel redundant decimal fused-multiply-add circuit

Negative two's complement processor for windowing in harmonic analysis

Montgomery modular multiplier

Encoder for a multiplier

Extendable squarer and operation method for processing digital signals

Smaller and lower power static mux circuitry in generating multipli...

Method and device for performing operations involving multiplicatio...

Fast multiplication circuits

Higher radix multiplier with simplified partial product generator

Switching activity reduced coding for low-power digital signal proc...

Methods and apparatus for variable radix scalable modular multiplic...

Noise invariant circuits, systems and methods

Noise invariant circuits, systems and methods

Apparatus for digital multiplication using redundant binary arithmetic

Apparatus and method for increasing performance of multipliers util...

Complex number multiplier circuit

Fast determination of carry inputs from lower order product for rad...

Fast carry-sum form booth encoder

Fast determination of carry inputs from lower order product for rad...

Table compression using bipartite tables

Self-timed multiplier array

Polynomial multiplier apparatus and method

Patents Applicationslast 30 patents

COMMUTATIVE 1ULP HARDWARE MULTIPLIER

MEMORY DEVICE AND COMPUTING DEVICE USING THE SAME

MICROPROCESSOR WITH BOOTH MULTIPLICATION

Implementation of Negation in a Multiplication Operation Without Po...

PARALLEL REDUNDANT DECIMAL FUSED-MULTIPLY-ADD CIRCUIT

HIGH RADIX DIGITAL MULTIPLIER

Negative two's complement processor for windowing in harmonic analysis

Negative two's complement numbering system

Extendable squarer and method of square operation

Modular-multiplication computing unit and information processing unit

Multiplier sign extension method and architecture

Montgomery modular multiplier

Encoder for a multiplier

Smaller and lower power static mux circuitry in generating multipli...

Switching activity reduced coding for low-power digital signal proc...

Montgomery modular multiplier and method thereof using carry save a...

Method and device for performing operations involving multiplicatio...

Noise invariant circuits, systems and methods

Pipelined multiplicative division with IEEE rounding

Fast multiplication circuits

Higher radix multiplier with simplified partial product generator

Apparatus and method for digital multiplication using redundant bin...