Pipeline control instructions

Industry

CPC
G06F9/30079

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

Current Industry

G06F9/30079Pipeline control instructions

Industries

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Sparse data handling and buffer sharing to reduce memory allocation...
- Patent number 12,153,900
- Issue date Nov 26, 2024
- Microsoft Technology Licensing, LLC
- Gary Shon Katzenberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global coherence operations
- Patent number 12,141,601
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence shared state suppression
- Patent number 12,135,646
- Issue date Nov 5, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for automated prediction and detection of compone...
- Patent number 12,105,579
- Issue date Oct 1, 2024
- Texas Tech University System
- Dy D. Le
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device for performing in-memory processing
- Patent number 12,099,839
- Issue date Sep 24, 2024
- Samsung Electronics Co., Ltd.
- Yuhwan Ro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,099,461
- Issue date Sep 24, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller, information processing apparatus, and informatio...
- Patent number 12,099,413
- Issue date Sep 24, 2024
- Fujitsu Limited
- Yasuhiro Kitamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression techniques
- Patent number 12,093,210
- Issue date Sep 17, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor operation scheduling for deterministic latency
- Patent number 12,079,155
- Issue date Sep 3, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
NPU implemented for fusion-artificial neural network to process het...
- Patent number 12,077,185
- Issue date Sep 3, 2024
- DEEPX CO., LTD.
- Lok Won Kim
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Cache line demote infrastructure for multi-processor pipelines
- Patent number 12,066,939
- Issue date Aug 20, 2024
- Intel Corporation
- Rahul R. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,066,975
- Issue date Aug 20, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tag update bus for updated coherence state
- Patent number 12,056,051
- Issue date Aug 6, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo-random way selection
- Patent number 12,045,644
- Issue date Jul 23, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rescheduling a failed memory request in a processor
- Patent number 12,020,064
- Issue date Jun 25, 2024
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile architecture for graphics operations
- Patent number 12,013,808
- Issue date Jun 18, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipeline arbitration
- Patent number 12,014,206
- Issue date Jun 18, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for efficient programmable instructions in com...
- Patent number 12,008,371
- Issue date Jun 11, 2024
- Advanced Micro Devices, Inc.
- Andrew G. Kegel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processors and graphics processing units having dot produc...
- Patent number 12,007,935
- Issue date Jun 11, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management for detecting cross tile access provid...
- Patent number 11,995,029
- Issue date May 28, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing pipeline with zero loop overhead
- Patent number 11,989,554
- Issue date May 21, 2024
- Intel Corporation
- Kameran Azadet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data pipeline controller
- Patent number 11,983,189
- Issue date May 14, 2024
- AT&T Intellectual Property I, L.P.
- James Fan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calculation method and related product
- Patent number 11,983,534
- Issue date May 14, 2024
- Cambricon (Xi'an) Semiconductor Co., Ltd.
- Tianshi Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processors and graphics processing units having dot produc...
- Patent number 11,954,063
- Issue date Apr 9, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic memory reconfiguration
- Patent number 11,954,062
- Issue date Apr 9, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipeline architecture for bitwise multiplier-accumulator (MAC)
- Patent number 11,941,407
- Issue date Mar 26, 2024
- GSI Technology Inc.
- Avidan Akerib
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
External exchange connectivity
- Patent number 11,940,940
- Issue date Mar 26, 2024
- Graphcore Limited
- Daniel Wilkinson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assistance for hardware prefetch in cache access
- Patent number 11,934,342
- Issue date Mar 19, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE FOR PERFORMING IN-MEMORY PROCESSING
- Publication number 20240419445
- Publication date Dec 19, 2024
- Samsung Electronics Co., Ltd.
- Yuhwan RO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION TECHNIQUES
- Publication number 20240403259
- Publication date Dec 5, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS, NPU AND CHIPSET IMPLEMENTED FOR FUSION NEURAL NETWORK
- Publication number 20240367681
- Publication date Nov 7, 2024
- DEEPX CO., LTD.
- Lok Won KIM
- B60 - VEHICLES IN GENERAL
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD
- Publication number 20240345839
- Publication date Oct 17, 2024
- Intel Corporation
- Kameran Azadet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO-RANDOM WAY SELECTION
- Publication number 20240345868
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG UPDATE BUS FOR UPDATED COHERENCE STATE
- Publication number 20240345956
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED USER MODE PROCESSING
- Publication number 20240320042
- Publication date Sep 26, 2024
- ADVANCED MICRO DEVICES, INC.
- Rex Eldon MCCRARY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20240320184
- Publication date Sep 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PIPELINE CONTROLLER
- Publication number 20240296169
- Publication date Sep 5, 2024
- AT&T INTELLECTUAL PROPERTY I, L.P.
- James Fan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Control to Preserve Register Data
- Publication number 20240289282
- Publication date Aug 29, 2024
- Apple Inc.
- Jonathan M. Redshaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINE ARBITRATION
- Publication number 20240281278
- Publication date Aug 22, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20240256483
- Publication date Aug 1, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BACKWARD COMPATIBILITY TESTING OF SOFTWARE IN A MODE THAT ATTEMPTS...
- Publication number 20240211380
- Publication date Jun 27, 2024
- Sony Interactive Entertainment LLC
- Mark Evan Cerny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID VIRTUAL GPU CO-SCHEDULING
- Publication number 20240202025
- Publication date Jun 20, 2024
- Intel Corporation
- Yan Zhao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINE ARCHITECTURE FOR BITWISE MULTIPLIER-ACCUMULATOR (MAC)
- Publication number 20240192962
- Publication date Jun 13, 2024
- GSI Technology Inc.
- Avidan AKERIB
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MEMORY RECONFIGURATION
- Publication number 20240184739
- Publication date Jun 6, 2024
- Intel Corporation
- Joydeep RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLER WITH CACHING AND NON-CACHING MODES
- Publication number 20240152385
- Publication date May 9, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR
- Publication number 20240118891
- Publication date Apr 11, 2024
- Fujitsu Limited
- Sota SAKASHITA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE SIZE CHANGE
- Publication number 20240095169
- Publication date Mar 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Thread Channel Deactivation based on Instruction Cache Misses
- Publication number 20240095031
- Publication date Mar 21, 2024
- Apple Inc.
- Justin Friesenhahn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...
- Publication number 20240086357
- Publication date Mar 14, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES
- Publication number 20240086356
- Publication date Mar 14, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE COHERENCE SIGNALING PROTOCOL
- Publication number 20240045803
- Publication date Feb 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHADOW CACHES FOR LEVEL 2 CACHE CONTROLLER
- Publication number 20240004793
- Publication date Jan 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MERGING DATA FOR WRITE ALLOCATE
- Publication number 20240004694
- Publication date Jan 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING DEVICE WITH VECTOR TRANSFORMATION EXECUTION
- Publication number 20240004663
- Publication date Jan 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mujibur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE THREAD MANAGEMENT FOR HETEROGENOUS COMPUTING ARCHITECTURES
- Publication number 20230418664
- Publication date Dec 28, 2023
- ADVANCED MICRO DEVICES, INC.
- Donny Yi
- G06 - COMPUTING CALCULATING COUNTING

Pipeline control instructions

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Sparse data handling and buffer sharing to reduce memory allocation...

Cache structure and utilization

Global coherence operations

Systolic disaggregation within a matrix accelerator architecture

Cache coherence shared state suppression

System and method for automated prediction and detection of compone...

Memory device for performing in-memory processing

Multi-tile memory management

Memory controller, information processing apparatus, and informatio...

Compression techniques

Graphics processor operation scheduling for deterministic latency

NPU implemented for fusion-artificial neural network to process het...

Cache line demote infrastructure for multi-processor pipelines

Cache structure and utilization

Tag update bus for updated coherence state

Pseudo-random way selection

Rescheduling a failed memory request in a processor

Multi-tile architecture for graphics operations

Pipeline arbitration

Method and apparatus for efficient programmable instructions in com...

Graphics processors and graphics processing units having dot produc...

Multi-tile memory management for detecting cross tile access provid...

Processing pipeline with zero loop overhead

Data pipeline controller

Calculation method and related product

Graphics processors and graphics processing units having dot produc...

Dynamic memory reconfiguration

Pipeline architecture for bitwise multiplier-accumulator (MAC)

External exchange connectivity

Assistance for hardware prefetch in cache access

Patents Applicationslast 30 patents

MEMORY DEVICE FOR PERFORMING IN-MEMORY PROCESSING

CACHE STRUCTURE AND UTILIZATION

COMPRESSION TECHNIQUES

APPARATUS, NPU AND CHIPSET IMPLEMENTED FOR FUSION NEURAL NETWORK

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

PSEUDO-RANDOM WAY SELECTION

TAG UPDATE BUS FOR UPDATED COHERENCE STATE

DISTRIBUTED USER MODE PROCESSING

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

DATA PIPELINE CONTROLLER

Cache Control to Preserve Register Data

PIPELINE ARBITRATION

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

BACKWARD COMPATIBILITY TESTING OF SOFTWARE IN A MODE THAT ATTEMPTS...

HYBRID VIRTUAL GPU CO-SCHEDULING

PIPELINE ARCHITECTURE FOR BITWISE MULTIPLIER-ACCUMULATOR (MAC)

DYNAMIC MEMORY RECONFIGURATION

CONTROLLER WITH CACHING AND NON-CACHING MODES

PROCESSOR

CACHE SIZE CHANGE

Thread Channel Deactivation based on Instruction Cache Misses

SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...

INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES

HARDWARE COHERENCE SIGNALING PROTOCOL

SHADOW CACHES FOR LEVEL 2 CACHE CONTROLLER

MERGING DATA FOR WRITE ALLOCATE

PROCESSING DEVICE WITH VECTOR TRANSFORMATION EXECUTION

ADAPTIVE THREAD MANAGEMENT FOR HETEROGENOUS COMPUTING ARCHITECTURES