Pipeline control instructions

Industry

CPC
G06F9/30079

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

Current Industry

G06F9/30079Pipeline control instructions

Industries

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Adaptive temporal resource binding based on speculative pipeline in...
- Patent number 12,301,451
- Issue date May 13, 2025
- F5, INC.
- Timothy S. Michels
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache size change
- Patent number 12,271,314
- Issue date Apr 8, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data initialization techniques
- Patent number 12,242,414
- Issue date Mar 4, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing of data synchronization barrier instructions
- Patent number 12,229,561
- Issue date Feb 18, 2025
- Apple Inc.
- Madhu Sudan Hari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence signaling protocol
- Patent number 12,197,331
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cost effective storage management
- Patent number 12,182,014
- Issue date Dec 31, 2024
- PURE STORAGE, INC.
- Chad Monteith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing device with vector transformation execution
- Patent number 12,182,573
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Mujibur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse data handling and buffer sharing to reduce memory allocation...
- Patent number 12,153,900
- Issue date Nov 26, 2024
- Microsoft Technology Licensing, LLC
- Gary Shon Katzenberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global coherence operations
- Patent number 12,141,601
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence shared state suppression
- Patent number 12,135,646
- Issue date Nov 5, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for automated prediction and detection of compone...
- Patent number 12,105,579
- Issue date Oct 1, 2024
- Texas Tech University System
- Dy D. Le
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device for performing in-memory processing
- Patent number 12,099,839
- Issue date Sep 24, 2024
- Samsung Electronics Co., Ltd.
- Yuhwan Ro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller, information processing apparatus, and informatio...
- Patent number 12,099,413
- Issue date Sep 24, 2024
- Fujitsu Limited
- Yasuhiro Kitamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,099,461
- Issue date Sep 24, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression techniques
- Patent number 12,093,210
- Issue date Sep 17, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor operation scheduling for deterministic latency
- Patent number 12,079,155
- Issue date Sep 3, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
NPU implemented for fusion-artificial neural network to process het...
- Patent number 12,077,185
- Issue date Sep 3, 2024
- DEEPX CO., LTD.
- Lok Won Kim
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Cache line demote infrastructure for multi-processor pipelines
- Patent number 12,066,939
- Issue date Aug 20, 2024
- Intel Corporation
- Rahul R. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,066,975
- Issue date Aug 20, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tag update bus for updated coherence state
- Patent number 12,056,051
- Issue date Aug 6, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo-random way selection
- Patent number 12,045,644
- Issue date Jul 23, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rescheduling a failed memory request in a processor
- Patent number 12,020,064
- Issue date Jun 25, 2024
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipeline arbitration
- Patent number 12,014,206
- Issue date Jun 18, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile architecture for graphics operations
- Patent number 12,013,808
- Issue date Jun 18, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for efficient programmable instructions in com...
- Patent number 12,008,371
- Issue date Jun 11, 2024
- Advanced Micro Devices, Inc.
- Andrew G. Kegel
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DATA INITIALIZATION TECHNIQUES
- Publication number 20250156371
- Publication date May 15, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE COHERENCE SIGNALING PROTOCOL
- Publication number 20250147888
- Publication date May 8, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing of Data Synchronization Barrier Instructions
- Publication number 20250147767
- Publication date May 8, 2025
- Apple Inc.
- Madhu Sudan Hari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR TRANSFORMATION IN PARALLEL WITH ARITHMETIC OPERATION
- Publication number 20250130808
- Publication date Apr 24, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Mujibur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250117356
- Publication date Apr 10, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20250103546
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250103547
- Publication date Mar 27, 2025
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS ITERATIVE NATURAL LANGUAGE-BASED DATA PIPELINE...
- Publication number 20250094171
- Publication date Mar 20, 2025
- Palantir Technologies Inc.
- Zachary Isaacson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE DATA HANDLING AND BUFFER SHARING TO REDUCE MEMORY ALLOCATION...
- Publication number 20250036368
- Publication date Jan 30, 2025
- Microsoft Technology Licensing, LLC
- Gary Shon KATZENBERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
- Publication number 20250028675
- Publication date Jan 23, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBAL COHERENCE OPERATIONS
- Publication number 20250028551
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE SHARED STATE SUPPRESSION
- Publication number 20250013569
- Publication date Jan 9, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250004981
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING PHYSICAL REGISTER (PR) SWAP MEMORY RENAMING IN PROCESSOR-...
- Publication number 20240427599
- Publication date Dec 26, 2024
- QUALCOMM Incorporated
- Akilesh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE FOR PERFORMING IN-MEMORY PROCESSING
- Publication number 20240419445
- Publication date Dec 19, 2024
- Samsung Electronics Co., Ltd.
- Yuhwan RO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION TECHNIQUES
- Publication number 20240403259
- Publication date Dec 5, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS, NPU AND CHIPSET IMPLEMENTED FOR FUSION NEURAL NETWORK
- Publication number 20240367681
- Publication date Nov 7, 2024
- DEEPX CO., LTD.
- Lok Won KIM
- B60 - VEHICLES IN GENERAL
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD
- Publication number 20240345839
- Publication date Oct 17, 2024
- Intel Corporation
- Kameran Azadet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO-RANDOM WAY SELECTION
- Publication number 20240345868
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG UPDATE BUS FOR UPDATED COHERENCE STATE
- Publication number 20240345956
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED USER MODE PROCESSING
- Publication number 20240320042
- Publication date Sep 26, 2024
- ADVANCED MICRO DEVICES, INC.
- Rex Eldon MCCRARY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20240320184
- Publication date Sep 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PIPELINE CONTROLLER
- Publication number 20240296169
- Publication date Sep 5, 2024
- AT&T INTELLECTUAL PROPERTY I, L.P.
- James Fan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Control to Preserve Register Data
- Publication number 20240289282
- Publication date Aug 29, 2024
- Apple Inc.
- Jonathan M. Redshaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINE ARBITRATION
- Publication number 20240281278
- Publication date Aug 22, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20240256483
- Publication date Aug 1, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING

Pipeline control instructions

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Adaptive temporal resource binding based on speculative pipeline in...

Cache size change

Data initialization techniques

Processing of data synchronization barrier instructions

Systems and methods for improving cache efficiency and utilization

Graphics processor data access and sharing

Hardware coherence signaling protocol

Cost effective storage management

Multi-tile memory management

Processing device with vector transformation execution

Sparse data handling and buffer sharing to reduce memory allocation...

Cache structure and utilization

Global coherence operations

Systolic disaggregation within a matrix accelerator architecture

Cache coherence shared state suppression

System and method for automated prediction and detection of compone...

Memory device for performing in-memory processing

Memory controller, information processing apparatus, and informatio...

Multi-tile memory management

Compression techniques

Graphics processor operation scheduling for deterministic latency

NPU implemented for fusion-artificial neural network to process het...

Cache line demote infrastructure for multi-processor pipelines

Cache structure and utilization

Tag update bus for updated coherence state

Pseudo-random way selection

Rescheduling a failed memory request in a processor

Pipeline arbitration

Multi-tile architecture for graphics operations

Method and apparatus for efficient programmable instructions in com...

Patents Applicationslast 30 patents

DATA INITIALIZATION TECHNIQUES

HARDWARE COHERENCE SIGNALING PROTOCOL

Processing of Data Synchronization Barrier Instructions

VECTOR TRANSFORMATION IN PARALLEL WITH ARITHMETIC OPERATION

MULTI-TILE MEMORY MANAGEMENT

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

CACHE STRUCTURE AND UTILIZATION

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

SYSTEMS AND METHODS ITERATIVE NATURAL LANGUAGE-BASED DATA PIPELINE...

SPARSE DATA HANDLING AND BUFFER SHARING TO REDUCE MEMORY ALLOCATION...

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

GLOBAL COHERENCE OPERATIONS

CACHE COHERENCE SHARED STATE SUPPRESSION

MULTI-TILE MEMORY MANAGEMENT

PROVIDING PHYSICAL REGISTER (PR) SWAP MEMORY RENAMING IN PROCESSOR-...

MEMORY DEVICE FOR PERFORMING IN-MEMORY PROCESSING

CACHE STRUCTURE AND UTILIZATION

COMPRESSION TECHNIQUES

APPARATUS, NPU AND CHIPSET IMPLEMENTED FOR FUSION NEURAL NETWORK

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD

PSEUDO-RANDOM WAY SELECTION

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

TAG UPDATE BUS FOR UPDATED COHERENCE STATE

DISTRIBUTED USER MODE PROCESSING

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

DATA PIPELINE CONTROLLER

Cache Control to Preserve Register Data

PIPELINE ARBITRATION

GRAPHICS PROCESSOR DATA ACCESS AND SHARING