Prefetch instructions; cache control instructions

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CPC
G06F9/30047

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/30047Prefetch instructions; cache control instructions

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Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache to receive firmware generated data during firmware update
- Patent number 12,210,784
- Issue date Jan 28, 2025
- Microsoft Technology Licensing, LLC
- Mallik Bulusu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache support for indirect loads and indirect stores in graph appli...
- Patent number 12,204,901
- Issue date Jan 21, 2025
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flushing cache lines involving persistent memory
- Patent number 12,204,441
- Issue date Jan 21, 2025
- Altera Corporation
- Sharath Raghava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-latency input data staging to execute kernels
- Patent number 12,197,350
- Issue date Jan 14, 2025
- Samsung Electronics Co., Ltd.
- Marie Mai Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence signaling protocol
- Patent number 12,197,331
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero latency prefetching in caches
- Patent number 12,197,334
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with multi dimensional circular addressing selecta...
- Patent number 12,197,343
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for improved deduplication performance using pr...
- Patent number 12,189,493
- Issue date Jan 7, 2025
- Veritas Technologies LLC
- Yaobin Qin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cooperative garbage collection barrier elision
- Patent number 12,190,112
- Issue date Jan 7, 2025
- Oracle International Corporation
- Erik Österlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interrupt cache configuration
- Patent number 12,182,611
- Issue date Dec 31, 2024
- Advanced Micro Devices, Inc.
- Philip Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction prefetch mechanism
- Patent number 12,164,430
- Issue date Dec 10, 2024
- Intel Corporation
- Vasileios Porpodas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Offloading data processing and knowledge synthesis
- Patent number 12,164,920
- Issue date Dec 10, 2024
- Lemon Inc.
- Viacheslav Dubeyko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device, method of operating the memory device, memory module...
- Patent number 12,154,651
- Issue date Nov 26, 2024
- Samsung Electronics Co., Ltd.
- Sunyoung Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computational memory with cooperation among rows of processing elem...
- Patent number 12,147,380
- Issue date Nov 19, 2024
- UNTETHER AI CORPORATION
- William Martin Snelgrove
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelized scrubbing transactions
- Patent number 12,147,301
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- David Matthew Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global coherence operations
- Patent number 12,141,601
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence shared state suppression
- Patent number 12,135,646
- Issue date Nov 5, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence validation using delayed fulfillment of L2 requests
- Patent number 12,118,355
- Issue date Oct 15, 2024
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLELIZED SCRUBBING TRANSACTIONS
- Publication number 20250036522
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- David Matthew THOMPSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR PREFETCHING FUNCTION SEGMENT AND NETWORK DEVICE
- Publication number 20250036414
- Publication date Jan 30, 2025
- Huawei Technologies Co., Ltd
- Hui Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTATIONAL MEMORY WITH COOPERATION AMONG ROWS OF PROCESSING ELEM...
- Publication number 20250036592
- Publication date Jan 30, 2025
- UNTETHER AI CORPORATION
- William Martin SNELGROVE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
- Publication number 20250028675
- Publication date Jan 23, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBAL COHERENCE OPERATIONS
- Publication number 20250028551
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE SHARED STATE SUPPRESSION
- Publication number 20250013569
- Publication date Jan 9, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING WHICH MEMORY SOURCE IS UTILIZED FOR FETCHING INSTRUCTIO...
- Publication number 20250013469
- Publication date Jan 9, 2025
- MICROCHIP TECHNOLOGY INCORPORATED
- Ivar Holand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A LOAD INSTRUCTION WITH A READ-SHARED INDI...
- Publication number 20250004765
- Publication date Jan 2, 2025
- Intel Coporation
- Christopher J. HUGHES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250004981
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20240427600
- Publication date Dec 26, 2024
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS
- Publication number 20240419324
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Matthew Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR UNFAIR ADVANTAGE AWARE SPINLOCK
- Publication number 20240411556
- Publication date Dec 12, 2024
- Samsung Electronics Co., Ltd.
- Anirban SAHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION TECHNIQUES
- Publication number 20240403259
- Publication date Dec 5, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CATEGORIZED MEMORY OPERATIONS FOR SELECTIVE MEMORY FLUSHING
- Publication number 20240403048
- Publication date Dec 5, 2024
- NVIDIA Corporation
- Kaushal AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS
- Publication number 20240403055
- Publication date Dec 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME T...
- Publication number 20240378056
- Publication date Nov 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTANT MEMORY SEGMENTATION FOR PARALLEL PROCESSORS
- Publication number 20240370260
- Publication date Nov 7, 2024
- NVIDIA Corporation
- Deepak Cholayil Unnikrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD AND APPARATUS FOR CONDITIONALLY OFFLOADING INSTRUCTI...
- Publication number 20240354107
- Publication date Oct 24, 2024
- Intel Corporation
- Frank Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO-RANDOM WAY SELECTION
- Publication number 20240345868
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG UPDATE BUS FOR UPDATED COHERENCE STATE
- Publication number 20240345956
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME
- Publication number 20240338215
- Publication date Oct 10, 2024
- SK HYNIX INC.
- Dong Uk LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE BUFFER SIZE DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT M...
- Publication number 20240330213
- Publication date Oct 3, 2024
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING

Prefetch instructions; cache control instructions

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Systems and methods for improving cache efficiency and utilization

Aggressive write flush scheme for a victim cache

Cache to receive firmware generated data during firmware update

Graphics processor data access and sharing

Cache support for indirect loads and indirect stores in graph appli...

Flushing cache lines involving persistent memory

Low-latency input data staging to execute kernels

Methods and apparatus to reduce bank pressure using aggressive writ...

Hardware coherence signaling protocol

Zero latency prefetching in caches

Streaming engine with multi dimensional circular addressing selecta...

Methods and systems for improved deduplication performance using pr...

Cooperative garbage collection barrier elision

Fully pipelined read-modify-write support

Multi-tile memory management

Methods and apparatus for allocation in a victim cache system

Interrupt cache configuration

Instruction prefetch mechanism

Offloading data processing and knowledge synthesis

Memory device, method of operating the memory device, memory module...

Cache structure and utilization

Methods and apparatus for read-modify-write support in multi-banked...

Computational memory with cooperation among rows of processing elem...

Parallelized scrubbing transactions

Global coherence operations

Victim cache with dynamic allocation of entries

Systolic disaggregation within a matrix accelerator architecture

Atomic operations and histogram operations in a cache pipeline

Cache coherence shared state suppression

Cache coherence validation using delayed fulfillment of L2 requests

Patents Applicationslast 30 patents

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

PARALLELIZED SCRUBBING TRANSACTIONS

METHOD FOR PREFETCHING FUNCTION SEGMENT AND NETWORK DEVICE

COMPUTATIONAL MEMORY WITH COOPERATION AMONG ROWS OF PROCESSING ELEM...

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

GLOBAL COHERENCE OPERATIONS

CACHE COHERENCE SHARED STATE SUPPRESSION

CONTROLLING WHICH MEMORY SOURCE IS UTILIZED FOR FETCHING INSTRUCTIO...

APPARATUS AND METHOD FOR A LOAD INSTRUCTION WITH A READ-SHARED INDI...

MULTI-TILE MEMORY MANAGEMENT

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS

CACHE STRUCTURE AND UTILIZATION

SYSTEM AND METHOD FOR UNFAIR ADVANTAGE AWARE SPINLOCK

COMPRESSION TECHNIQUES

CATEGORIZED MEMORY OPERATIONS FOR SELECTIVE MEMORY FLUSHING

DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS

STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME T...

CONSTANT MEMORY SEGMENTATION FOR PARALLEL PROCESSORS

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

SYSTEM, METHOD AND APPARATUS FOR CONDITIONALLY OFFLOADING INSTRUCTI...

PSEUDO-RANDOM WAY SELECTION

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

TAG UPDATE BUS FOR UPDATED COHERENCE STATE

MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME

VARIABLE BUFFER SIZE DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT M...