Prefetch instructions; cache control instructions

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CPC
G06F9/30047

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

Current Industry

G06F9/30047Prefetch instructions; cache control instructions

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Patents Grantslast 30 patents

Information Patent Grant
Data processing apparatus having streaming engine with read and rea...
- Patent number 12,346,698
- Issue date Jul 1, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with separately selectable element and group dupli...
- Patent number 12,339,782
- Issue date Jun 24, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance constant cache and constant access mechanisms
- Patent number 12,333,306
- Issue date Jun 17, 2025
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delayed cache writeback instructions for improved data sharing in m...
- Patent number 12,333,305
- Issue date Jun 17, 2025
- Intel Corporation
- Wim Heirman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DSB operation with excluded region
- Patent number 12,321,746
- Issue date Jun 3, 2025
- Apple Inc.
- Jeff Gonion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 12,321,284
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implicit fence for write messages
- Patent number 12,321,310
- Issue date Jun 3, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence for memory controller
- Patent number 12,321,270
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,321,285
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-indexed micro-operations cache for a processor
- Patent number 12,314,719
- Issue date May 27, 2025
- Nokia Solutions and Networks Oy
- Pranjal Kumar Dutta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with stream metadata saving for context switching
- Patent number 12,299,446
- Issue date May 13, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stream data unit with multiple head registers
- Patent number 12,288,069
- Issue date Apr 29, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction simulation device and method thereof
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- Issue date Apr 29, 2025
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Weilin Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable control of micro-operations cache resources of a proce...
- Patent number 12,282,777
- Issue date Apr 22, 2025
- Nokia Technologies Oy
- Pranjal Kumar Dutta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective speculative prefetch requests for a last-level cache
- Patent number 12,282,428
- Issue date Apr 22, 2025
- Advanced Micro Devices, Inc.
- Tarun Nakra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for affinity-aware prefetching
- Patent number 12,277,032
- Issue date Apr 15, 2025
- Cohesity Inc.
- Yaobin Qin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache replacement policy optimization for producer-consumer flows
- Patent number 12,277,071
- Issue date Apr 15, 2025
- Microsoft Technology Licensing, LLC
- Ramakrishna Huggahalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for managing cores for storage
- Patent number 12,271,752
- Issue date Apr 8, 2025
- EMC IP Holding Company LLC
- John Gillono
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache size change
- Patent number 12,271,314
- Issue date Apr 8, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable exactly-once data processing using transactional streaming...
- Patent number 12,259,800
- Issue date Mar 25, 2025
- Google LLC
- Pavan Edara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for flush plus reload cache side-channel attack...
- Patent number 12,259,973
- Issue date Mar 25, 2025
- Microsoft Technology Licensing, LLC
- Ishwar Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization of asymmetric processors executing in quasi-dual pr...
- Patent number 12,242,849
- Issue date Mar 4, 2025
- Ceremorphic, Inc.
- Heonchul Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data initialization techniques
- Patent number 12,242,414
- Issue date Mar 4, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable tweak engines and prefetched tweak values for encyrption e...
- Patent number 12,231,532
- Issue date Feb 18, 2025
- Xilinx, Inc.
- Devanjan Maiti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-layer data cache to prevent user experience interrupts during...
- Patent number 12,217,058
- Issue date Feb 4, 2025
- Brex, Inc.
- Ming Xiao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of storing register data elements to interleave with data el...
- Patent number 12,217,054
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Duc Quang Bui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CACHE SIZE CHANGE
- Publication number 20250231878
- Publication date Jul 17, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20250225083
- Publication date Jul 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH MULTI DIMENSIONAL CIRCULAR ADDRESSING SELECTA...
- Publication number 20250217301
- Publication date Jul 3, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE EXACTLY-ONCE DATA PROCESSING USING TRANSACTIONAL STREAMING...
- Publication number 20250199928
- Publication date Jun 19, 2025
- Google LLC
- Pavan Edara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Universal Core to Accelerator Communication Architecture
- Publication number 20250199890
- Publication date Jun 19, 2025
- Intel Corporation
- Yipeng Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH
- Publication number 20250190368
- Publication date Jun 12, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-armed bandit improvement
- Publication number 20250181411
- Publication date Jun 5, 2025
- MELLANOX TECHNOLOGIES, LTD.
- Amir Rosen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20250173308
- Publication date May 29, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE, OPERATING METHOD OF MEMORY DEVICE, AND OPERATING MET...
- Publication number 20250173282
- Publication date May 29, 2025
- Samsung Electronics Co., Ltd.
- YONGMIN TAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA INITIALIZATION TECHNIQUES
- Publication number 20250156371
- Publication date May 15, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE COHERENCE SIGNALING PROTOCOL
- Publication number 20250147888
- Publication date May 8, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCHING PROGRAM CODE FROM FLASH MEMORY BASED ON BRANCH LOGIC
- Publication number 20250138825
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Veeramanikandan Raju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MEMORY EQUIPPED ARITHMETIC DEVICE
- Publication number 20250130796
- Publication date Apr 24, 2025
- Fujitsu Limited
- Shiho NAKAHARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF STORING REGISTER DATA ELEMENTS TO INTERLEAVE WITH DATA EL...
- Publication number 20250130797
- Publication date Apr 24, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Duc Quang BUI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LAYER DATA CACHE TO PREVENT USER EXPERIENCE INTERRUPTS DURING...
- Publication number 20250123842
- Publication date Apr 17, 2025
- Brex Inc.
- Ming Xiao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flushing Cache Lines Involving Persistent Memory
- Publication number 20250117319
- Publication date Apr 10, 2025
- Altera Corporation
- Sharath Raghava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250117356
- Publication date Apr 10, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, CIRCUITS, METHODS, AND ARTICLES OF MANUFACTURER FOR DRAM-B...
- Publication number 20250117223
- Publication date Apr 10, 2025
- University of Virginia Patent Foundation
- Kevin Skadron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR AND METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING
- Publication number 20250110736
- Publication date Apr 3, 2025
- Beijing Youzhuju Network Technology Co., Ltd.
- Yuhui CAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC INSTRUCTION DECOUPLING (SID) FOR DATA MOVEMENT AND COMPUTE
- Publication number 20250110735
- Publication date Apr 3, 2025
- AppaRao CHALLAGUNDLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH TARGET BUFFER VICTIM CACHE
- Publication number 20250110743
- Publication date Apr 3, 2025
- Microsoft Technology Licensing, LLC
- Julio Gago Alonso
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20250103546
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO LATENCY PREFETCHING IN CACHES
- Publication number 20250103503
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250103547
- Publication date Mar 27, 2025
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

Prefetch instructions; cache control instructions

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Data processing apparatus having streaming engine with read and rea...

Streaming engine with separately selectable element and group dupli...

High performance constant cache and constant access mechanisms

Delayed cache writeback instructions for improved data sharing in m...

DSB operation with excluded region

Methods and apparatus to facilitate atomic operations in victim cache

Implicit fence for write messages

Hardware coherence for memory controller

Victim cache with write miss merging

Multi-indexed micro-operations cache for a processor

Streaming engine with stream metadata saving for context switching

Write merging on stores with different privilege levels

Stream data unit with multiple head registers

Instruction simulation device and method thereof

Programmable control of micro-operations cache resources of a proce...

Selective speculative prefetch requests for a last-level cache

Methods and systems for affinity-aware prefetching

Cache replacement policy optimization for producer-consumer flows

Techniques for managing cores for storage

Cache size change

Hybrid victim cache and write miss buffer with fence operation

Scalable exactly-once data processing using transactional streaming...

Methods and apparatus for multi-banked victim cache with dual datapath

Systems and methods for flush plus reload cache side-channel attack...

Synchronization of asymmetric processors executing in quasi-dual pr...

Data initialization techniques

Scalable tweak engines and prefetched tweak values for encyrption e...

Multi-layer data cache to prevent user experience interrupts during...

Method of storing register data elements to interleave with data el...

Atomic compare and swap in a coherent cache system

Patents Applicationslast 30 patents

CACHE SIZE CHANGE

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

STREAMING ENGINE WITH MULTI DIMENSIONAL CIRCULAR ADDRESSING SELECTA...

SCALABLE EXACTLY-ONCE DATA PROCESSING USING TRANSACTIONAL STREAMING...

Universal Core to Accelerator Communication Architecture

METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH

Multi-armed bandit improvement

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

MEMORY DEVICE, OPERATING METHOD OF MEMORY DEVICE, AND OPERATING MET...

DATA INITIALIZATION TECHNIQUES

HARDWARE COHERENCE SIGNALING PROTOCOL

PREFETCHING PROGRAM CODE FROM FLASH MEMORY BASED ON BRANCH LOGIC

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

CACHE MEMORY EQUIPPED ARITHMETIC DEVICE

METHOD OF STORING REGISTER DATA ELEMENTS TO INTERLEAVE WITH DATA EL...

MULTI-LAYER DATA CACHE TO PREVENT USER EXPERIENCE INTERRUPTS DURING...

Flushing Cache Lines Involving Persistent Memory

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

MULTI-TILE MEMORY MANAGEMENT

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

SYSTEMS, CIRCUITS, METHODS, AND ARTICLES OF MANUFACTURER FOR DRAM-B...

PROCESSOR AND METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING

STATIC INSTRUCTION DECOUPLING (SID) FOR DATA MOVEMENT AND COMPUTE

BRANCH TARGET BUFFER VICTIM CACHE

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

CACHE STRUCTURE AND UTILIZATION

ZERO LATENCY PREFETCHING IN CACHES

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...