Prefetch instructions; cache control instructions

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CPC
G06F9/30047

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

Current Industry

G06F9/30047Prefetch instructions; cache control instructions

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Patents Grantslast 30 patents

Information Patent Grant
Instruction prefetch mechanism
- Patent number 12,164,430
- Issue date Dec 10, 2024
- Intel Corporation
- Vasileios Porpodas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Offloading data processing and knowledge synthesis
- Patent number 12,164,920
- Issue date Dec 10, 2024
- Lemon Inc.
- Viacheslav Dubeyko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device, method of operating the memory device, memory module...
- Patent number 12,154,651
- Issue date Nov 26, 2024
- Samsung Electronics Co., Ltd.
- Sunyoung Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computational memory with cooperation among rows of processing elem...
- Patent number 12,147,380
- Issue date Nov 19, 2024
- UNTETHER AI CORPORATION
- William Martin Snelgrove
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelized scrubbing transactions
- Patent number 12,147,301
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- David Matthew Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global coherence operations
- Patent number 12,141,601
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence shared state suppression
- Patent number 12,135,646
- Issue date Nov 5, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence validation using delayed fulfillment of L2 requests
- Patent number 12,118,355
- Issue date Oct 15, 2024
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-threading processor and operating method thereof
- Patent number 12,118,356
- Issue date Oct 15, 2024
- MetisX CO., Ltd.
- Kwang Sun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device, system and method for selectively dropping software prefetc...
- Patent number 12,111,772
- Issue date Oct 8, 2024
- Intel Corporation
- Wim Heirman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a page-local delta-based prefetcher
- Patent number 12,111,767
- Issue date Oct 8, 2024
- Advanced Micro Devices, Inc.
- Susumu Mashimo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for processing multiple transactions converted from single t...
- Patent number 12,112,168
- Issue date Oct 8, 2024
- MetisX CO., Ltd.
- Kwang Sun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor instructions for data compression and decompression
- Patent number 12,106,104
- Issue date Oct 1, 2024
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing apparatus and related product
- Patent number 12,106,109
- Issue date Oct 1, 2024
- ANHUI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
- Xuyan Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cat aware loads and software prefetches
- Patent number 12,099,444
- Issue date Sep 24, 2024
- CENTAUR TECHNOLOGY, INC.
- Douglas Raye Reed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,099,461
- Issue date Sep 24, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression techniques
- Patent number 12,093,210
- Issue date Sep 17, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hypervisor-assisted security mechanism
- Patent number 12,093,711
- Issue date Sep 17, 2024
- VMWARE LLC
- Bharath Kumar Chandrasekhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical address proxy reuse management
- Patent number 12,086,063
- Issue date Sep 10, 2024
- Ventana Micro Systems Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor that prevents speculative execution across translation co...
- Patent number 12,086,245
- Issue date Sep 10, 2024
- Ventana Micro Systems Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector friendly instruction format and execution thereof
- Patent number 12,086,594
- Issue date Sep 10, 2024
- Intel Corporation
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated database cache resizing
- Patent number 12,079,189
- Issue date Sep 3, 2024
- SERVICENOW, INC.
- Ankit Khetarpal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for hardware-assisted pre-execution
- Patent number 12,079,631
- Issue date Sep 3, 2024
- Hewlett Packard Enterprise Development LP
- Sanyam Mehta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor operation scheduling for deterministic latency
- Patent number 12,079,155
- Issue date Sep 3, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20240427600
- Publication date Dec 26, 2024
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS
- Publication number 20240419324
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Matthew Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR UNFAIR ADVANTAGE AWARE SPINLOCK
- Publication number 20240411556
- Publication date Dec 12, 2024
- Samsung Electronics Co., Ltd.
- Anirban SAHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION TECHNIQUES
- Publication number 20240403259
- Publication date Dec 5, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CATEGORIZED MEMORY OPERATIONS FOR SELECTIVE MEMORY FLUSHING
- Publication number 20240403048
- Publication date Dec 5, 2024
- NVIDIA Corporation
- Kaushal AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS
- Publication number 20240403055
- Publication date Dec 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME T...
- Publication number 20240378056
- Publication date Nov 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTANT MEMORY SEGMENTATION FOR PARALLEL PROCESSORS
- Publication number 20240370260
- Publication date Nov 7, 2024
- NVIDIA Corporation
- Deepak Cholayil Unnikrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD AND APPARATUS FOR CONDITIONALLY OFFLOADING INSTRUCTI...
- Publication number 20240354107
- Publication date Oct 24, 2024
- Intel Corporation
- Frank Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO-RANDOM WAY SELECTION
- Publication number 20240345868
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG UPDATE BUS FOR UPDATED COHERENCE STATE
- Publication number 20240345956
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME
- Publication number 20240338215
- Publication date Oct 10, 2024
- SK HYNIX INC.
- Dong Uk LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE BUFFER SIZE DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT M...
- Publication number 20240330213
- Publication date Oct 3, 2024
- Xilinx, Inc.
- Chandrasekhar S. Thyamagondlu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD OF PROCESSING DATA, ELECTRONIC DEVICE, AND STO...
- Publication number 20240329987
- Publication date Oct 3, 2024
- Kunlunxin Technology (Beijing) Company Limited
- Liang SHAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH ERROR DETECTION, CORRECTION AND RESTART
- Publication number 20240320094
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20240320184
- Publication date Sep 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HANDLING NON-CORRECTABLE ERRORS
- Publication number 20240311235
- Publication date Sep 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- David Matthew THOMPSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE, METHOD AND SYSTEM FOR PRIORITIZING ENTRIES OF AN INSTRUCTIO...
- Publication number 20240311151
- Publication date Sep 19, 2024
- Intel Corporation
- Gilles Pokam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSLATION LOOKASIDE BUFFER MAINTENANCE METHOD AND RELATED DEVICE
- Publication number 20240311152
- Publication date Sep 19, 2024
- Huawei Technologies Co., Ltd
- Bo WAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH SHORT CUT START INSTRUCTIONS
- Publication number 20240296065
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Control to Preserve Register Data
- Publication number 20240289282
- Publication date Aug 29, 2024
- Apple Inc.
- Jonathan M. Redshaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINE ARBITRATION
- Publication number 20240281278
- Publication date Aug 22, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EMBEDDED CONFIGURABLE ENGINE
- Publication number 20240281377
- Publication date Aug 22, 2024
- Xilinx, Inc.
- Alireza KAVIANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD STORE CACHE MICROARCHITECTURE
- Publication number 20240281249
- Publication date Aug 22, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING

Prefetch instructions; cache control instructions

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Instruction prefetch mechanism

Offloading data processing and knowledge synthesis

Memory device, method of operating the memory device, memory module...

Cache structure and utilization

Methods and apparatus for read-modify-write support in multi-banked...

Computational memory with cooperation among rows of processing elem...

Parallelized scrubbing transactions

Global coherence operations

Victim cache with dynamic allocation of entries

Systolic disaggregation within a matrix accelerator architecture

Atomic operations and histogram operations in a cache pipeline

Cache coherence shared state suppression

Cache coherence validation using delayed fulfillment of L2 requests

Multi-threading processor and operating method thereof

Device, system and method for selectively dropping software prefetc...

Method and apparatus for a page-local delta-based prefetcher

Method for processing multiple transactions converted from single t...

Processor instructions for data compression and decompression

Methods and apparatus for eviction in dual datapath victim cache sy...

Data processing apparatus and related product

Cat aware loads and software prefetches

Multi-tile memory management

Compression techniques

Hypervisor-assisted security mechanism

Physical address proxy reuse management

Processor that prevents speculative execution across translation co...

Vector friendly instruction format and execution thereof

Automated database cache resizing

Method and system for hardware-assisted pre-execution

Graphics processor operation scheduling for deterministic latency

Patents Applicationslast 30 patents

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS

CACHE STRUCTURE AND UTILIZATION

SYSTEM AND METHOD FOR UNFAIR ADVANTAGE AWARE SPINLOCK

COMPRESSION TECHNIQUES

CATEGORIZED MEMORY OPERATIONS FOR SELECTIVE MEMORY FLUSHING

DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS

STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME T...

CONSTANT MEMORY SEGMENTATION FOR PARALLEL PROCESSORS

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

SYSTEM, METHOD AND APPARATUS FOR CONDITIONALLY OFFLOADING INSTRUCTI...

PSEUDO-RANDOM WAY SELECTION

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

TAG UPDATE BUS FOR UPDATED COHERENCE STATE

MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME

VARIABLE BUFFER SIZE DESCRIPTOR FETCHING FOR A MULTI-QUEUE DIRECT M...

APPARATUS AND METHOD OF PROCESSING DATA, ELECTRONIC DEVICE, AND STO...

STREAMING ENGINE WITH ERROR DETECTION, CORRECTION AND RESTART

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

HANDLING NON-CORRECTABLE ERRORS

DEVICE, METHOD AND SYSTEM FOR PRIORITIZING ENTRIES OF AN INSTRUCTIO...

TRANSLATION LOOKASIDE BUFFER MAINTENANCE METHOD AND RELATED DEVICE

STREAMING ENGINE WITH SHORT CUT START INSTRUCTIONS

VICTIM CACHE WITH WRITE MISS MERGING

Cache Control to Preserve Register Data

PIPELINE ARBITRATION

EMBEDDED CONFIGURABLE ENGINE

LOAD STORE CACHE MICROARCHITECTURE