Prefetch instructions; cache control instructions

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CPC
G06F9/30047

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/30047Prefetch instructions; cache control instructions

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Patents Grantslast 30 patents

Information Patent Grant
Techniques for managing cores for storage
- Patent number 12,271,752
- Issue date Apr 8, 2025
- EMC IP Holding Company LLC
- John Gillono
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache size change
- Patent number 12,271,314
- Issue date Apr 8, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable exactly-once data processing using transactional streaming...
- Patent number 12,259,800
- Issue date Mar 25, 2025
- Google LLC
- Pavan Edara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for flush plus reload cache side-channel attack...
- Patent number 12,259,973
- Issue date Mar 25, 2025
- Microsoft Technology Licensing, LLC
- Ishwar Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization of asymmetric processors executing in quasi-dual pr...
- Patent number 12,242,849
- Issue date Mar 4, 2025
- Ceremorphic, Inc.
- Heonchul Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data initialization techniques
- Patent number 12,242,414
- Issue date Mar 4, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable tweak engines and prefetched tweak values for encyrption e...
- Patent number 12,231,532
- Issue date Feb 18, 2025
- Xilinx, Inc.
- Devanjan Maiti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-layer data cache to prevent user experience interrupts during...
- Patent number 12,217,058
- Issue date Feb 4, 2025
- Brex, Inc.
- Ming Xiao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of storing register data elements to interleave with data el...
- Patent number 12,217,054
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Duc Quang Bui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache to receive firmware generated data during firmware update
- Patent number 12,210,784
- Issue date Jan 28, 2025
- Microsoft Technology Licensing, LLC
- Mallik Bulusu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache support for indirect loads and indirect stores in graph appli...
- Patent number 12,204,901
- Issue date Jan 21, 2025
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flushing cache lines involving persistent memory
- Patent number 12,204,441
- Issue date Jan 21, 2025
- Altera Corporation
- Sharath Raghava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-latency input data staging to execute kernels
- Patent number 12,197,350
- Issue date Jan 14, 2025
- Samsung Electronics Co., Ltd.
- Marie Mai Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence signaling protocol
- Patent number 12,197,331
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero latency prefetching in caches
- Patent number 12,197,334
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming engine with multi dimensional circular addressing selecta...
- Patent number 12,197,343
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for improved deduplication performance using pr...
- Patent number 12,189,493
- Issue date Jan 7, 2025
- Veritas Technologies LLC
- Yaobin Qin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cooperative garbage collection barrier elision
- Patent number 12,190,112
- Issue date Jan 7, 2025
- Oracle International Corporation
- Erik Österlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interrupt cache configuration
- Patent number 12,182,611
- Issue date Dec 31, 2024
- Advanced Micro Devices, Inc.
- Philip Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction prefetch mechanism
- Patent number 12,164,430
- Issue date Dec 10, 2024
- Intel Corporation
- Vasileios Porpodas
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Flushing Cache Lines Involving Persistent Memory
- Publication number 20250117319
- Publication date Apr 10, 2025
- Altera Corporation
- Sharath Raghava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250117356
- Publication date Apr 10, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, CIRCUITS, METHODS, AND ARTICLES OF MANUFACTURER FOR DRAM-B...
- Publication number 20250117223
- Publication date Apr 10, 2025
- University of Virginia Patent Foundation
- Kevin Skadron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR AND METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING
- Publication number 20250110736
- Publication date Apr 3, 2025
- Beijing Youzhuju Network Technology Co., Ltd.
- Yuhui CAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC INSTRUCTION DECOUPLING (SID) FOR DATA MOVEMENT AND COMPUTE
- Publication number 20250110735
- Publication date Apr 3, 2025
- AppaRao CHALLAGUNDLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH TARGET BUFFER VICTIM CACHE
- Publication number 20250110743
- Publication date Apr 3, 2025
- Microsoft Technology Licensing, LLC
- Julio Gago Alonso
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20250103546
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO LATENCY PREFETCHING IN CACHES
- Publication number 20250103503
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250103547
- Publication date Mar 27, 2025
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE FOR PREDICTING BEHAVIOUR OF CONTROL FLOW INSTRUCTIONS
- Publication number 20250068427
- Publication date Feb 27, 2025
- ARM Limited
- Houdhaifa BOUZGUARROU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR PREFETCHING FUNCTION SEGMENT AND NETWORK DEVICE
- Publication number 20250036414
- Publication date Jan 30, 2025
- Huawei Technologies Co., Ltd
- Hui Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLELIZED SCRUBBING TRANSACTIONS
- Publication number 20250036522
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- David Matthew THOMPSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTATIONAL MEMORY WITH COOPERATION AMONG ROWS OF PROCESSING ELEM...
- Publication number 20250036592
- Publication date Jan 30, 2025
- UNTETHER AI CORPORATION
- William Martin SNELGROVE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
- Publication number 20250028675
- Publication date Jan 23, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBAL COHERENCE OPERATIONS
- Publication number 20250028551
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE SHARED STATE SUPPRESSION
- Publication number 20250013569
- Publication date Jan 9, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING WHICH MEMORY SOURCE IS UTILIZED FOR FETCHING INSTRUCTIO...
- Publication number 20250013469
- Publication date Jan 9, 2025
- MICROCHIP TECHNOLOGY INCORPORATED
- Ivar Holand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A LOAD INSTRUCTION WITH A READ-SHARED INDI...
- Publication number 20250004765
- Publication date Jan 2, 2025
- Intel Coporation
- Christopher J. HUGHES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250004981
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20240427600
- Publication date Dec 26, 2024
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS
- Publication number 20240419324
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Matthew Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

Prefetch instructions; cache control instructions

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Techniques for managing cores for storage

Cache size change

Hybrid victim cache and write miss buffer with fence operation

Scalable exactly-once data processing using transactional streaming...

Methods and apparatus for multi-banked victim cache with dual datapath

Systems and methods for flush plus reload cache side-channel attack...

Synchronization of asymmetric processors executing in quasi-dual pr...

Data initialization techniques

Scalable tweak engines and prefetched tweak values for encyrption e...

Multi-layer data cache to prevent user experience interrupts during...

Method of storing register data elements to interleave with data el...

Atomic compare and swap in a coherent cache system

Systems and methods for improving cache efficiency and utilization

Aggressive write flush scheme for a victim cache

Cache to receive firmware generated data during firmware update

Graphics processor data access and sharing

Cache support for indirect loads and indirect stores in graph appli...

Flushing cache lines involving persistent memory

Low-latency input data staging to execute kernels

Methods and apparatus to reduce bank pressure using aggressive writ...

Hardware coherence signaling protocol

Zero latency prefetching in caches

Streaming engine with multi dimensional circular addressing selecta...

Methods and systems for improved deduplication performance using pr...

Cooperative garbage collection barrier elision

Fully pipelined read-modify-write support

Multi-tile memory management

Methods and apparatus for allocation in a victim cache system

Interrupt cache configuration

Instruction prefetch mechanism

Patents Applicationslast 30 patents

Flushing Cache Lines Involving Persistent Memory

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

MULTI-TILE MEMORY MANAGEMENT

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

SYSTEMS, CIRCUITS, METHODS, AND ARTICLES OF MANUFACTURER FOR DRAM-B...

PROCESSOR AND METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING

STATIC INSTRUCTION DECOUPLING (SID) FOR DATA MOVEMENT AND COMPUTE

BRANCH TARGET BUFFER VICTIM CACHE

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

CACHE STRUCTURE AND UTILIZATION

ZERO LATENCY PREFETCHING IN CACHES

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

TECHNIQUE FOR PREDICTING BEHAVIOUR OF CONTROL FLOW INSTRUCTIONS

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

METHOD FOR PREFETCHING FUNCTION SEGMENT AND NETWORK DEVICE

PARALLELIZED SCRUBBING TRANSACTIONS

COMPUTATIONAL MEMORY WITH COOPERATION AMONG ROWS OF PROCESSING ELEM...

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

GLOBAL COHERENCE OPERATIONS

CACHE COHERENCE SHARED STATE SUPPRESSION

CONTROLLING WHICH MEMORY SOURCE IS UTILIZED FOR FETCHING INSTRUCTIO...

APPARATUS AND METHOD FOR A LOAD INSTRUCTION WITH A READ-SHARED INDI...

MULTI-TILE MEMORY MANAGEMENT

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...