Routing

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G06F17/5077

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions

Current Industry

G06F17/5077Routing

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Patents Grantslast 30 patents

Information Patent Grant
Defense techniques for split manufacturing
- Patent number 10,867,937
- Issue date Dec 15, 2020
- Board of Regents, The University of Texas System
- Jeyavijayan Rajendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit layout wiring for multi-core chips
- Patent number 10,812,079
- Issue date Oct 20, 2020
- STMicroelectronics, Inc.
- Chetan Bisht
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic integrated circuit, design support system, and c...
- Patent number 10,740,435
- Issue date Aug 11, 2020
- NEC Corporation
- Noboru Sakimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bandwidth test in networking System-on-Chip verification
- Patent number 10,664,566
- Issue date May 26, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electromagnetic shielding metal-insulator-metal capacitor structure
- Patent number 10,665,550
- Issue date May 26, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hui Yu Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wirelength distribution schemes and techniques
- Patent number 10,657,218
- Issue date May 19, 2020
- ARM Limited
- Divya Madapusi Srinivas Prasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routerless networks-on-chip
- Patent number 10,657,216
- Issue date May 19, 2020
- Oregon State University
- Lizhong Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency test in networking system-on-chip verification
- Patent number 10,657,217
- Issue date May 19, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying circuits based on timing reports for critical paths
- Patent number 10,650,113
- Issue date May 12, 2020
- International Business Machines Corporation
- Rina Kipnis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-bit clock gating cell to reduce clock power
- Patent number 10,650,112
- Issue date May 12, 2020
- Apple Inc.
- Harsha Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register pull-out for sequential circuit blocks in circuit designs
- Patent number 10,642,951
- Issue date May 5, 2020
- Xilinx, Inc.
- Govinda Keshavdas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design
- Patent number 10,635,774
- Issue date Apr 28, 2020
- ARM Limited
- Anup Gangwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus comprising conductive traces configured to transmit diffe...
- Patent number 10,638,601
- Issue date Apr 28, 2020
- Seagate Technology LLC
- Vinod Arjun Huddar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware and software event tracing for a system-on-chip
- Patent number 10,635,769
- Issue date Apr 28, 2020
- Xilinx, Inc.
- Samuel A. Skalicky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing fast incremental physical desig...
- Patent number 10,635,772
- Issue date Apr 28, 2020
- Altera Corporation
- Junaid Asim Khan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit including filler cell
- Patent number 10,635,775
- Issue date Apr 28, 2020
- Samsung Electronics Co., Ltd.
- Hoi-jin Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flow control in networking system-on-chip verification
- Patent number 10,628,548
- Issue date Apr 21, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing circuit designs for implementation using a programmable net...
- Patent number 10,628,547
- Issue date Apr 21, 2020
- Xilinx, Inc.
- Ian A. Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing system for performing colorless routing for quadruple pat...
- Patent number 10,621,300
- Issue date Apr 14, 2020
- Samsung Electronics Co., Ltd.
- Hyo-Sig Won
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing placement and routing concurrently
- Patent number 10,614,191
- Issue date Apr 7, 2020
- Xilinx, Inc.
- Henri Fraisse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constructing staging trees in hierarchical circuit designs
- Patent number 10,616,103
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Harald Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Engineering change order aware global routing
- Patent number 10,606,976
- Issue date Mar 31, 2020
- International Business Machines Corporation
- Michael A Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for dynamic visual guidance of mutually paired co...
- Patent number 10,606,974
- Issue date Mar 31, 2020
- Cadence Design Systems, Inc.
- Amiya Acharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coordinates-based generative adversarial networks for generating sy...
- Patent number 10,606,975
- Issue date Mar 31, 2020
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leadframe with vertically spaced die attach pads
- Patent number 10,600,724
- Issue date Mar 24, 2020
- Texas Instruments Incorporated
- Chia-Yu Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fabricating unique chips using a charged particle multi-beamlet lit...
- Patent number 10,600,733
- Issue date Mar 24, 2020
- ASML Netherlands B.V.
- Marcel Nicolaas Jacobus van Kervinck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device including a gate pitch and an interconnection...
- Patent number 10,593,701
- Issue date Mar 17, 2020
- Samsung Electronics Co., Ltd.
- Jae-Woo Seo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for pin automation for topology editing
- Patent number 10,586,011
- Issue date Mar 10, 2020
- Cadence Design Systems, Inc.
- Dennis Nagle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Build synthesized soft arrays
- Patent number 10,586,006
- Issue date Mar 10, 2020
- International Business Machines Corporation
- Albert Frisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D-microstrip branchline coupler
- Patent number 10,586,752
- Issue date Mar 10, 2020
- International Business Machines Corporation
- Barbara S. DeWitt
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AUTOMATED DESIGN CLOSURE WITH ABUTTED HIERARCHY
- Publication number 20210165856
- Publication date Jun 3, 2021
- International Business Machines Corporation
- Michael Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FEOL INTERCONNECT USED AS CAPACITANCE OVER FINS INSTEAD OF GATES
- Publication number 20210143095
- Publication date May 13, 2021
- International Business Machines Corporation
- Michael Sperling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN-RULE CHECKING FOR CURVILINEAR DEVICE FEATURES
- Publication number 20210133293
- Publication date May 6, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Ahmed Hassan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH CELLS HAVING METAL LAYER CONFIGURED BASED O...
- Publication number 20210125917
- Publication date Apr 29, 2021
- QUALCOMM Incorporated
- Mamta BANSAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH CIRCUIT CELLS HAVING LOWER INTERCELL ROUTIN...
- Publication number 20210125926
- Publication date Apr 29, 2021
- QUALCOMM Incorporated
- Vincent Xavier LE BARS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH CONSTRAINED METAL LINE ARRANGEMENT
- Publication number 20210110000
- Publication date Apr 15, 2021
- Taiwan Semiconductor Manufacturing company Ltd.
- XinYong WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROUTING A CELL OF A SEMICONDUCTOR CHIP
- Publication number 20210103641
- Publication date Apr 8, 2021
- International Business Machines Corporation
- Thomas Makowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Grid Layout Techniques
- Publication number 20210103640
- Publication date Apr 8, 2021
- ARM Limited
- Abhilash Velluridathil Thazhathidathil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Grid Porosity Techniques
- Publication number 20210096627
- Publication date Apr 1, 2021
- ARM Limited
- Soutani Bala Venkatanaga Durga Prasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIELET DESIGN TECHNIQUES
- Publication number 20210081508
- Publication date Mar 18, 2021
- ARM Limited
- Xiaoqing Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SRAM HAVING IRREGULARLY SHAPED METAL LINES
- Publication number 20210082475
- Publication date Mar 18, 2021
- Taiwan Semiconductor Manufacturing Co., LTD
- Jui-Lin Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT AND TUNING THEREOF
- Publication number 20210082860
- Publication date Mar 18, 2021
- International Business Machines Corporation
- David Audette
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NET ROUTING FOR INTEGRATED CIRCUIT (IC) DESIGN
- Publication number 20210073347
- Publication date Mar 11, 2021
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METAL FILL SHAPE REMOVAL FROM SELECTED NETS
- Publication number 20210073348
- Publication date Mar 11, 2021
- International Business Machines Corporation
- Jesse SURPRISE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for improved Circuit Structure Thermal Reliabi...
- Publication number 20210066209
- Publication date Mar 4, 2021
- NXP B.V.
- Leo van Gemert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLACE-AND-ROUTE RESISTANCE AND CAPACITANCE OPTIMIZATION USING MULTI...
- Publication number 20210043567
- Publication date Feb 11, 2021
- Intel Corporation
- Mark ANDERS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL CLOCK TREE CONSTRUCTION BASED ON CONSTRAINTS
- Publication number 20200401179
- Publication date Dec 24, 2020
- Samsung Electronics Co., Ltd.
- Sridhar SUBRAMANIAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL CLOCK TREE IMPLEMENTATION
- Publication number 20200401673
- Publication date Dec 24, 2020
- Samsung Electronics Co., Ltd.
- Hongda LU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR FABRICATING INTEGRATED CIRCUIT WITH AID OF PR...
- Publication number 20200394279
- Publication date Dec 17, 2020
- Taiwan Semiconductor Manufacturing company Ltd.
- YUNG-HSU CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIAS WITH MULTICONNECTION VIA STRUCTURES
- Publication number 20200387581
- Publication date Dec 10, 2020
- Avatar Integrated Systems, Inc.
- Ping-San Tzeng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF A MEMORY CELL OF AN INTEGRATED CIRCUIT
- Publication number 20200320174
- Publication date Oct 8, 2020
- International Business Machines Corporation
- Rolf Sautter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR IMPLEMENTING VERIFICATION IP FOR PRE-SILICON...
- Publication number 20200311225
- Publication date Oct 1, 2020
- SILICONCH SYSTEMS PVT LTD
- Kaustubh KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EMBEDDED FPGA TIMING SIGN-OFF
- Publication number 20200311219
- Publication date Oct 1, 2020
- Achronix Semiconductor Corporation
- Namit Varma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREDICTING ROUTABILITY OF INTERCONNECTS
- Publication number 20200257770
- Publication date Aug 13, 2020
- International Business Machines Corporation
- ZHICHAO LI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN AND FABRICATION
- Publication number 20200250281
- Publication date Aug 6, 2020
- ARM Limited
- Sean James SALISBURY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELL ARCHITECTURE WITH POWER TRACKS COMPLETELY INSIDE A CELL
- Publication number 20200251464
- Publication date Aug 6, 2020
- Intel Corporation
- Srinivasa Chaitanya GADIGATLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERIPHERAL TOOL
- Publication number 20200242210
- Publication date Jul 30, 2020
- EFINIX, INC.
- James Schleicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IDENTIFICATION OF HOTSPOTS IN CONGESTION ANALYSIS DURING PHYSICAL D...
- Publication number 20200218789
- Publication date Jul 9, 2020
- International Business Machines Corporation
- Zhichao Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR REDUCING SILICON AREA OF RESILIENT SYSTEMS US...
- Publication number 20200210544
- Publication date Jul 2, 2020
- Arteris, Inc
- K. Charles JANAC
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF DESIGNING A LAYOUT FOR A SEMICONDUCTOR INTEGRATED CIRCUIT
- Publication number 20200201954
- Publication date Jun 25, 2020
- Samsung Electronics Co., Ltd.
- Vassilios Gerousis
- G06 - COMPUTING CALCULATING COUNTING

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Defense techniques for split manufacturing

Integrated circuit layout wiring for multi-core chips

Programmable logic integrated circuit, design support system, and c...

Bandwidth test in networking System-on-Chip verification

Electromagnetic shielding metal-insulator-metal capacitor structure

Wirelength distribution schemes and techniques

Routerless networks-on-chip

Latency test in networking system-on-chip verification

Modifying circuits based on timing reports for critical paths

Multi-bit clock gating cell to reduce clock power

Register pull-out for sequential circuit blocks in circuit designs

Integrated circuit design

Apparatus comprising conductive traces configured to transmit diffe...

Hardware and software event tracing for a system-on-chip

Method and apparatus for performing fast incremental physical desig...

Integrated circuit including filler cell

Flow control in networking system-on-chip verification

Routing circuit designs for implementation using a programmable net...

Computing system for performing colorless routing for quadruple pat...

Performing placement and routing concurrently

Constructing staging trees in hierarchical circuit designs

Engineering change order aware global routing

System and method for dynamic visual guidance of mutually paired co...

Coordinates-based generative adversarial networks for generating sy...

Leadframe with vertically spaced die attach pads

Fabricating unique chips using a charged particle multi-beamlet lit...

Semiconductor device including a gate pitch and an interconnection...

System and method for pin automation for topology editing

Build synthesized soft arrays

3D-microstrip branchline coupler

Patents Applicationslast 30 patents

AUTOMATED DESIGN CLOSURE WITH ABUTTED HIERARCHY

FEOL INTERCONNECT USED AS CAPACITANCE OVER FINS INSTEAD OF GATES

DESIGN-RULE CHECKING FOR CURVILINEAR DEVICE FEATURES

INTEGRATED CIRCUIT WITH CELLS HAVING METAL LAYER CONFIGURED BASED O...

INTEGRATED CIRCUIT WITH CIRCUIT CELLS HAVING LOWER INTERCELL ROUTIN...

INTEGRATED CIRCUIT WITH CONSTRAINED METAL LINE ARRANGEMENT

ROUTING A CELL OF A SEMICONDUCTOR CHIP

Power Grid Layout Techniques

Power Grid Porosity Techniques

DIELET DESIGN TECHNIQUES

SRAM HAVING IRREGULARLY SHAPED METAL LINES

INTERCONNECT AND TUNING THEREOF

NET ROUTING FOR INTEGRATED CIRCUIT (IC) DESIGN

METAL FILL SHAPE REMOVAL FROM SELECTED NETS

Method and Apparatus for improved Circuit Structure Thermal Reliabi...

PLACE-AND-ROUTE RESISTANCE AND CAPACITANCE OPTIMIZATION USING MULTI...

HIERARCHICAL CLOCK TREE CONSTRUCTION BASED ON CONSTRAINTS

HIERARCHICAL CLOCK TREE IMPLEMENTATION

METHOD AND SYSTEM FOR FABRICATING INTEGRATED CIRCUIT WITH AID OF PR...

VIAS WITH MULTICONNECTION VIA STRUCTURES

LAYOUT OF A MEMORY CELL OF AN INTEGRATED CIRCUIT

SYSTEM AND METHOD FOR IMPLEMENTING VERIFICATION IP FOR PRE-SILICON...

EMBEDDED FPGA TIMING SIGN-OFF

PREDICTING ROUTABILITY OF INTERCONNECTS

INTEGRATED CIRCUIT DESIGN AND FABRICATION

STANDARD CELL ARCHITECTURE WITH POWER TRACKS COMPLETELY INSIDE A CELL

PERIPHERAL TOOL

IDENTIFICATION OF HOTSPOTS IN CONGESTION ANALYSIS DURING PHYSICAL D...

SYSTEM AND METHOD FOR REDUCING SILICON AREA OF RESILIENT SYSTEMS US...

METHOD OF DESIGNING A LAYOUT FOR A SEMICONDUCTOR INTEGRATED CIRCUIT