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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures

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G06F2212/655Same page detection

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Patents Grantslast 30 patents

Information Patent Grant
Host performance booster L2P handoff
- Patent number 11,966,341
- Issue date Apr 23, 2024
- QUALCOMM Incorporated
- Madhu Yashwanth Boenapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fine-grained access memory controller
- Patent number 11,467,973
- Issue date Oct 11, 2022
- Amazon Technologies, Inc.
- Ron Diamant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process isolation for out of process page fault handling
- Patent number 11,151,051
- Issue date Oct 19, 2021
- Red Hat, Inc.
- Michael Tsirkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for performing cache maintenance over a virtua...
- Patent number 11,144,458
- Issue date Oct 12, 2021
- ARM Limited
- Jason Parker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetching data to reduce cache misses
- Patent number 10,977,176
- Issue date Apr 13, 2021
- Marvell Asia Pte, Ltd.
- David Carlson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stride prefetching across memory pages
- Patent number 10,671,535
- Issue date Jun 2, 2020
- Advanced Micro Devices, Inc.
- John Kalamatianos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for reducing first level cache energy by elimin...
- Patent number 10,671,543
- Issue date Jun 2, 2020
- Samsung Electronics Co., Ltd.
- Erik Hagersten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Filtering of redundantly scheduled write passes
- Patent number 10,592,414
- Issue date Mar 17, 2020
- International Business Machines Corporation
- Simon H. Friedmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for handling access requests
- Patent number 10,545,879
- Issue date Jan 28, 2020
- ARM Limited
- Richard F. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo-invalidating dynamic address translation (DAT) tables of a D...
- Patent number 10,528,477
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Charles E. Mari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process isolation for out of process page fault handling
- Patent number 10,437,735
- Issue date Oct 8, 2019
- Red Hat, Inc.
- Michael Tsirkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Real time memory address translation device
- Patent number 10,331,570
- Issue date Jun 25, 2019
- Avago Technologies International Sales Pte. Limited
- Flaviu Dorin Turean
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-threaded translation and transaction re-ordering for memory m...
- Patent number 10,007,619
- Issue date Jun 26, 2018
- QUALCOMM Incorporated
- Jason Edward Podaima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of controlling memory swap operation and data processing sys...
- Patent number 9,934,100
- Issue date Apr 3, 2018
- Samsung Electronics Co., Ltd.
- Sun-Young Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative addressing using a virtual address-to-physical address...
- Patent number 9,804,969
- Issue date Oct 31, 2017
- QUALCOMM Incorporated
- Suresh K. Venkumahanti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual memory mapping for improved DRAM page locality
- Patent number 9,710,392
- Issue date Jul 18, 2017
- Advanced Micro Devices, Inc.
- Syed Ali Jafri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Page crossing prefetches
- Patent number 9,563,562
- Issue date Feb 7, 2017
- NVIDIA Corporation
- Joseph Rowlands
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent page table walker control for TLB miss handling
- Patent number 9,069,690
- Issue date Jun 30, 2015
- Intel Corporation
- Gur Hildesheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Program trace message generation for page crossing events for debug
- Patent number 8,589,738
- Issue date Nov 19, 2013
- FREESCALE SEMICONDUCTOR, INC.
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing memory accesses while omitting unnecessary address trans...
- Patent number 8,285,968
- Issue date Oct 9, 2012
- International Business Machines Corporation
- Viktor S. Gyuris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address translation method and apparatus
- Patent number 8,239,657
- Issue date Aug 7, 2012
- QUALCOMM Incorporated
- Brian Joseph Kopec
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Apparatus and method to translate virtual addresses to physical add...
- Patent number 8,195,916
- Issue date Jun 5, 2012
- QUALCOMM Incorporated
- Paul Douglas Bassett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic translation in the presence of intermixed code and data
- Patent number 8,103,850
- Issue date Jan 24, 2012
- International Business Machines Corporation
- Ravi Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Collapsible front-end translation for instruction fetch
- Patent number 7,509,472
- Issue date Mar 24, 2009
- Sun Microsystems, Inc.
- Paul Caprioli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation lookaside buffer (TLB) suppression for intra-page progr...
- Patent number 7,406,613
- Issue date Jul 29, 2008
- QUALCOMM Incorporated
- James Norris Dieffenderfer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling cache miss in an instruction crossing a cache line boundary
- Patent number 7,404,042
- Issue date Jul 22, 2008
- QUALCOMM Incorporated
- Brian Michael Stempel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping an arbitrary number of contiguous memory pages at an arbitr...
- Patent number 7,181,587
- Issue date Feb 20, 2007
- Cray Inc.
- Andrew B. Hastings
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing instruction TLB accesses
- Patent number 7,076,635
- Issue date Jul 11, 2006
- Advanced Micro Devices, Inc.
- Michael G. Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for address translation pre-fetch
- Patent number 6,961,837
- Issue date Nov 1, 2005
- Intel Corporation
- Ken C. Haren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for reducing power consumption due to cache an...
- Patent number 6,678,815
- Issue date Jan 13, 2004
- Intel Corporation
- Gregory S. Mathews
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HOST PERFORMANCE BOOSTER L2P HANDOFF
- Publication number 20240160576
- Publication date May 16, 2024
- QUALCOMM Incorporated
- Madhu Yashwanth BOENAPALLI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Indexless Logical-to-Physical Translation Table
- Publication number 20230367707
- Publication date Nov 16, 2023
- Western Digital Technologies, Inc.
- Oleg Kragel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESS ISOLATION FOR OUT OF PROCESS PAGE FAULT HANDLING
- Publication number 20200042461
- Publication date Feb 6, 2020
- Red Hat, Inc.
- Michael Tsirkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESS ISOLATION FOR OUT OF PROCESS PAGE FAULT HANDLING
- Publication number 20190179767
- Publication date Jun 13, 2019
- Red Hat, Inc.
- Michael Tsirkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVELY PROCESSING DATA ASSOCIATED WITH A WORKLOAD
- Publication number 20180307618
- Publication date Oct 25, 2018
- International Business Machines Corporation
- Charles E. Mari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REAL TIME MEMORY ADDRESS TRANSLATION DEVICE
- Publication number 20180032442
- Publication date Feb 1, 2018
- BROADCOM CORPORATION
- Flaviu Dorin Turean
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MAINTENANCE INSTRUCTION
- Publication number 20180032435
- Publication date Feb 1, 2018
- ARM Limited
- Jason PARKER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF CONTROLLING MEMORY SWAP OPERATION AND DATA PROCESSING SYS...
- Publication number 20150261616
- Publication date Sep 17, 2015
- Samsung Electronics Co., Ltd.
- SUN-YOUNG LIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECULATIVE ADDRESSING USING A VIRTUAL ADDRESS-TO-PHYSICAL ADDRESS...
- Publication number 20140181459
- Publication date Jun 26, 2014
- QUAL COMM Incorporated
- Suresh K. Venkumahanti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAGE CROSSING PREFETCHES
- Publication number 20140149679
- Publication date May 29, 2014
- NVIDIA Corporation
- Joseph Rowlands
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Concurrent Control For A Page Miss Handler
- Publication number 20140075123
- Publication date Mar 13, 2014
- Gur HILDESHEIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING MEMORY ACCESSES WHILE OMITTING UNNECESSARY ADDRESS TRANS...
- Publication number 20120331262
- Publication date Dec 27, 2012
- International Business Machines Corporation
- Viktor S. Gyuris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatuses, Systems, and Methods for Reducing Translation Lookasid...
- Publication number 20110145542
- Publication date Jun 16, 2011
- QUALCOMM Incorporated
- Michael William Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAM TRACE MESSAGE GENERATION FOR PAGE CROSSING EVENTS FOR DEBUG
- Publication number 20110119533
- Publication date May 19, 2011
- FREESCALE SEMICONDUCTOR, INC.
- William C. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FACILITATING MEMORY ACCESSES
- Publication number 20110078388
- Publication date Mar 31, 2011
- International Business Machines Corporation
- Viktor S. Gyuris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Translation in the Presence of Intermixed Code and Data
- Publication number 20100287355
- Publication date Nov 11, 2010
- International Business Machines Corporation
- Ravi Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method to Translate Virtual Addresses to Physical Add...
- Publication number 20100228944
- Publication date Sep 9, 2010
- QUALCOMM Incorporated
- Paul Douglas Bassett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address Translation Method and Apparatus
- Publication number 20080189506
- Publication date Aug 7, 2008
- Brian Joseph Kopec
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Collapsible front-end translation for instruction fetch
- Publication number 20070180218
- Publication date Aug 2, 2007
- Sun Microsystems, Inc.
- Paul Caprioli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Preventing multiple translation lookaside buffer accesses for a sam...
- Publication number 20070005933
- Publication date Jan 4, 2007
- Brian Joseph Kopec
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Handling cache miss in an instruction crossing a cache line boundary
- Publication number 20060265572
- Publication date Nov 23, 2006
- Brian Michael Stempel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prefetching across a page boundary
- Publication number 20060248279
- Publication date Nov 2, 2006
- Hassan F. Al-Sukhni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method to improve hardware pre-fetching using translatio...
- Publication number 20060179236
- Publication date Aug 10, 2006
- Hazim Shafi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Translation lookaside buffer (TLB) suppression for intra-page progr...
- Publication number 20060149981
- Publication date Jul 6, 2006
- James Norris Dieffenderfer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for address translation pre-fetch
- Publication number 20040193830
- Publication date Sep 30, 2004
- Ken C. Haren
- G06 - COMPUTING CALCULATING COUNTING

Same page detection

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Host performance booster L2P handoff

Fine-grained access memory controller

Process isolation for out of process page fault handling

Apparatus and method for performing cache maintenance over a virtua...

Prefetching data to reduce cache misses

Stride prefetching across memory pages

Systems and methods for reducing first level cache energy by elimin...

Filtering of redundantly scheduled write passes

Apparatus and method for handling access requests

Pseudo-invalidating dynamic address translation (DAT) tables of a D...

Process isolation for out of process page fault handling

Real time memory address translation device

Multi-threaded translation and transaction re-ordering for memory m...

Method of controlling memory swap operation and data processing sys...

Speculative addressing using a virtual address-to-physical address...

Virtual memory mapping for improved DRAM page locality

Page crossing prefetches

Concurrent page table walker control for TLB miss handling

Program trace message generation for page crossing events for debug

Performing memory accesses while omitting unnecessary address trans...

Address translation method and apparatus

Apparatus and method to translate virtual addresses to physical add...

Dynamic translation in the presence of intermixed code and data

Collapsible front-end translation for instruction fetch

Translation lookaside buffer (TLB) suppression for intra-page progr...

Handling cache miss in an instruction crossing a cache line boundary

Mapping an arbitrary number of contiguous memory pages at an arbitr...

Method and apparatus for reducing instruction TLB accesses

Method and apparatus for address translation pre-fetch

Apparatus and method for reducing power consumption due to cache an...

Patents Applicationslast 30 patents

HOST PERFORMANCE BOOSTER L2P HANDOFF

Indexless Logical-to-Physical Translation Table

PROCESS ISOLATION FOR OUT OF PROCESS PAGE FAULT HANDLING

PROCESS ISOLATION FOR OUT OF PROCESS PAGE FAULT HANDLING

SELECTIVELY PROCESSING DATA ASSOCIATED WITH A WORKLOAD

REAL TIME MEMORY ADDRESS TRANSLATION DEVICE

CACHE MAINTENANCE INSTRUCTION

METHOD OF CONTROLLING MEMORY SWAP OPERATION AND DATA PROCESSING SYS...

SPECULATIVE ADDRESSING USING A VIRTUAL ADDRESS-TO-PHYSICAL ADDRESS...

PAGE CROSSING PREFETCHES

Concurrent Control For A Page Miss Handler

PERFORMING MEMORY ACCESSES WHILE OMITTING UNNECESSARY ADDRESS TRANS...

Apparatuses, Systems, and Methods for Reducing Translation Lookasid...

PROGRAM TRACE MESSAGE GENERATION FOR PAGE CROSSING EVENTS FOR DEBUG

FACILITATING MEMORY ACCESSES

Dynamic Translation in the Presence of Intermixed Code and Data

Apparatus and Method to Translate Virtual Addresses to Physical Add...

Address Translation Method and Apparatus

Collapsible front-end translation for instruction fetch

Preventing multiple translation lookaside buffer accesses for a sam...

Handling cache miss in an instruction crossing a cache line boundary

Prefetching across a page boundary

System and method to improve hardware pre-fetching using translatio...

Translation lookaside buffer (TLB) suppression for intra-page progr...

Method and apparatus for address translation pre-fetch