Scan chain

Industry

CPC
G11C2029/3202

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES

Current Industry

G11C2029/3202Scan chain

Industries

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit having test circuitry for memory sub-systems
- Patent number 12,181,522
- Issue date Dec 31, 2024
- NXP USA, INC.
- Alexander Hoefler
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan chain compression for testing memory of a system on a chip
- Patent number 12,112,818
- Issue date Oct 8, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
JTAG registers with concurrent inputs
- Patent number 12,072,380
- Issue date Aug 27, 2024
- Antonino Mondello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test access port architecture to facilitate multiple testing modes
- Patent number 12,057,183
- Issue date Aug 6, 2024
- Micron Technology, Inc.
- Michael Richard Spica
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for scan chain stitching
- Patent number 12,007,440
- Issue date Jun 11, 2024
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single “A” latch with an array of “B” latches
- Patent number 11,961,575
- Issue date Apr 16, 2024
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device, memory test circuit and memory test method thereof h...
- Patent number 11,935,611
- Issue date Mar 19, 2024
- Realtek Semiconductor Corporation
- Sheng-Lin Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device with design for test functionality
- Patent number 11,848,066
- Issue date Dec 19, 2023
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Grant
System including hierarchical memory modules having different types...
- Patent number 11,823,757
- Issue date Nov 21, 2023
- RAMBUS INC.
- Craig Hampel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay fault testing of pseudo static controls
- Patent number 11,768,726
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Aravinda Acharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device architecture coupled to a system-on-chip
- Patent number 11,749,369
- Issue date Sep 5, 2023
- Micron Technology, Inc.
- Antonino Mondello
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with analog measurement mode features
- Patent number 11,728,002
- Issue date Aug 15, 2023
- Micron Technology, Inc.
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital circuit testing and analysis module, system and method thereof
- Patent number 11,688,482
- Issue date Jun 27, 2023
- Numascale AS
- Thibaut Palfer-Sollier
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and associated chip
- Patent number 11,508,452
- Issue date Nov 22, 2022
- Realtek Semiconductor Corporation
- Sheng-Lin Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for scan dump of latch array
- Patent number 11,443,823
- Issue date Sep 13, 2022
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device architecture coupled to a System-on-Chip
- Patent number 11,443,821
- Issue date Sep 13, 2022
- Micron Technology, Inc.
- Antonino Mondello
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for row scannable latch array
- Patent number 11,443,822
- Issue date Sep 13, 2022
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
JTAG registers with concurrent inputs
- Patent number 11,408,935
- Issue date Aug 9, 2022
- Micron Technology, Inc.
- Antonino Mondello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with improved sensing structure
- Patent number 11,367,497
- Issue date Jun 21, 2022
- Micron Technology, Inc.
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with analog measurement mode features
- Patent number 11,348,655
- Issue date May 31, 2022
- Micron Technology, Inc.
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Grant
Direct memory access using JTAG cell addressing
- Patent number 11,309,049
- Issue date Apr 19, 2022
- Micron Technology, Inc.
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Grant
Test access port architecture to facilitate multiple testing modes
- Patent number 11,250,928
- Issue date Feb 15, 2022
- Micron Technology, Inc.
- Michael Richard Spica
- G01 - MEASURING TESTING
Information Patent Grant
Delay fault testing of pseudo static controls
- Patent number 11,194,645
- Issue date Dec 7, 2021
- Texas Instruments Incorporated
- Aravinda Acharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile computer data storage production-level programming
- Patent number 11,181,580
- Issue date Nov 23, 2021
- Raytheon Company
- Matthew S. Zobel
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan chain techniques and method of using scan chain structure
- Patent number 11,156,664
- Issue date Oct 26, 2021
- SK Hynix Inc.
- Yisu Hai
- G01 - MEASURING TESTING
Information Patent Grant
Test access port architecture to facilitate multiple testing modes
- Patent number 10,867,689
- Issue date Dec 15, 2020
- Micron Technology, Inc.
- Michael Richard Spica
- G01 - MEASURING TESTING
Information Patent Grant
System including hierarchical memory modules having different types...
- Patent number 10,755,794
- Issue date Aug 25, 2020
- RAMBUS INC.
- Craig Hampel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scannable-latch random access memory
- Patent number 10,714,207
- Issue date Jul 14, 2020
- BAE Systems Information and Electronic Systems Integration Inc.
- David D Moser
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-port register file device and method of operation in normal m...
- Patent number 10,706,949
- Issue date Jul 7, 2020
- Fujitsu Limited
- Soichiro Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit and testing method thereof
- Patent number 10,679,720
- Issue date Jun 9, 2020
- Nuvoton Technology Corporation
- Cheng-Chih Wang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TRIPLE VIA CHAIN FOR ADVANCED INTERCONNECT IN A MEMORY DEVICE
- Publication number 20250014665
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- G11 - INFORMATION STORAGE
Information Patent Application
DISTRIBUTED MRAM CONFIGURATION BIT AND METHOD OF REPAIR
- Publication number 20240420796
- Publication date Dec 19, 2024
- EVERSPIN TECHNOLOGIES, INC.
- Syed M. ALAM
- G11 - INFORMATION STORAGE
Information Patent Application
Fully Scannable Memory Arrays
- Publication number 20240412797
- Publication date Dec 12, 2024
- SambaNova Systems, Inc.
- Thomas A. ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
Method for Scanning a Memory Array
- Publication number 20240412798
- Publication date Dec 12, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN
- Publication number 20240363187
- Publication date Oct 31, 2024
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier O...
- Publication number 20240321376
- Publication date Sep 26, 2024
- QUALCOMM Incorporated
- Debarghya DUTTA
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT COMPRISING A TEST CIRCUIT, RELATED METHOD AND CO...
- Publication number 20240295604
- Publication date Sep 5, 2024
- STMicroelectronics International N.V.
- Gianluca TORTORA
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
- Publication number 20240249791
- Publication date Jul 25, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Register Bank Architecture with Latches
- Publication number 20240249790
- Publication date Jul 25, 2024
- ARM Limited
- Yannis Jallamion-Grive
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY
- Publication number 20240170087
- Publication date May 23, 2024
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH IMPROVED SENSING STRUCTURE
- Publication number 20230410930
- Publication date Dec 21, 2023
- Micron Technology, Inc.
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY
- Publication number 20230317192
- Publication date Oct 5, 2023
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device, memory test circuit and memory test method thereof h...
- Publication number 20230031828
- Publication date Feb 2, 2023
- REALTEK SEMICONDUCTOR CORPORATION
- SHENG-LIN LIN
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
- Publication number 20230005560
- Publication date Jan 5, 2023
- SambaNova Systems, Inc.
- Thomas A. ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE ARCHITECTURE COUPLED TO A SYSTEM-ON-CHIP
- Publication number 20230005561
- Publication date Jan 5, 2023
- Micron Technology, Inc.
- Antonino Mondello
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN CHAIN COMPRESSION FOR TESTING MEMORY OF A SYSTEM ON A CHIP
- Publication number 20230005562
- Publication date Jan 5, 2023
- Synopsys, Inc.
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH ANALOG MEASUREMENT MODE FEATURES
- Publication number 20220293203
- Publication date Sep 15, 2022
- Micron Technology, Inc.
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND CIRCUIT FOR ROW SCANNABLE LATCH ARRAY
- Publication number 20220139477
- Publication date May 5, 2022
- SambaNova Systems, Inc.
- Thomas A. ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND CIRCUIT FOR SCAN DUMP OF LATCH ARRAY
- Publication number 20220139478
- Publication date May 5, 2022
- SambaNova Systems, Inc.
- Thomas A. ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT AND ASSOCIATED CHIP
- Publication number 20220130481
- Publication date Apr 28, 2022
- REALTEK SEMICONDUCTOR CORPORATION
- SHENG-LIN LIN
- G01 - MEASURING TESTING
Information Patent Application
DIRECT MEMORY ACCESS USING JTAG CELL ADDRESSING
- Publication number 20210335438
- Publication date Oct 28, 2021
- Micron Technology, Inc.
- Alberto Troia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
A MEMORY DEVICE ARCHITECTURE COUPLED TO A SYSTEM-ON-CHIP
- Publication number 20210335439
- Publication date Oct 28, 2021
- Micron Technology, Inc.
- Antonino Mondello
- G11 - INFORMATION STORAGE
Information Patent Application
JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION
- Publication number 20210335435
- Publication date Oct 28, 2021
- Micron Technology, Inc.
- Alberto Troia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY DEVICE WITH ANALOG MEASUREMENT MODE FEATURES
- Publication number 20210327526
- Publication date Oct 21, 2021
- Micron Technology, Inc.
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH IMPROVED SENSING STRUCTURE
- Publication number 20210287757
- Publication date Sep 16, 2021
- Micron Technology, Inc.
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE COMPUTER DATA STORAGE PRODUCTION-LEVEL PROGRAMMING
- Publication number 20210102997
- Publication date Apr 8, 2021
- Raytheon Company
- Matthew S. Zobel
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM INCLUDING HIERARCHICAL MEMORY MODULES HAVING DIFFERENT TYPES...
- Publication number 20210035652
- Publication date Feb 4, 2021
- Rambus Inc.
- Craig Hampel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN CHAIN TECHNIQUES AND METHOD OF USING SCAN CHAIN STRUCTURE
- Publication number 20200132767
- Publication date Apr 30, 2020
- SK HYNIX INC.
- Yisu HAI
- G11 - INFORMATION STORAGE
Information Patent Application
SCANNABLE-LATCH RANDOM ACCESS MEMORY
- Publication number 20200105360
- Publication date Apr 2, 2020
- DAVID D. MOSER
- G11 - INFORMATION STORAGE
Information Patent Application
SIMULTANEOUS SCAN CHAIN INITIALIZATION WITH DISPARATE LATCHES
- Publication number 20190156907
- Publication date May 23, 2019
- International Business Machines Corporation
- Mitesh Agrawal
- G11 - INFORMATION STORAGE

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Integrated circuit having test circuitry for memory sub-systems

Scan chain compression for testing memory of a system on a chip

JTAG registers with concurrent inputs

Test access port architecture to facilitate multiple testing modes

Systems and methods for scan chain stitching

Single “A” latch with an array of “B” latches

Memory device, memory test circuit and memory test method thereof h...

Programmable logic device with design for test functionality

System including hierarchical memory modules having different types...

Delay fault testing of pseudo static controls

Memory device architecture coupled to a system-on-chip

Memory device with analog measurement mode features

Digital circuit testing and analysis module, system and method thereof

Circuit and associated chip

Method and circuit for scan dump of latch array

Memory device architecture coupled to a System-on-Chip

Method and circuit for row scannable latch array

JTAG registers with concurrent inputs

Memory device with improved sensing structure

Memory device with analog measurement mode features

Direct memory access using JTAG cell addressing

Test access port architecture to facilitate multiple testing modes

Delay fault testing of pseudo static controls

Non-volatile computer data storage production-level programming

Scan chain techniques and method of using scan chain structure

Test access port architecture to facilitate multiple testing modes

System including hierarchical memory modules having different types...

Scannable-latch random access memory

Multi-port register file device and method of operation in normal m...

Memory circuit and testing method thereof

Patents Applicationslast 30 patents

TRIPLE VIA CHAIN FOR ADVANCED INTERCONNECT IN A MEMORY DEVICE

DISTRIBUTED MRAM CONFIGURATION BIT AND METHOD OF REPAIR

Fully Scannable Memory Arrays

Method for Scanning a Memory Array

AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN

Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier O...

INTEGRATED CIRCUIT COMPRISING A TEST CIRCUIT, RELATED METHOD AND CO...

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

Register Bank Architecture with Latches

PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY

MEMORY DEVICE WITH IMPROVED SENSING STRUCTURE

PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY

Memory device, memory test circuit and memory test method thereof h...

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

MEMORY DEVICE ARCHITECTURE COUPLED TO A SYSTEM-ON-CHIP

SCAN CHAIN COMPRESSION FOR TESTING MEMORY OF A SYSTEM ON A CHIP

MEMORY DEVICE WITH ANALOG MEASUREMENT MODE FEATURES

METHOD AND CIRCUIT FOR ROW SCANNABLE LATCH ARRAY

METHOD AND CIRCUIT FOR SCAN DUMP OF LATCH ARRAY

CIRCUIT AND ASSOCIATED CHIP

DIRECT MEMORY ACCESS USING JTAG CELL ADDRESSING

A MEMORY DEVICE ARCHITECTURE COUPLED TO A SYSTEM-ON-CHIP

JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION

MEMORY DEVICE WITH ANALOG MEASUREMENT MODE FEATURES

MEMORY DEVICE WITH IMPROVED SENSING STRUCTURE

NON-VOLATILE COMPUTER DATA STORAGE PRODUCTION-LEVEL PROGRAMMING

SYSTEM INCLUDING HIERARCHICAL MEMORY MODULES HAVING DIFFERENT TYPES...

SCAN CHAIN TECHNIQUES AND METHOD OF USING SCAN CHAIN STRUCTURE

SCANNABLE-LATCH RANDOM ACCESS MEMORY

SIMULTANEOUS SCAN CHAIN INITIALIZATION WITH DISPARATE LATCHES