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G06F7/49994

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F7/49994Sign extension

Industries

Patents Grantslast 30 patents

Information Patent Grant
Increased precision neural processing element
- Patent number 12,154,027
- Issue date Nov 26, 2024
- Microsoft Technology Licensing, LLC
- Amol A. Ambardekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for forming constant extensions in the same execute packet i...
- Patent number 11,681,532
- Issue date Jun 20, 2023
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Increased precision neural processing element
- Patent number 11,604,972
- Issue date Mar 14, 2023
- Microsoft Technology Licensing, LLC
- Amol A. Ambardekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple modes for handling overflow conditions resulting from arit...
- Patent number 11,169,777
- Issue date Nov 9, 2021
- Graphcore Limited
- Alan Graham Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core for a data processing engine in an integrated circuit
- Patent number 10,747,531
- Issue date Aug 18, 2020
- Xilinx, Inc.
- Jan Langer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for forming constant extensions in the same execute packet i...
- Patent number 10,620,957
- Issue date Apr 14, 2020
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating sign extensions for loads
- Patent number 10,126,976
- Issue date Nov 13, 2018
- International Business Machines Corporation
- Michael K. Gschwind
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating sign extensions for loads
- Patent number 9,600,194
- Issue date Mar 21, 2017
- International Business Machines Corporation
- Michael K. Gschwind
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to implement a matrix multiply unit of a broadban...
- Patent number 8,943,119
- Issue date Jan 27, 2015
- MicroUnity Systems Engineering, Inc.
- Craig Hansen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplier architecture utilizing a uniform array of logic blocks,...
- Patent number 8,527,572
- Issue date Sep 3, 2013
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DSP engine with implicit mixed sign operands
- Patent number 8,495,125
- Issue date Jul 23, 2013
- Microchip Technology Incorporated
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to implement a matrix multiply unit of a broadban...
- Patent number 8,195,735
- Issue date Jun 5, 2012
- MicroUnity Systems Engineering, Inc.
- Craig Hansen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-efficient sign extension for booth multiplication methods and...
- Patent number 7,797,366
- Issue date Sep 14, 2010
- QUALCOMM Incorporated
- Shankar Krithivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compute-centric architecture for integrated circuits
- Patent number 7,746,108
- Issue date Jun 29, 2010
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for performing parallel integer multiply accumula...
- Patent number 7,716,269
- Issue date May 11, 2010
- Cradle Technologies
- Moshe B. Simon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for digital signal processing, program product th...
- Patent number 7,711,761
- Issue date May 4, 2010
- STMicroelectronics S.r.l.
- Daniele Lo Iacono
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital signal processor with efficient multi-modal multiplier
- Patent number 7,587,443
- Issue date Sep 8, 2009
- Altera Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fixed length memory to memory arithmetic and architecture for direc...
- Patent number 7,546,442
- Issue date Jun 9, 2009
- Ubicom, Inc.
- David A. Fotland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing packed shift operations in a pro...
- Patent number 7,461,109
- Issue date Dec 2, 2008
- Intel Corporation
- Derrick Chu Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing packed shift operations in a pro...
- Patent number 7,451,169
- Issue date Nov 11, 2008
- Intel Corporation
- Derrick Chu Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power vector summation apparatus
- Patent number 7,328,227
- Issue date Feb 5, 2008
- Agere Systems Inc.
- Kameran Azadet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for aligning operands for a processor
- Patent number 7,320,013
- Issue date Jan 15, 2008
- Adaptec, Inc.
- Shridhar Mukund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for DMA transfer of data in scatter/gather mode
- Patent number 7,249,202
- Issue date Jul 24, 2007
- Cradle Technologies, Inc.
- Moshe B. Simon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing packed shift operations in a pro...
- Patent number 7,117,232
- Issue date Oct 3, 2006
- Intel Corporation
- Derrick Chu Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power vector summation method and apparatus
- Patent number 7,085,794
- Issue date Aug 1, 2006
- Agere Systems Inc.
- Kameran Azadet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fixed length memory to memory arithmetic and architecture for a com...
- Patent number 7,047,396
- Issue date May 16, 2006
- Ubicom, Inc.
- David A. Fotland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for performing parallel integer multiply accumula...
- Patent number 7,043,518
- Issue date May 9, 2006
- Cradle Technologies, Inc.
- Moshe B. Simon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiply accumulator for two N bit multipliers and an M bit addend
- Patent number 7,043,517
- Issue date May 9, 2006
- Faraday Technology Corp.
- Chi-jui Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiler for enabling multiple signed independent data elements per...
- Patent number 7,039,906
- Issue date May 2, 2006
- International Business Machines Corporation
- Jennifer Q. Trelewicz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing signed multiplication of oper...
- Patent number 6,973,471
- Issue date Dec 6, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Trinh Huy Nguyen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Forming Constant Extensions in the Same Execute Packet in a VLIW Pr...
- Publication number 20230325189
- Publication date Oct 12, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASED PRECISION NEURAL PROCESSING ELEMENT
- Publication number 20230196086
- Publication date Jun 22, 2023
- Microsoft Technology Licensing, LLC
- Amol A. AMBARDEKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE FOR BIT UP-CONVERSION WITH SIGN EXTENSION
- Publication number 20220326909
- Publication date Oct 13, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Anshu JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASED PRECISION NEURAL PROCESSING ELEMENT
- Publication number 20200410329
- Publication date Dec 31, 2020
- Microsoft Technology Licensing, LLC
- Amol A. AMBARDEKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Forming Constant Extensions in the Same Execute Packet i...
- Publication number 20200310807
- Publication date Oct 1, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OVERFLOW CONDITION
- Publication number 20200201600
- Publication date Jun 25, 2020
- Graphcore Limited
- Alan Graham Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAN...
- Publication number 20120215826
- Publication date Aug 23, 2012
- MicroUnity Systems Engineering, Inc.
- Craig HANSEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DSP Engine with Implicit Mixed Sign Operands
- Publication number 20100306292
- Publication date Dec 2, 2010
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR SIGN-EXTENSION IN A MULTI-PRECISION MULTIPLIER
- Publication number 20090198758
- Publication date Aug 6, 2009
- International Business Machines Corporation
- Harry S. Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAN...
- Publication number 20090094309
- Publication date Apr 9, 2009
- MicroUnity Systems Engineering, Inc.
- Craig HANSEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Full-Adder Modules and Multiplier Devices Using the Same
- Publication number 20080256165
- Publication date Oct 16, 2008
- NXP B.V.
- Rohini Krishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PROVIDING PACKED SHIFT OPERATIONS IN A PRO...
- Publication number 20070239810
- Publication date Oct 11, 2007
- Derrick Chu Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power-efficient sign extension for booth multiplication methods and...
- Publication number 20070192399
- Publication date Aug 16, 2007
- Shankar Krithivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for providing packed shift operations in a pro...
- Publication number 20060235914
- Publication date Oct 19, 2006
- Derrick Chu Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low power vector summation method and apparatus
- Publication number 20060143259
- Publication date Jun 29, 2006
- Kameran Azadet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for digital signal processing, program product th...
- Publication number 20060020653
- Publication date Jan 26, 2006
- STMicroelectronics S.r. I.
- Daniele Lo Iacono
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for performing parallel integer multiply accumula...
- Publication number 20050235026
- Publication date Oct 20, 2005
- Cradle Technologies, Inc.
- Moshe B. Simon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for providing packed shift operations in a pro...
- Publication number 20050219897
- Publication date Oct 6, 2005
- Derrick Chu Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiplier sign extension method and architecture
- Publication number 20050223054
- Publication date Oct 6, 2005
- Yu-Cheng Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for DMA transfer of data in scatter/gather mode
- Publication number 20050027901
- Publication date Feb 3, 2005
- Moshe B. Simon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for performing parallel integer multiply accumula...
- Publication number 20050027773
- Publication date Feb 3, 2005
- Erik P. Machnicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for performing single instruction multiple data operations o...
- Publication number 20050027969
- Publication date Feb 3, 2005
- Moshe B. Simon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for aligning operands for a processor
- Publication number 20040210610
- Publication date Oct 21, 2004
- Adaptec, Inc.
- Shridhar Mukund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiply accumulator for two N bit multipliers and an M bit addend
- Publication number 20040177104
- Publication date Sep 9, 2004
- Chi-jui Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Linear summation multiplier array implementation for both signed an...
- Publication number 20040024804
- Publication date Feb 5, 2004
- Richard B. Zeng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for performing packed shift operations
- Publication number 20040024800
- Publication date Feb 5, 2004
- Derrick Chu Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Converting bits to vectors in a programmable logic device
- Publication number 20040000927
- Publication date Jan 1, 2004
- Lattice Semiconductor Corporation
- Conrad Dante
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low power vector summation method and apparatus
- Publication number 20030195906
- Publication date Oct 16, 2003
- Kameran Azadet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for implementing signed multiplication of oper...
- Publication number 20030163503
- Publication date Aug 28, 2003
- Trinh Huy Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Double precision floating point multiplier having a 32-bit booth-en...
- Publication number 20030005016
- Publication date Jan 2, 2003
- Sun Microsystems, Inc.
- Tzungren Allan Tzeng
- G06 - COMPUTING CALCULATING COUNTING

Sign extension

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Increased precision neural processing element

Method for forming constant extensions in the same execute packet i...

Increased precision neural processing element

Multiple modes for handling overflow conditions resulting from arit...

Core for a data processing engine in an integrated circuit

Method for forming constant extensions in the same execute packet i...

Integrating sign extensions for loads

Integrating sign extensions for loads

System and method to implement a matrix multiply unit of a broadban...

Multiplier architecture utilizing a uniform array of logic blocks,...

DSP engine with implicit mixed sign operands

System and method to implement a matrix multiply unit of a broadban...

Power-efficient sign extension for booth multiplication methods and...

Compute-centric architecture for integrated circuits

Method and system for performing parallel integer multiply accumula...

Method and system for digital signal processing, program product th...

Digital signal processor with efficient multi-modal multiplier

Fixed length memory to memory arithmetic and architecture for direc...

Method and apparatus for providing packed shift operations in a pro...

Method and apparatus for providing packed shift operations in a pro...

Low power vector summation apparatus

Method and apparatus for aligning operands for a processor

System and method for DMA transfer of data in scatter/gather mode

Method and apparatus for providing packed shift operations in a pro...

Low power vector summation method and apparatus

Fixed length memory to memory arithmetic and architecture for a com...

Method and system for performing parallel integer multiply accumula...

Multiply accumulator for two N bit multipliers and an M bit addend

Compiler for enabling multiple signed independent data elements per...

Method and apparatus for implementing signed multiplication of oper...

Patents Applicationslast 30 patents

Forming Constant Extensions in the Same Execute Packet in a VLIW Pr...

INCREASED PRECISION NEURAL PROCESSING ELEMENT

TECHNIQUE FOR BIT UP-CONVERSION WITH SIGN EXTENSION

INCREASED PRECISION NEURAL PROCESSING ELEMENT

Method for Forming Constant Extensions in the Same Execute Packet i...

OVERFLOW CONDITION

SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAN...

DSP Engine with Implicit Mixed Sign Operands

METHOD FOR SIGN-EXTENSION IN A MULTI-PRECISION MULTIPLIER

SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAN...

Full-Adder Modules and Multiplier Devices Using the Same

METHOD AND APPARATUS FOR PROVIDING PACKED SHIFT OPERATIONS IN A PRO...

Power-efficient sign extension for booth multiplication methods and...

Method and apparatus for providing packed shift operations in a pro...

Low power vector summation method and apparatus

Method and system for digital signal processing, program product th...

Method and system for performing parallel integer multiply accumula...

Method and apparatus for providing packed shift operations in a pro...

Multiplier sign extension method and architecture

System and method for DMA transfer of data in scatter/gather mode

Method and system for performing parallel integer multiply accumula...

Method for performing single instruction multiple data operations o...

Method and apparatus for aligning operands for a processor

Multiply accumulator for two N bit multipliers and an M bit addend

Linear summation multiplier array implementation for both signed an...

Method and apparatus for performing packed shift operations

Converting bits to vectors in a programmable logic device

Low power vector summation method and apparatus

Method and apparatus for implementing signed multiplication of oper...

Double precision floating point multiplier having a 32-bit booth-en...