Space or buffer allocation for DMA transfers

Industry

CPC
G06F2213/2806

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Current Industry

G06F2213/2806Space or buffer allocation for DMA transfers

Industries

Patents Grantslast 30 patents

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Elastic method of remote direct memory access memory advertisement
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Bit manipulation capable direct memory access
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Opportunistic cache injection of data into lower latency levels of...
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Method and apparatus for protecting a PCI device controller from ma...
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Memory management for finite automata processing
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Information Patent Grant
Optimized credit return mechanism for packet sends
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Engine architecture for processing finite automata
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System and method for supporting a lazy sorting priority queue in a...
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Generating a non-deterministic finite automata (NFA) graph for regu...
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Optimized credit return mechanism for packet sends
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System and method for assigning memory access transfers between com...
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- FREESCALE SEMICONDUCTOR, INC.
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Shared and managed memory unified access
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Multi-lane concurrent bag for facilitating inter-thread communication
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Method of operating a computer system by identifying source code co...
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- Issue date Jan 1, 2002
- Hewlett-Packard Company
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Information Patent Grant
Memory architecture for a computer system
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Bit Manipulation Capable Direct Memory Access
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DIRECT MEMORY ACCESS FOR CO-PROCESSOR MEMORY
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STORAGE APPARATUS ACCESSED BY USING MEMORY BUS
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OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS
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SYSTEM AND METHOD FOR ASSIGNING MEMORY ACCESS TRANSFERS BETWEEN COM...
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SHARED AND MANAGED MEMORY UNIFIED ACCESS
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Multi-Lane Concurrent Bag for Facilitating Inter-Thread Communication
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Space or buffer allocation for DMA transfers

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Asymmetric read / write architecture for enhanced throughput and re...

Computing system for transmitting completion early between serially...

Asymmetric read / write architecture for enhanced throughput and re...

Fixed ethernet frame descriptor

Semiconductor device and systems using the same

Elastic method of remote direct memory access memory advertisement

Fixed ethernet frame descriptor

Apparatus and method for processing burst read transactions

Bit manipulation capable direct memory access

Computer and control method for computer

Storage apparatus accessed by using memory bus

Direct memory access for co-processor memory

Engine architecture for processing finite automata

Throughput in openfabrics environments

Opportunistic cache injection of data into lower latency levels of...

Method and apparatus for protecting a PCI device controller from ma...

Optimized credit return mechanism for packet sends

Methods and systems for direct memory access operations

Memory management for finite automata processing

Optimized credit return mechanism for packet sends

Engine architecture for processing finite automata

System and method for supporting a lazy sorting priority queue in a...

Generating a non-deterministic finite automata (NFA) graph for regu...

System and method to traverse a non-deterministic finite automata (...

Optimized credit return mechanism for packet sends

System and method for assigning memory access transfers between com...

Shared and managed memory unified access

Multi-lane concurrent bag for facilitating inter-thread communication

Method of operating a computer system by identifying source code co...

Memory architecture for a computer system

Patents Applicationslast 30 patents

INPUT AND OUTPUT SPATIAL CROPPING OPERATIONS IN NEURAL PROCESSOR CI...

ACCELERATION OF NETWORK INTERFACE DEVICE TRANSACTIONS USING COMPUTE...

Asymmetric Read / Write Architecture for Enhanced Throughput and Re...

PERIPHERAL COMPONENT INTERCONNECT EXPRESS DEVICE AND METHOD OF OPER...

SYSTEMS AND METHODS FOR ENABLING CONCURRENT APPLICATIONS TO PERFORM...

COMPUTING SYSTEM FOR TRANSMITTING COMPLETION EARLY BETWEEN SERIALLY...

FIXED ETHERNET FRAME DESCRIPTOR

APPARATUS AND METHOD FOR PROCESSING BURST READ TRANSACTIONS

FIXED ETHERNET FRAME DESCRIPTOR

Bit Manipulation Capable Direct Memory Access

DIRECT MEMORY ACCESS FOR CO-PROCESSOR MEMORY

COMPUTER AND CONTROL METHOD FOR COMPUTER

STORAGE APPARATUS ACCESSED BY USING MEMORY BUS

OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS

ENGINE ARCHITECTURE FOR PROCESSING FINITE AUTOMATA

METHOD AND APPARATUS FOR PROTECTING A PCI DEVICE CONTROLLER FROM MA...

OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS

SYSTEM AND METHOD FOR SUPPORTING A LAZY SORTING PRIORITY QUEUE IN A...

DIRECT MEMORY ACCESS CONTROLLER, CONTROL METHOD THEREOF, AND INFORM...

Memory Management for Finite Automata Processing

SYSTEM AND METHOD FOR ASSIGNING MEMORY ACCESS TRANSFERS BETWEEN COM...

SHARED AND MANAGED MEMORY UNIFIED ACCESS

Multi-Lane Concurrent Bag for Facilitating Inter-Thread Communication