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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2217/00Indexing scheme relating to computer aided design [CAD]

Current Industry

G06F2217/72Spare resources

Industries

Patents Grantslast 30 patents

Information Patent Grant
Programmable logic integrated circuit, design support system, and c...
- Patent number 10,740,435
- Issue date Aug 11, 2020
- NEC Corporation
- Noboru Sakimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Safety analysis system for wiring
- Patent number 10,319,057
- Issue date Jun 11, 2019
- MITSUBISHI AIRCRAFT CORPORATION
- Koji Toyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for placing and routing partial reconfiguratio...
- Patent number 10,242,146
- Issue date Mar 26, 2019
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reliability of an electronic device
- Patent number 10,042,969
- Issue date Aug 7, 2018
- GLOBALFOUNDRIES Inc.
- Lars W. Liebmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dummy gate placement methodology to enhance integrated circuit perf...
- Patent number 9,947,765
- Issue date Apr 17, 2018
- Texas Instruments Incorporated
- Younsung Choi
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Methods for modifying an integrated circuit layout design
- Patent number 9,747,401
- Issue date Aug 29, 2017
- GLOBALFOUNDRIES, INC.
- Ayman Hamouda
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Network stochastic cross-layer optimization for meeting traffic flo...
- Patent number 9,722,912
- Issue date Aug 1, 2017
- Google Inc.
- Xiaoxue Zhao
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dummy gate placement methodology to enhance integrated circuit perf...
- Patent number 9,496,142
- Issue date Nov 15, 2016
- Texas Instruments Incorporated
- Younsung Choi
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method and apparatus for placing and routing partial reconfiguratio...
- Patent number 9,361,421
- Issue date Jun 7, 2016
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for modifying an integrated circuit layout design
- Patent number 9,317,645
- Issue date Apr 19, 2016
- GLOBALFOUNDRIES, INC.
- Ayman Hamouda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methodology for preventing functional failure caused by CDM ESD
- Patent number 9,239,896
- Issue date Jan 19, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Choshu Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying partial good voltage island structures
- Patent number 9,172,373
- Issue date Oct 27, 2015
- GlobalFoundries U.S. 2 LLC
- Kevin W. Gorman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of generating data for estimating resource requirements for...
- Patent number 9,117,046
- Issue date Aug 25, 2015
- Xilinx, Inc.
- Paul R. Schumacher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing performance degradation in backup semiconductor chips
- Patent number 9,110,777
- Issue date Aug 18, 2015
- International Business Machines Corporation
- Aditya Bansal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and apparatus to improve reliability of isolated vias
- Patent number 8,987,916
- Issue date Mar 24, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing redundant via insertion during...
- Patent number 8,984,470
- Issue date Mar 17, 2015
- Synopsys, Inc.
- Abhijit Chakanakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for bypassing silicon bugs
- Patent number 8,791,713
- Issue date Jul 29, 2014
- Advanced Micro Devices, Inc.
- William L. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of implementing timing engineering change order
- Patent number 8,776,000
- Issue date Jul 8, 2014
- National Chiao Tung University
- Hua-Yu Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Satisfying routing rules during circuit design
- Patent number 8,745,565
- Issue date Jun 3, 2014
- Synopsys, Inc.
- Tong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to improve reliability of vias
- Patent number 8,703,507
- Issue date Apr 22, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for placement and routing of partial reconfigu...
- Patent number 8,671,377
- Issue date Mar 11, 2014
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Spare cell insertion based on reachable state analysis
- Patent number 8,661,391
- Issue date Feb 25, 2014
- International Business Machines Corporation
- Manikandan Viswanath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable gate array as drivers for data ports of spare latches
- Patent number 8,638,120
- Issue date Jan 28, 2014
- International Business Machines Corporation
- Ashish Jaitly
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Spare latch distribution
- Patent number 8,572,536
- Issue date Oct 29, 2013
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing routing optimization during circuit design
- Patent number 8,490,042
- Issue date Jul 16, 2013
- Synopsys, Inc.
- Tong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods of designing integrated circuits
- Patent number 8,473,888
- Issue date Jun 25, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ta-Pen Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing using a dynamic grid
- Patent number 8,458,640
- Issue date Jun 4, 2013
- Synopsys, Inc.
- Tong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor layer forming method and structure
- Patent number 8,341,588
- Issue date Dec 25, 2012
- International Business Machines Corporation
- Robert D. Herzl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing spare latch placement quality determination
- Patent number 8,296,707
- Issue date Oct 23, 2012
- International Business Machines Corporation
- Michael David Amundson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stress reduction on vias and yield improvement in layout design thr...
- Patent number 8,276,104
- Issue date Sep 25, 2012
- Spansion LLC
- Gregory Sylvester Emmanuel
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SAFETY ANALYSIS SYSTEM FOR WIRING
- Publication number 20180053278
- Publication date Feb 22, 2018
- MITSUBISHI AIRCRAFT CORPORATION
- Koji TOYAMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SAFETY ANALYSIS SYSTEM FOR WIRING
- Publication number 20140297207
- Publication date Oct 2, 2014
- MITSUBISHI AIRCRAFT CORPORATION
- Koji TOYAMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Placing and Routing Partial Reconfiguratio...
- Publication number 20140237441
- Publication date Aug 21, 2014
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO IMPROVE RELIABILITY OF VIAS
- Publication number 20140091475
- Publication date Apr 3, 2014
- DOUGLAS M. REBER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF IMPLEMENTING TIMING ENGINEERING CHANGE ORDER
- Publication number 20130298097
- Publication date Nov 7, 2013
- National Taiwan University
- Hua-Yu Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TERMINAL DEVICE AND METHOD FOR REALIZING ANALOGUE CIRCUIT IN TERMIN...
- Publication number 20130214849
- Publication date Aug 22, 2013
- ZTE CORPORATION
- Weiwei Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING PERFORMANCE DEGRADATION IN BACKUP SEMICONDUCTOR CHIPS
- Publication number 20130212414
- Publication date Aug 15, 2013
- International Business Machines Corporation
- Aditya Bansal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR IMPLEMENTING SPARE LOGIC OF SEMICONDUCTOR MEMORY APPARAT...
- Publication number 20130155753
- Publication date Jun 20, 2013
- SK HYNIX INC.
- Young Suk MOON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO IMPROVE RELIABILITY OF ISOLATED VIAS
- Publication number 20130134595
- Publication date May 30, 2013
- DOUGLAS M. REBER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Self-healing and reconfiguration in an integrated circuit
- Publication number 20130111071
- Publication date May 2, 2013
- International Business Machines Corporation
- Gerald Kreissig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARE LATCH DISTRIBUTION
- Publication number 20130080989
- Publication date Mar 28, 2013
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE GATE ARRAY AS DRIVERS FOR DATA PORTS OF SPARE LATCHES
- Publication number 20130076391
- Publication date Mar 28, 2013
- International Business Machines Corporation
- Ashish Jaitly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS OF DESIGNING INTEGRATED CIRCUITS
- Publication number 20120240088
- Publication date Sep 20, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ta-Pen GUO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Placement and Routing of Partial Reconfigu...
- Publication number 20120227026
- Publication date Sep 6, 2012
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRESS REDUCTION ON VIAS AND YIELD IMPROVEMENT IN LAYOUT DESIGN THR...
- Publication number 20120151430
- Publication date Jun 14, 2012
- Gregory Sylvester EMMANUEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING SPARE LATCH PLACEMENT QUALITY DETERMINATION
- Publication number 20120124541
- Publication date May 17, 2012
- International Business Machines Corporation
- Michael David Amundson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR LAYER FORMING METHOD AND STRUCTURE
- Publication number 20120083913
- Publication date Apr 5, 2012
- International Business Machines Corporation
- Robert D. Herzl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STABILITY-DEPENDENT SPARE CELL INSERTION
- Publication number 20120066654
- Publication date Mar 15, 2012
- International Business Machines Corporation
- Jeremy T. Hopkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONE-AWARE SPARE CELL PLACEMENT USING HYPERGRAPH CONNECTIVITY ANALYSIS
- Publication number 20120054707
- Publication date Mar 1, 2012
- International Business Machines Corporation
- Benjiman L. Goodman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR BYPASSING SILICON BUGS
- Publication number 20110309855
- Publication date Dec 22, 2011
- WILLIAM L. WALKER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING REDUNDANT VIA INSERTION DURING...
- Publication number 20110055785
- Publication date Mar 3, 2011
- Synopsys, Inc.
- Abhijit Chakanakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SATISFYING ROUTING RULES DURING CIRCUIT DE...
- Publication number 20110055786
- Publication date Mar 3, 2011
- Synopsys, Inc.
- Tong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING ROUTING OPTIMIZATION DURING CIR...
- Publication number 20110055791
- Publication date Mar 3, 2011
- Synopsys, Inc.
- Tong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ROUTING USING A DYNAMIC GRID
- Publication number 20110055788
- Publication date Mar 3, 2011
- Synopsys, Inc.
- Tong Gao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN METHODOLOGY FOR PREVENTING FUNCTIONAL FAILURE CAUSED BY CDM ESD
- Publication number 20100100859
- Publication date Apr 22, 2010
- LSI Corporation
- Choshu Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF DESIGNING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STA...
- Publication number 20090307637
- Publication date Dec 10, 2009
- Susan K. Lichtensteiger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Assessing Resources Required to Complete a VLSI Design
- Publication number 20090259977
- Publication date Oct 15, 2009
- Derick G. Behrends
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT CIRCUIT HAVING A COMBINED TIE CELL
- Publication number 20090249273
- Publication date Oct 1, 2009
- MEDIATEK INC.
- Tung-Kai Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Verification of Spare Latch Placement in Synthesized Macros
- Publication number 20090210832
- Publication date Aug 20, 2009
- International Business Machines Corporation
- Michael Hemsley Wood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Selecting Spares to Implement a Design Change in an...
- Publication number 20090172608
- Publication date Jul 2, 2009
- Jeremy T. Hopkins
- G06 - COMPUTING CALCULATING COUNTING

Spare resources

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Programmable logic integrated circuit, design support system, and c...

Safety analysis system for wiring

Method and apparatus for placing and routing partial reconfiguratio...

Reliability of an electronic device

Dummy gate placement methodology to enhance integrated circuit perf...

Methods for modifying an integrated circuit layout design

Network stochastic cross-layer optimization for meeting traffic flo...

Dummy gate placement methodology to enhance integrated circuit perf...

Method and apparatus for placing and routing partial reconfiguratio...

Methods for modifying an integrated circuit layout design

Methodology for preventing functional failure caused by CDM ESD

Verifying partial good voltage island structures

Method of generating data for estimating resource requirements for...

Reducing performance degradation in backup semiconductor chips

Methods and apparatus to improve reliability of isolated vias

Method and apparatus for performing redundant via insertion during...

Method and apparatus for bypassing silicon bugs

Method of implementing timing engineering change order

Satisfying routing rules during circuit design

Method and apparatus to improve reliability of vias

Method and apparatus for placement and routing of partial reconfigu...

Spare cell insertion based on reachable state analysis

Programmable gate array as drivers for data ports of spare latches

Spare latch distribution

Performing routing optimization during circuit design

Systems and methods of designing integrated circuits

Routing using a dynamic grid

Semiconductor layer forming method and structure

Implementing spare latch placement quality determination

Stress reduction on vias and yield improvement in layout design thr...

Patents Applicationslast 30 patents

SAFETY ANALYSIS SYSTEM FOR WIRING

SAFETY ANALYSIS SYSTEM FOR WIRING

Method and Apparatus for Placing and Routing Partial Reconfiguratio...

METHOD AND APPARATUS TO IMPROVE RELIABILITY OF VIAS

METHOD OF IMPLEMENTING TIMING ENGINEERING CHANGE ORDER

TERMINAL DEVICE AND METHOD FOR REALIZING ANALOGUE CIRCUIT IN TERMIN...

REDUCING PERFORMANCE DEGRADATION IN BACKUP SEMICONDUCTOR CHIPS

METHOD FOR IMPLEMENTING SPARE LOGIC OF SEMICONDUCTOR MEMORY APPARAT...

METHODS AND APPARATUS TO IMPROVE RELIABILITY OF ISOLATED VIAS

Self-healing and reconfiguration in an integrated circuit

SPARE LATCH DISTRIBUTION

PROGRAMMABLE GATE ARRAY AS DRIVERS FOR DATA PORTS OF SPARE LATCHES

SYSTEMS AND METHODS OF DESIGNING INTEGRATED CIRCUITS

Method and Apparatus for Placement and Routing of Partial Reconfigu...

STRESS REDUCTION ON VIAS AND YIELD IMPROVEMENT IN LAYOUT DESIGN THR...

IMPLEMENTING SPARE LATCH PLACEMENT QUALITY DETERMINATION

SEMICONDUCTOR LAYER FORMING METHOD AND STRUCTURE

STABILITY-DEPENDENT SPARE CELL INSERTION

CONE-AWARE SPARE CELL PLACEMENT USING HYPERGRAPH CONNECTIVITY ANALYSIS

METHOD AND APPARATUS FOR BYPASSING SILICON BUGS

METHOD AND APPARATUS FOR PERFORMING REDUNDANT VIA INSERTION DURING...

METHOD AND APPARATUS FOR SATISFYING ROUTING RULES DURING CIRCUIT DE...

METHOD AND APPARATUS FOR PERFORMING ROUTING OPTIMIZATION DURING CIR...

METHOD AND APPARATUS FOR ROUTING USING A DYNAMIC GRID

DESIGN METHODOLOGY FOR PREVENTING FUNCTIONAL FAILURE CAUSED BY CDM ESD

METHOD OF DESIGNING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STA...

Assessing Resources Required to Complete a VLSI Design

LAYOUT CIRCUIT HAVING A COMBINED TIE CELL

Verification of Spare Latch Placement in Synthesized Macros

Techniques for Selecting Spares to Implement a Design Change in an...