Testing of logic operation

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F11/00Error detection Error correction Monitoring

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G06F11/25Testing of logic operation

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Patents Grantslast 30 patents

Information Patent Grant
JTAG-based burning device
- Patent number 11,874,323
- Issue date Jan 16, 2024
- INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD
- Peng Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for debugging server startup sequence in debugging method ap...
- Patent number 11,797,375
- Issue date Oct 24, 2023
- Fulian Precision Electronics (Tianjin) Co., LTD.
- Xiao-Long Zhou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling of scenario models for execution within different comput...
- Patent number 11,748,240
- Issue date Sep 5, 2023
- Breker Verification Systems
- Adnan Hamid
- G01 - MEASURING TESTING
Information Patent Grant
Vehicle control system verification device, vehicle control system,...
- Patent number 11,151,076
- Issue date Oct 19, 2021
- HITACHI AUTOMOTIVE SYSTEMS, LTD.
- Satoshi Otsuka
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Apparatuses and methods for a multiple master capable debug interface
- Patent number 11,138,083
- Issue date Oct 5, 2021
- Intel Corporation
- Patrik Eder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Display in a graphical format of test results generated using scena...
- Patent number 11,113,184
- Issue date Sep 7, 2021
- Breker Verification Systems
- Adnan Hamid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer device and testing method for basic input/output system
- Patent number 11,068,369
- Issue date Jul 20, 2021
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Tzu-Pin Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing SoC with portable scenario models and at different levels
- Patent number 11,055,212
- Issue date Jul 6, 2021
- Breker Verification Systems
- Adnan Hamid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus packet format displaying method for logic analyzer
- Patent number 11,038,992
- Issue date Jun 15, 2021
- Zeroplus Technology Co., Ltd.
- Sung-Hui Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory circuit and method of operating a memory circuit
- Patent number 10,937,469
- Issue date Mar 2, 2021
- Infineon Technologies AG
- Jan Otterstedt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling of scenario models for execution within different comput...
- Patent number 10,838,006
- Issue date Nov 17, 2020
- Breker Verification Systems
- Adnan Hamid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single circuit fault detection
- Patent number 10,830,816
- Issue date Nov 10, 2020
- Panasonic Corporation
- Omid Oliaei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accessing a passenger transportation device control means
- Patent number 10,776,523
- Issue date Sep 15, 2020
- Kone Corporation
- Sampo Ahokas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device and method for concurrently analyzing a plurality of telecom...
- Patent number 10,705,938
- Issue date Jul 7, 2020
- David Webster
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CMOS process skew sensor
- Patent number 10,571,516
- Issue date Feb 25, 2020
- ARM Limited
- Bal S. Sandhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Full memory logical erase for circuit verification
- Patent number 10,546,081
- Issue date Jan 28, 2020
- Mentor Graphics Corporation
- Khaled Salah Mohamed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On demand data stream controller for programming and executing oper...
- Patent number 10,541,043
- Issue date Jan 21, 2020
- Cadence Design Systems, Inc.
- Carl Alexander Wisnesky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory circuit including overlay memory cells and method of operati...
- Patent number 10,497,408
- Issue date Dec 3, 2019
- Infineon Technologies AG
- Jan Otterstedt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic analyzer for integrated circuits
- Patent number 10,482,205
- Issue date Nov 19, 2019
- Xilinx, Inc.
- Akhilesh Mahajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for a multiple master capable debug interface
- Patent number 10,481,990
- Issue date Nov 19, 2019
- Intel Corporation
- Patrik Eder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing SOC with portable scenario models and at different levels
- Patent number 10,429,442
- Issue date Oct 1, 2019
- Breker Verification Systems
- Adnan Hamid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock selection circuit and test clock generation circuit for LBIST...
- Patent number 10,393,804
- Issue date Aug 27, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Scheduling of scenario models for execution within different comput...
- Patent number 10,365,326
- Issue date Jul 30, 2019
- Breker Verification Systems
- Adnan Hamid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan compression architecture for highly compressed designs and ass...
- Patent number 10,354,742
- Issue date Jul 16, 2019
- STMicroelectronics International N.V.
- Swapnil Bahl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test decompressor and test method thereof
- Patent number 10,324,130
- Issue date Jun 18, 2019
- National Cheng Kung University
- Kuen-Jong Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Board level leakage testing for memory interface
- Patent number 10,319,453
- Issue date Jun 11, 2019
- Intel Corporation
- Lakshminarayana Pappu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test circuit to debug missed test clock pulses
- Patent number 10,302,700
- Issue date May 28, 2019
- STMicroelectronics, Inc.
- Vinay Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Persistent command parameter table for pre-silicon device testing
- Patent number 10,289,512
- Issue date May 14, 2019
- International Business Machines Corporation
- Dean G. Bair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
JTAG lockout for embedded processors in programmable devices
- Patent number 10,267,858
- Issue date Apr 23, 2019
- Hamilton Sundstrand Corporation
- Kirk A. Lillestolen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic to test transactional execution status
- Patent number 10,261,879
- Issue date Apr 16, 2019
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM FOR DEBUGGING SERVER STARTUP SEQUENCE IN DEBUGGING METHOD AP...
- Publication number 20230168963
- Publication date Jun 1, 2023
- Fulian Precision Electronics (Tianjin) Co., LTD.
- XIAO-LONG ZHOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduling Of Scenario Models For Execution Within Different Comput...
- Publication number 20210073113
- Publication date Mar 11, 2021
- Breker Verification Systems
- Adnan Hamid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER DEVICE AND TESTING METHOD FOR BASIC INPUT/OUTPUT SYSTEM
- Publication number 20200379859
- Publication date Dec 3, 2020
- INVENTEC (PUDONG) TECHNOLOGY CORPORATION
- Tzu-Pin WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CIRCUIT AND METHOD OF OPERATING A MEMORY CIRCUIT
- Publication number 20200066312
- Publication date Feb 27, 2020
- INFINEON TECHNOLOGIES AG
- Jan OTTERSTEDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR A MULTIPLE MASTER CAPABLE DEBUG INTERFACE
- Publication number 20200034260
- Publication date Jan 30, 2020
- Intel Corporation
- PATRIK EDER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING SOC WITH PORTABLE SCENARIO MODELS AND AT DIFFERENT LEVELS
- Publication number 20190391204
- Publication date Dec 26, 2019
- Breker Verification Systems
- Adnan Hamid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduling Of Scenario Models For Execution Within Different Comput...
- Publication number 20190317147
- Publication date Oct 17, 2019
- Breker Verification Systems
- Adnan Hamid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Vehicle Control System Verification Device, Vehicle Control System,...
- Publication number 20190108160
- Publication date Apr 11, 2019
- Hitachi Automotive Systems, Ltd.
- Satoshi OTSUKA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Full Memory Logical Erase For Circuit Verification
- Publication number 20190087522
- Publication date Mar 21, 2019
- Mentor Graphics Corporation
- Khaled Salah Mohamed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK SELECTION CIRCUIT AND TEST CLOCK GENERATION CIRCUIT FOR LBIST...
- Publication number 20190064268
- Publication date Feb 28, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
JTAG LOCKOUT FOR EMBEDDED PROCESSORS IN PROGRAMMABLE DEVICES
- Publication number 20180292458
- Publication date Oct 11, 2018
- HAMILTON SUNDSTRAND CORPORATION
- Kirk A. Lillestolen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST CIRCUIT TO DEBUG MISSED TEST CLOCK PULSES
- Publication number 20180284192
- Publication date Oct 4, 2018
- STMicroelectronics, Inc.
- Vinay Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE CIRCUIT FAULT DETECTION
- Publication number 20180284188
- Publication date Oct 4, 2018
- InvenSense, Inc.
- Omid Oliaei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOARD LEVEL LEAKAGE TESTING FOR MEMORY INTERFACE
- Publication number 20180268915
- Publication date Sep 20, 2018
- Intel Corporation
- Lakshminarayana Pappu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESSING A PASSENGER TRANSPORTATION DEVICE CONTROL MEANS
- Publication number 20180211066
- Publication date Jul 26, 2018
- KONE Corporation
- Sampo AHOKAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CIRCUIT AND METHOD OF OPERATING A MEMORY CIRCUIT
- Publication number 20180158534
- Publication date Jun 7, 2018
- INFINEON TECHNOLOGIES AG
- Jan OTTERSTEDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC GENERATION OF AN EXCEPTION DETECTOR FOR DETERMINING AN OV...
- Publication number 20180137030
- Publication date May 17, 2018
- Microsoft Technology Licensing, LLC
- Shachar Raindel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduling Of Scenario Models For Execution Within Different Comput...
- Publication number 20180136277
- Publication date May 17, 2018
- Breker Verification Systems
- Adnan Hamid
- G01 - MEASURING TESTING
Information Patent Application
TEST DECOMPRESSOR AND TEST METHOD THEREOF
- Publication number 20180120378
- Publication date May 3, 2018
- National Cheng Kung University
- KUEN-JONG LEE
- G01 - MEASURING TESTING
Information Patent Application
PERSISTENT COMMAND PARAMETER TABLE FOR PRE-SILICON DEVICE TESTING
- Publication number 20180018250
- Publication date Jan 18, 2018
- International Business Machines Corporation
- Dean G. Bair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST APPARATUS, MEMORY TEST SYSTEM, AND TEST METHOD
- Publication number 20170372792
- Publication date Dec 28, 2017
- SK HYNIX INC.
- Hak Song KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR A MULTIPLE MASTER CAPABLE DEBUG INTERFACE
- Publication number 20170356961
- Publication date Dec 14, 2017
- Intel Corporation
- PATRIK EDER
- G01 - MEASURING TESTING
Information Patent Application
Device And Method For Concurrently Analyzing A Plurality Of Telecom...
- Publication number 20170322858
- Publication date Nov 9, 2017
- David Webster
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONDITION MONITORING DEVICE AND CONDITION MONITORING METHOD FOR EXT...
- Publication number 20170284386
- Publication date Oct 5, 2017
- Mitsubishi Heavy Industries, Ltd.
- Akihiro NAKANIWA
- F04 - POSITIVE DISPLACEMENT MACHINES FOR LIQUIDS PUMPS FOR LIQUIDS OR ELASTIC...
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20170285106
- Publication date Oct 5, 2017
- RENESAS ELECTRONICS CORPORATION
- Yoichi MAEDA
- G01 - MEASURING TESTING
Information Patent Application
SCHEDULING OF SCENARIO MODELS FOR EXECUTION WITHIN DIFFERENT COMPUT...
- Publication number 20170227603
- Publication date Aug 10, 2017
- Breker Verification Systems
- Adnan Hamid
- G01 - MEASURING TESTING
Information Patent Application
Memory circuit defect correction
- Publication number 20170186500
- Publication date Jun 29, 2017
- Intel Corporation
- Ravi H. Motwani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST APPARATUS AND TESTABLE ASYNCHRONOUS CIRCUIT
- Publication number 20170160340
- Publication date Jun 8, 2017
- Huawei Technologies Co., Ltd
- Zhen XU
- G01 - MEASURING TESTING
Information Patent Application
SCAN COMPRESSION ARCHITECTURE FOR HIGHLY COMPRESSED DESIGNS AND ASS...
- Publication number 20170140838
- Publication date May 18, 2017
- STMicroelectronics International N.V
- Swapnil BAHL
- G01 - MEASURING TESTING
Information Patent Application
HIGH SPEED FUNCTIONAL TEST VECTORS IN LOW POWER TEST CONDITIONS OF...
- Publication number 20170091059
- Publication date Mar 30, 2017
- Oracle International Corporation
- Ali Vahidsafa
- G06 - COMPUTING CALCULATING COUNTING

Testing of logic operation

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

JTAG-based burning device

System for debugging server startup sequence in debugging method ap...

Scheduling of scenario models for execution within different comput...

Vehicle control system verification device, vehicle control system,...

Apparatuses and methods for a multiple master capable debug interface

Display in a graphical format of test results generated using scena...

Computer device and testing method for basic input/output system

Testing SoC with portable scenario models and at different levels

Bus packet format displaying method for logic analyzer

Memory circuit and method of operating a memory circuit

Scheduling of scenario models for execution within different comput...

Single circuit fault detection

Accessing a passenger transportation device control means

Device and method for concurrently analyzing a plurality of telecom...

CMOS process skew sensor

Full memory logical erase for circuit verification

On demand data stream controller for programming and executing oper...

Memory circuit including overlay memory cells and method of operati...

Logic analyzer for integrated circuits

Apparatuses and methods for a multiple master capable debug interface

Testing SOC with portable scenario models and at different levels

Clock selection circuit and test clock generation circuit for LBIST...

Scheduling of scenario models for execution within different comput...

Scan compression architecture for highly compressed designs and ass...

Test decompressor and test method thereof

Board level leakage testing for memory interface

Test circuit to debug missed test clock pulses

Persistent command parameter table for pre-silicon device testing

JTAG lockout for embedded processors in programmable devices

Instruction and logic to test transactional execution status

Patents Applicationslast 30 patents

SYSTEM FOR DEBUGGING SERVER STARTUP SEQUENCE IN DEBUGGING METHOD AP...

Scheduling Of Scenario Models For Execution Within Different Comput...

COMPUTER DEVICE AND TESTING METHOD FOR BASIC INPUT/OUTPUT SYSTEM

MEMORY CIRCUIT AND METHOD OF OPERATING A MEMORY CIRCUIT

APPARATUSES AND METHODS FOR A MULTIPLE MASTER CAPABLE DEBUG INTERFACE

TESTING SOC WITH PORTABLE SCENARIO MODELS AND AT DIFFERENT LEVELS

Scheduling Of Scenario Models For Execution Within Different Comput...

Vehicle Control System Verification Device, Vehicle Control System,...

Full Memory Logical Erase For Circuit Verification

CLOCK SELECTION CIRCUIT AND TEST CLOCK GENERATION CIRCUIT FOR LBIST...

JTAG LOCKOUT FOR EMBEDDED PROCESSORS IN PROGRAMMABLE DEVICES

TEST CIRCUIT TO DEBUG MISSED TEST CLOCK PULSES

SINGLE CIRCUIT FAULT DETECTION

BOARD LEVEL LEAKAGE TESTING FOR MEMORY INTERFACE

ACCESSING A PASSENGER TRANSPORTATION DEVICE CONTROL MEANS

MEMORY CIRCUIT AND METHOD OF OPERATING A MEMORY CIRCUIT

AUTOMATIC GENERATION OF AN EXCEPTION DETECTOR FOR DETERMINING AN OV...

Scheduling Of Scenario Models For Execution Within Different Comput...

TEST DECOMPRESSOR AND TEST METHOD THEREOF

PERSISTENT COMMAND PARAMETER TABLE FOR PRE-SILICON DEVICE TESTING

TEST APPARATUS, MEMORY TEST SYSTEM, AND TEST METHOD

APPARATUSES AND METHODS FOR A MULTIPLE MASTER CAPABLE DEBUG INTERFACE

Device And Method For Concurrently Analyzing A Plurality Of Telecom...

CONDITION MONITORING DEVICE AND CONDITION MONITORING METHOD FOR EXT...

SEMICONDUCTOR DEVICE

SCHEDULING OF SCENARIO MODELS FOR EXECUTION WITHIN DIFFERENT COMPUT...

Memory circuit defect correction

TEST APPARATUS AND TESTABLE ASYNCHRONOUS CIRCUIT

SCAN COMPRESSION ARCHITECTURE FOR HIGHLY COMPRESSED DESIGNS AND ASS...

HIGH SPEED FUNCTIONAL TEST VECTORS IN LOW POWER TEST CONDITIONS OF...