the controlled phase shifter comprising coarse and fine delay or phase-shifting means

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CPC
H03L7/0818

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HELECTRICITY H03Electronic circuits H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES H03L7/00Automatic control of frequency or phase Synchronisation

Current Industry

H03L7/0818the controlled phase shifter comprising coarse and fine delay or phase-shifting means

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Patents Grantslast 30 patents

Information Patent Grant
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the controlled phase shifter comprising coarse and fine delay or phase-shifting means

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Field programmable platform array

Digital frequency synthesizer

Low jitter clock multiplier circuit and method with arbitrary frequ...

ASGPR-binding compounds for the degradation of extracellular proteins

Methods and apparatus to retime data using a programmable delay

ASGPR-binding compounds for the degradation of extracellular proteins

Phase alignment of signals of different frequencies

Systems and methods for PLL duty cycle calibration

Clock jitter and spurious tone cancellation system using optical delay

Methods and circuits for slew-rate calibration

Delta-sigma modulator with modified quantization error shaping

Generating divided signals from phase-locked loop (PLL) output when...

Integrated circuit and memory system

Clock synthesizer

Systems and methods for PLL gain calibration

ASGPR-binding compounds for the degradation of extracellular proteins

Systems and methods for PLL gain calibration and duty cycle calibra...

Compact digital delay locked loop

ASGPR-binding compounds for the degradation of extracellular proteins

Clock scheme circuit and a mobile double data rate memory using the...

Digital phase locked loop and methods of operating same

Delay lock loop circuits and methods for operating same

Clock generation circuit and semiconductor apparatus using the cloc...

Ring oscillator, random number generator including the same, and op...

Time-to-digital converter circuitry

Methods and apparatus to retime data using a programmable delay

Digital system synchronization

Systems and methods for providing a delay-locked loop with coarse t...

Generating divided signals from phase-locked loop (PLL) output when...

Synchronization between data and clock signals in high-speed interf...

Patents Applicationslast 30 patents

DIGITAL DELAY LINE OF A MEMORY SYSTEM AND METHOD OF ADJUSTING TIMIN...

Circuit and Method for Data Recovery

METHODS AND APPARATUS TO RETIME DATA USING A PROGRAMMABLE DELAY

ASGPR-BINDING COMPOUNDS FOR THE DEGRADATION OF EXTRACELLULAR PROTEINS

SYSTEMS AND METHODS FOR PLL DUTY CYCLE CALIBRATION

MULTIPHASE CLOCK GENERATOR

METHODS AND CIRCUITS FOR SLEW-RATE CALIBRATION

PHASE ALIGNMENT OF SIGNALS OF DIFFERENT FREQUENCIES

MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME

ERROR DETECTORS AND MEMORY DEVICES HAVING ERROR DETECTORS THEREIN,...

DELAY-LOCKED LOOP (DLL) WITH BINARY SEARCH LOCKING AND DEAD CLOCK D...

Low Noise, Supply Rejecting Linear Phase Interpolator

Clock Synchronization System and Method

ASGPR-BINDING COMPOUNDS FOR THE DEGRADATION OF EXTRACELLULAR PROTEINS

DIGITAL FREQUENCY SYNTHESIZER

Clock Synthesizer

Delay Lock Loop Circuits and Methods for Operating Same

DIGITAL PHASE LOCKED LOOP AND METHODS OF OPERATING SAME

PROGRAMMABLE CIRCUIT, INTEGRATED CIRCUIT, AND ELECTRONIC DEVICE

FREQUENCY OFFSET OF A CLOCK SIGNAL

MULTI-PHASE CLOCK GENERATION DEVICE

SYNCHRONIZATION CIRCUIT AND METHOD

SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION AND DUTY CYCLE CALIBRA...

SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION

ASGPR-BINDING COMPOUNDS FOR THE DEGRADATION OF EXTRACELLULAR PROTEINS

SYSTEMS AND METHODS FOR PLL DUTY CYCLE CALIBRATION

METHODS AND APPARATUS TO RETIME DATA USING A PROGRAMMABLE DELAY

CLOCK JITTER AND SPURIOUS TONE CANCELLATION SYSTEM USING OPTICAL DELAY

ASGPR-BINDING COMPOUNDS FOR THE DEGRADATION OF EXTRACELLULAR PROTEINS

CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE