the reference signal being additionally directly applied to the generator

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H03L7/083

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HELECTRICITY H03Electronic circuits H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES H03L7/00Automatic control of frequency or phase Synchronisation

Current Industry

H03L7/083the reference signal being additionally directly applied to the generator

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Patents Grantslast 30 patents

Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Clock synchronization in a network using a distributed pulse signal
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Cycle slip detection and correction in phase-locked loop
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Information Patent Grant
Hybrid single loop feedback retiming circuit
- Patent number 10,860,052
- Issue date Dec 8, 2020
- California Institute of Technology
- Matan Gal
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
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RETIMER WITH SLICER LEVEL ADJUSTMENT
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the reference signal being additionally directly applied to the generator

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Clock synthesizer

Systems and methods for PLL gain calibration

Systems and methods for PLL gain calibration and duty cycle calibra...

Methods and systems for controlling frequency and phase variations...

Methods and systems for controlling frequency variation for a PLL r...

Ring oscillator, random number generator including the same, and op...

Clock frequency limiter

Digital system synchronization

Clock synchronization in a network using a distributed pulse signal

Phase-locked loop reference clock management

Delay locked loop including replica fine delay circuit and memory d...

Clock signal generation circuit and method, and electronic device

Digital phase-locked loop with fast output frequency digital control

Calibration method, calibration device and multi-phase clock circuit

Phase-locked loop (PLL) with direct feedforward circuit

Fractional-N ADPLL with reference dithering

Increased phase interpolator linearity in phase-locked loop

Clock synthesizer

System reference (SYSREF) signal system and method

Multi-channel high-speed converter clock synchronization with auton...

Memory device and clock locking method thereof

Time-to-digital converter

Phase-locked loop (PLL) with direct feedforward circuit

Method of detecting jitter in clock of apparatus and apparatus util...

DPLL restart without frequency overshoot

Low noise quadrature signal generation

Quadrature local oscillator signal generation systems and methods

Phase-locked loop (PLL) with direct feedforward circuit

Cycle slip detection and correction in phase-locked loop

Hybrid single loop feedback retiming circuit

Patents Applicationslast 30 patents

DIGITAL FREQUENCY SYNTHESIZER

Clock Synthesizer

SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION AND DUTY CYCLE CALIBRA...

SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION

SYSTEMS AND METHODS FOR PLL DUTY CYCLE CALIBRATION

CLOCK SWITCHING METHOD AND APPARATUS, ELECTRONIC DEVICE, AND COMPUT...

Clock Frequency Limiter

PLL CIRCUIT AND TRANSMISSION SYSTEM

Media communication system and media communication apparatus and me...

PHASE-LOCKED LOOP REFERENCE CLOCK MANAGEMENT

DEVICE AND METHOD FOR MULTI-CHIP CLOCK SYNCHRONIZATION

RETIMER WITH SLICER LEVEL ADJUSTMENT

PHASE-LOCKED LOOP (PLL) WITH DIRECT FEEDFORWARD CIRCUIT

Clock Frequency Limiter

Clock Synthesizer

METHODS AND SYSTEMS FOR CONTROLLING FREQUENCY AND PHASE VARIATIONS...

DELAY LOCKED LOOP INCLUDING REPLICA FINE DELAY CIRCUIT AND MEMORY D...

INCREASED PHASE INTERPOLATOR LINEARITY IN PHASE-LOCKED LOOP

CLOCK SIGNAL GENERATION CIRCUIT

CALIBRATION METHOD, CALIBRATION DEVICE AND MULTI-PHASE CLOCK CIRCUIT

RING OSCILLATOR, RANDOM NUMBER GENERATOR INCLUDING THE SAME, AND OP...

Clock Synthesizer

PHASE-LOCKED LOOP (PLL) WITH DIRECT FEEDFORWARD CIRCUIT

CLOCK SIGNAL GENERATION CIRCUIT AND METHOD, AND ELECTRONIC DEVICE

DIGITAL PHASE-LOCKED LOOP WITH FAST OUTPUT FREQUENCY DIGITAL CONTROL

DIGITAL SYSTEM SYNCHRONIZATION

MEMORY DEVICE AND CLOCK LOCKING METHOD THEREOF

LOW NOISE QUADRATURE SIGNAL GENERATION

PHASE-LOCKED LOOP (PLL) WITH DIRECT FEEDFORWARD CIRCUIT

PHASE CANCELLATION IN A PHASE-LOCKED LOOP