Thread control instructions

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CPC
G06F9/3009

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/3009Thread control instructions

Industries

Patents Grantslast 30 patents

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Page faulting and selective preemption
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Digital messages in a load control system
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Multi-threading processor and operating method thereof
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One-dimensional zero padding in a stream of matrix elements
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Register freeing latency
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Matrix data scatter and gather between rows and irregularly spaced...
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Execution or write mask generation for data selection in a multi-th...
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Method and apparatus for vector permutation
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Methods and apparatus to generate graphics processing unit long ins...
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System call management in a user-mode, multi-threaded, self-schedul...
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Patents Applicationslast 30 patents

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Group Thread Dispatch for Graph Streaming Processor
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DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS
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Thread control instructions

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Upgrade infrastucture with integration points

Reconfigurable arithmetic engine circuit

Apparatuses, methods, and systems for instructions for a hardware a...

Concurrent multi-datatype execution within a processing resource

Method for detecting reverse engineering on a processor using an in...

Tracking streaming engine vector predicates to control processor ex...

Neuron using posits

Processor-guided execution of offloaded instructions using fixed fu...

PIM search stop control

Commanded JTAG test access port operations

Framework for preventing cascading failures across layers of a syst...

Computing 2-body statistics on graphics processing units (GPUs)

Global coherence operations

Systems and methods of resource configuration optimization for mach...

Thread scheduling control and memory splitting in a barrel processor

System and method for synchronizing processing between a plurality...

Manycore system for performing execution of multi-threads in asynch...

Page faulting and selective preemption

Digital messages in a load control system

Multi-threading processor and operating method thereof

One-dimensional zero padding in a stream of matrix elements

Register freeing latency

Matrix data scatter and gather between rows and irregularly spaced...

Memory-independent and scalable state component initialization for...

Method for processing multiple transactions converted from single t...

Memory bandwidth monitoring extensible counter

Execution or write mask generation for data selection in a multi-th...

Method and apparatus for vector permutation

Methods and apparatus to generate graphics processing unit long ins...

System call management in a user-mode, multi-threaded, self-schedul...

Patents Applicationslast 30 patents

DYNAMIC ACCUMULATOR ALLOCATION

METHOD AND APPARATUS FOR VECTOR PERMUTATION

INTERRUPT HANDLING

PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT

VARIABLE LATENCY INSTRUCTIONS

Group Thread Dispatch for Graph Streaming Processor

UPDATE OF SEAMLESS CONTAINER IN VEHICLES SYSTEM BASED ON CONTAINER

VECTOR COMPARISON AND/OR POPULATION COUNT OPERATIONS

DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS

IN-VEHICLE DEVICE AND METHOD TO BE EXECUTED BY IN-VEHICLE DEVICE

Communication Processor Handling Communications Protocols on Separa...

TASK EXECUTION ORDER DETERMINATION SYSTEM AND TASK EXECUTION METHOD

CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE

METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS

DYNAMICALLY GENERATED OPERATIONS IN A PARALLEL PROCESSING FRAMEWORK

REGISTER CONFIGURATION TECHNIQUE USING METRICS

TWO-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS

STORAGE ORGANIZATION FOR TRANSPOSING A MATRIX USING A STREAMING ENGINE

ERRONEOUS-WRITING-TO-REGISTER PREVENTION CIRCUIT, MICROCONTROLLER,...

COMPUTING DEVICE AND METHOD OF SCHEDULING FOR EXECUTING PLURALITY O...

PIPELINE FOR PROCESSING TRANSACTIONS

Vector Based Matrix Multiplication

SORTING VECTOR ELEMENTS USING A COUNT VALUE

CACHE WITH SET ASSOCIATIVITY HAVING DATA DEFINED CACHE SETS

PSEUDO-RANDOM WAY SELECTION

SYSTEM, APPARATUS AND METHOD FOR FINE-GRAIN ADDRESS SPACE SELECTION...

CACHE MANAGEMENT METHOD, APPARATUS, AND SYSTEM, AND STORAGE MEDIUM

MANYCORE SYSTEM FOR PERFORMING EXECUTION OF MULTI-THREADS IN ASYNCH...

METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MUL...

WAVE LEVEL MATRIX MULTIPLY INSTRUCTIONS