Timing analysis and optimization

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CPC
G06F2217/84

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2217/00Indexing scheme relating to computer aided design [CAD]

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G06F2217/84Timing analysis and optimization

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Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for inter-die block level design
- Patent number 10,664,564
- Issue date May 26, 2020
- Xcelsis Corporation
- Javier A Delacruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slack time recycling
- Patent number 10,657,210
- Issue date May 19, 2020
- Mentor Graphics Corporation
- Brian Etscheid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying circuits based on timing reports for critical paths
- Patent number 10,650,113
- Issue date May 12, 2020
- International Business Machines Corporation
- Rina Kipnis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Glitch detection at clock domain crossing
- Patent number 10,635,767
- Issue date Apr 28, 2020
- Mentor Graphics Corporation
- Sulabh Kumar Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic multi-clock circuit generation
- Patent number 10,629,161
- Issue date Apr 21, 2020
- National Instruments Corporation
- Hojin Kee
- G01 - MEASURING TESTING
Information Patent Grant
Interactive incremental synthesis flow for integrated circuit design
- Patent number 10,614,188
- Issue date Apr 7, 2020
- The Regents of the University of California
- Jose Renau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of manufacturing semiconductor devices by etching active fi...
- Patent number 10,615,080
- Issue date Apr 7, 2020
- Samsung Electronics Co., Ltd.
- Min-Chul Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor process and performance sensor
- Patent number 10,614,184
- Issue date Apr 7, 2020
- ATLAZO, INC.
- Shahin Solki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing clock power consumption of a computer processor
- Patent number 10,614,183
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Erez Barak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constructing staging trees in hierarchical circuit designs
- Patent number 10,616,103
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Harald Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying equivalence of design latency
- Patent number 10,606,979
- Issue date Mar 31, 2020
- Xilinx, Inc.
- Shangzhi Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Engineering change order aware global routing
- Patent number 10,606,976
- Issue date Mar 31, 2020
- International Business Machines Corporation
- Michael A Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selection of corners and/or margins using statistical static timing...
- Patent number 10,606,970
- Issue date Mar 31, 2020
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, design program, and design apparatus of a high level synthe...
- Patent number 10,606,972
- Issue date Mar 31, 2020
- SOCIONEXT INC.
- Atsushi Yasunaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design analyzer
- Patent number 10,599,792
- Issue date Mar 24, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal clock network analysis, visualization, verification and gene...
- Patent number 10,599,800
- Issue date Mar 24, 2020
- Synopsys, Inc.
- Mohamed Shaker Sarwary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parasitic extraction based on compact representation of process cal...
- Patent number 10,592,628
- Issue date Mar 17, 2020
- Mentor Graphics Corporation
- Sandeep Koranne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing clock power consumption of a computer processor
- Patent number 10,585,995
- Issue date Mar 10, 2020
- International Business Machines Corporation
- Erez Barak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Die resistance-capacitance extraction and validation
- Patent number 10,585,996
- Issue date Mar 10, 2020
- Seagate Technology LLC
- Nitin Kumar Chhabra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for utilizing estimations for register retimin...
- Patent number 10,586,004
- Issue date Mar 10, 2020
- Altera Corporation
- Nishanth Sinnadurai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable connectivity verification using conditional cut-points
- Patent number 10,579,770
- Issue date Mar 3, 2020
- International Business Machines Corporation
- Pradeep Kumar Nalla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective conditional stall for hardware-based circuit design verif...
- Patent number 10,579,776
- Issue date Mar 3, 2020
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical synthesis within placement
- Patent number 10,572,621
- Issue date Feb 25, 2020
- Xilinx, Inc.
- Zhiyong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling automatic staging for nets or net groups with VHDL attributes
- Patent number 10,572,618
- Issue date Feb 25, 2020
- International Business Machines Corporation
- Manuel Beck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for layout design and structure with inter-layer vias
- Patent number 10,566,278
- Issue date Feb 18, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Lin Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing-adaptive, configurable logic architecture
- Patent number 10,565,339
- Issue date Feb 18, 2020
- Mellanox Technologies, Ltd.
- Uria Basher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pessimism reduction in cross-talk noise determination used in integ...
- Patent number 10,565,336
- Issue date Feb 18, 2020
- International Business Machines Corporation
- Jason D. Morsey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit simulation using a recording of a reference execution
- Patent number 10,565,337
- Issue date Feb 18, 2020
- OPTIMA DESIGN AUTOMATION LTD
- Jamil Raja Mazzawi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying a circuit design
- Patent number 10,568,203
- Issue date Feb 18, 2020
- International Business Machines Corporation
- Ofer Geva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for virtual clock and mode extraction in hierarchical...
- Patent number 10,558,782
- Issue date Feb 11, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EFFICIENT PROJECTION BASED ADJUSTMENT EVALUATION IN STATIC TIMING A...
- Publication number 20210103637
- Publication date Apr 8, 2021
- International Business Machines Corporation
- Chaitanya Ravindra Peddawad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODULAR EVENT-BASED PERFORMANCE MONITORING IN INTEGRATED CIRCUIT DE...
- Publication number 20210097146
- Publication date Apr 1, 2021
- International Business Machines Corporation
- Lahiruka Winter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK GATING LATCH PLACEMENT
- Publication number 20210073344
- Publication date Mar 11, 2021
- International Business Machines Corporation
- Jesse SURPRISE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OUT-OF-CONTEXT FEEDBACK HIERARCHICAL LARGE BLOCK SYNTHESIS (HLBS) O...
- Publication number 20210073343
- Publication date Mar 11, 2021
- International Business Machines Corporation
- Frank Musante
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINK-BASED WIRE TAGGING IN MULTI-SINK INTEGRATED CIRCUIT NET
- Publication number 20210064711
- Publication date Mar 4, 2021
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPERCONDUCTING CIRCUIT WITH VIRTUAL TIMING ELEMENTS AND RELATED ME...
- Publication number 20210064718
- Publication date Mar 4, 2021
- Microsoft Technology Licensing, LLC
- Janet L. Schneider
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FEEDBACK-AWARE SLACK STEALING ACROSS TRANSPARENT LATCHES EMPOWERING...
- Publication number 20210011980
- Publication date Jan 14, 2021
- International Business Machines Corporation
- Chaitanya Ravindra Peddawad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINISTIC TEST PATTERN GENERATION FOR DESIGNS WITH TIMING EXCEP...
- Publication number 20200410065
- Publication date Dec 31, 2020
- Mentor Graphics Corporation
- Wu-Tung Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR CIRCUIT TIMING FIXING USING EXTENSION META...
- Publication number 20200401668
- Publication date Dec 24, 2020
- Samsung Electronics Co., Ltd.
- Hongda LU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL CLOCK TREE IMPLEMENTATION
- Publication number 20200401673
- Publication date Dec 24, 2020
- Samsung Electronics Co., Ltd.
- Hongda LU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL CLOCK TREE CONSTRUCTION BASED ON CONSTRAINTS
- Publication number 20200401179
- Publication date Dec 24, 2020
- Samsung Electronics Co., Ltd.
- Sridhar SUBRAMANIAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVELY GROUNDING FILL WIRES
- Publication number 20200387580
- Publication date Dec 10, 2020
- International Business Machines Corporation
- Steven Joseph Kurtz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC LAYER TRAIT GENERATION AND PROMOTION COST COMPUTATION
- Publication number 20200380082
- Publication date Dec 3, 2020
- International Business Machines Corporation
- Stephen Thomas Quay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHIP HEALTH MONITOR
- Publication number 20200334118
- Publication date Oct 22, 2020
- NXP. B.V.
- Jurgen Geerlings
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR COMPACT NEURAL NETWORK MODELING OF TRANSISTORS
- Publication number 20200320366
- Publication date Oct 8, 2020
- Samsung Electronics Co., Ltd.
- Jing Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING MODEL, TIMING MODEL BUILDING METHOD, AND RELATED TOP-LEVEL A...
- Publication number 20200311218
- Publication date Oct 1, 2020
- Global Unichip Corporation
- Meng-Hsiu TSAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CYCLE LATCH TREE SYNTHESIS
- Publication number 20200311221
- Publication date Oct 1, 2020
- International Business Machines Corporation
- Lakshmi N. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EMBEDDED FPGA TIMING SIGN-OFF
- Publication number 20200311219
- Publication date Oct 1, 2020
- Achronix Semiconductor Corporation
- Namit Varma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHARACTERIZATION OF SPATIAL CORRELATION IN INTEGRATED CIRCUIT DEVEL...
- Publication number 20200257769
- Publication date Aug 13, 2020
- International Business Machines Corporation
- Ning Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD OF OPERATING TIMING ANALYSIS CONSIDERING MULTI...
- Publication number 20200242206
- Publication date Jul 30, 2020
- Samsung Electronics Co., Ltd.
- MOON SU KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE ACCURACY INCREMENTAL TIMING ANALYSIS
- Publication number 20200242205
- Publication date Jul 30, 2020
- International Business Machines Corporation
- Jeffrey Hemmett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTRUCTION OF STAGING TREES ON FULLY HIERARCHICAL VLSI CIRCUIT DE...
- Publication number 20200210545
- Publication date Jul 2, 2020
- International Business Machines Corporation
- Sven Peyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVENT-TRIGGERED ANALYSIS FOR HIGH FIDELITY SIMULATION
- Publication number 20200175125
- Publication date Jun 4, 2020
- SAP SE
- Lars Erbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROPAGATING CONSTANTS OF STRUCTURED SOFT BLOCKS WHILE PRESERVING TH...
- Publication number 20200159882
- Publication date May 21, 2020
- International Business Machines Corporation
- Salim Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS OF FABRICATING SEMICONDUCTOR DEVICES, AND RELATED LAYOUT DE...
- Publication number 20200159884
- Publication date May 21, 2020
- Samsung Electronics Co., Ltd.
- Jae Hwan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for determining IC voltage and method for finding relation b...
- Publication number 20200151295
- Publication date May 14, 2020
- REALTEK SEMICONDUCTOR CORPORATION
- YING-CHIEH CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING SYSTEM AND TESTING METHOD
- Publication number 20200151299
- Publication date May 14, 2020
- Global Unichip (Nanjing) Ltd.
- Shih-Hsin Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR GENERATING AGING MODEL AND MANUFACTURING SEMICONDUCTOR C...
- Publication number 20200151294
- Publication date May 14, 2020
- Samsung Electronics Co., Ltd.
- Moon Su KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER-BAY PLACEMENT IN AN INTEGRATED CIRCUIT
- Publication number 20200117768
- Publication date Apr 16, 2020
- International Business Machines Corporation
- Jayaprakash Udhayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR TRANSACTION BASED PROPAGATED CLOCK-GATING...
- Publication number 20200117231
- Publication date Apr 16, 2020
- Huawei Technologies Co., Ltd
- Chang Hoon LEE
- G06 - COMPUTING CALCULATING COUNTING

Timing analysis and optimization

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Systems and methods for inter-die block level design

Slack time recycling

Modifying circuits based on timing reports for critical paths

Glitch detection at clock domain crossing

Automatic multi-clock circuit generation

Interactive incremental synthesis flow for integrated circuit design

Methods of manufacturing semiconductor devices by etching active fi...

Semiconductor process and performance sensor

Reducing clock power consumption of a computer processor

Constructing staging trees in hierarchical circuit designs

Verifying equivalence of design latency

Engineering change order aware global routing

Selection of corners and/or margins using statistical static timing...

Method, design program, and design apparatus of a high level synthe...

Circuit design analyzer

Formal clock network analysis, visualization, verification and gene...

Parasitic extraction based on compact representation of process cal...

Reducing clock power consumption of a computer processor

Die resistance-capacitance extraction and validation

Method and apparatus for utilizing estimations for register retimin...

Scalable connectivity verification using conditional cut-points

Selective conditional stall for hardware-based circuit design verif...

Physical synthesis within placement

Enabling automatic staging for nets or net groups with VHDL attributes

Method for layout design and structure with inter-layer vias

Timing-adaptive, configurable logic architecture

Pessimism reduction in cross-talk noise determination used in integ...

Circuit simulation using a recording of a reference execution

Modifying a circuit design

Phase algebra for virtual clock and mode extraction in hierarchical...

Patents Applicationslast 30 patents

EFFICIENT PROJECTION BASED ADJUSTMENT EVALUATION IN STATIC TIMING A...

MODULAR EVENT-BASED PERFORMANCE MONITORING IN INTEGRATED CIRCUIT DE...

CLOCK GATING LATCH PLACEMENT

OUT-OF-CONTEXT FEEDBACK HIERARCHICAL LARGE BLOCK SYNTHESIS (HLBS) O...

SINK-BASED WIRE TAGGING IN MULTI-SINK INTEGRATED CIRCUIT NET

SUPERCONDUCTING CIRCUIT WITH VIRTUAL TIMING ELEMENTS AND RELATED ME...

FEEDBACK-AWARE SLACK STEALING ACROSS TRANSPARENT LATCHES EMPOWERING...

DETERMINISTIC TEST PATTERN GENERATION FOR DESIGNS WITH TIMING EXCEP...

APPARATUS AND METHOD FOR CIRCUIT TIMING FIXING USING EXTENSION META...

HIERARCHICAL CLOCK TREE IMPLEMENTATION

HIERARCHICAL CLOCK TREE CONSTRUCTION BASED ON CONSTRAINTS

SELECTIVELY GROUNDING FILL WIRES

AUTOMATIC LAYER TRAIT GENERATION AND PROMOTION COST COMPUTATION

CHIP HEALTH MONITOR

SYSTEM AND METHOD FOR COMPACT NEURAL NETWORK MODELING OF TRANSISTORS

TIMING MODEL, TIMING MODEL BUILDING METHOD, AND RELATED TOP-LEVEL A...

MULTI-CYCLE LATCH TREE SYNTHESIS

EMBEDDED FPGA TIMING SIGN-OFF

CHARACTERIZATION OF SPATIAL CORRELATION IN INTEGRATED CIRCUIT DEVEL...

APPARATUS AND METHOD OF OPERATING TIMING ANALYSIS CONSIDERING MULTI...

VARIABLE ACCURACY INCREMENTAL TIMING ANALYSIS

CONSTRUCTION OF STAGING TREES ON FULLY HIERARCHICAL VLSI CIRCUIT DE...

EVENT-TRIGGERED ANALYSIS FOR HIGH FIDELITY SIMULATION

PROPAGATING CONSTANTS OF STRUCTURED SOFT BLOCKS WHILE PRESERVING TH...

METHODS OF FABRICATING SEMICONDUCTOR DEVICES, AND RELATED LAYOUT DE...

Method for determining IC voltage and method for finding relation b...

TESTING SYSTEM AND TESTING METHOD

METHOD FOR GENERATING AGING MODEL AND MANUFACTURING SEMICONDUCTOR C...

BUFFER-BAY PLACEMENT IN AN INTEGRATED CIRCUIT

METHOD AND APPARATUS FOR TRANSACTION BASED PROPAGATED CLOCK-GATING...