TLB miss handling

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CPC
G06F2212/684

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures

Current Industry

G06F2212/684TLB miss handling

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Patents Grantslast 30 patents

Information Patent Grant
Memory array page table walk
- Patent number 12,277,067
- Issue date Apr 15, 2025
- Perry V. Lea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic tuning of larger pages during runtime
- Patent number 12,147,352
- Issue date Nov 19, 2024
- International Business Machines Corporation
- Naijie Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for shared virtual memory to manage data coher...
- Patent number 12,147,346
- Issue date Nov 19, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Access log and address translation log for a processor
- Patent number 12,032,487
- Issue date Jul 9, 2024
- Advanced Micro Devices, Inc.
- Benjamin T. Sander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supporting secure memory intent
- Patent number 11,995,001
- Issue date May 28, 2024
- Intel Corporation
- Krystof C. Zmudzinski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling memory requests
- Patent number 11,941,430
- Issue date Mar 26, 2024
- Imagination Technologies Limited
- Mark Landers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for shared virtual memory to manage data coher...
- Patent number 11,921,635
- Issue date Mar 5, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tracking memory block access frequency in processor-based devices
- Patent number 11,868,269
- Issue date Jan 9, 2024
- Microsoft Technology Licensing, LLC
- Andrew Joseph Rushing
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supervisory memory management unit
- Patent number 11,775,443
- Issue date Oct 3, 2023
- Hewlett Packard Enterprise Development LP
- Derek Alan Sherlock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory array page table walk
- Patent number 11,663,137
- Issue date May 30, 2023
- Micron Technology, Inc.
- Perry V. Lea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling memory requests
- Patent number 11,537,427
- Issue date Dec 27, 2022
- Imagination Technologies Limited
- Mark Landers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Page table walker with page table entry (PTE) physical address pred...
- Patent number 11,494,300
- Issue date Nov 8, 2022
- Advanced Micro Devices, Inc.
- Gabriel H. Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and computer readable media for performing page f...
- Patent number 11,474,952
- Issue date Oct 18, 2022
- The Texas A&M University System
- Narasimha Reddy Annapareddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fine-grained access memory controller
- Patent number 11,467,973
- Issue date Oct 11, 2022
- Amazon Technologies, Inc.
- Ron Diamant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure using a logical directory
- Patent number 11,403,222
- Issue date Aug 2, 2022
- International Business Machines Corporation
- Christian Jacobi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supporting secure memory intent
- Patent number 11,392,507
- Issue date Jul 19, 2022
- Intel Corporation
- Krystof C. Zmudzinski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Active side-channel attack prevention
- Patent number 11,392,698
- Issue date Jul 19, 2022
- Intel Corporation
- Chaim Shen-Orr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for an efficient TLB lookup
- Patent number 11,372,776
- Issue date Jun 28, 2022
- International Business Machines Corporation
- Michael Johannes Jaspers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller and memory page management method
- Patent number 11,372,779
- Issue date Jun 28, 2022
- Industrial Technology Research Institute
- Che-Wei Tsao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tablewalk takeover
- Patent number 11,314,657
- Issue date Apr 26, 2022
- CENTAUR TECHNOLOGY, INC.
- Colin Eddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Access log and address translation log for a processor
- Patent number 11,288,205
- Issue date Mar 29, 2022
- Advanced Micro Devices, Inc.
- Benjamin T. Sander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning TLB or cache allocation
- Patent number 11,243,892
- Issue date Feb 8, 2022
- ARM Ltd.
- Steven Douglas Krueger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for setting a 2-level auto-close timer to access a memor...
- Patent number 11,216,386
- Issue date Jan 4, 2022
- Intel Corporation
- Vivek Kozhikkottu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory array page table walk
- Patent number 11,182,304
- Issue date Nov 23, 2021
- Micron Technology, Inc.
- Perry V. Lea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operation of a multi-slice processor implementing a unified page wa...
- Patent number 11,157,415
- Issue date Oct 26, 2021
- International Business Machines Corporation
- Dwain A. Hicks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heat-based load balancing
- Patent number 11,157,561
- Issue date Oct 26, 2021
- SCYLLA DB LTD.
- Nadav Har'El
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative address translation requests pertaining to instruction...
- Patent number 11,151,054
- Issue date Oct 19, 2021
- International Business Machines Corporation
- Naga P. Gorti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable skewed associativity in a translation lookaside buffer
- Patent number 11,106,596
- Issue date Aug 31, 2021
- Advanced Micro Devices, Inc.
- John M. King
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CPU-efficient cache replacment with two-phase eviction
- Patent number 11,080,189
- Issue date Aug 3, 2021
- VMware, Inc.
- Wenguang Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core computer systems with private/shared cache line indicators
- Patent number 11,068,410
- Issue date Jul 20, 2021
- ETA SCALE AB
- Alberto Ros
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...
- Publication number 20250061060
- Publication date Feb 20, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC TUNING OF LARGER PAGES DURING RUNTIME
- Publication number 20240232098
- Publication date Jul 11, 2024
- International Business Machines Corporation
- Naijie Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...
- Publication number 20240152457
- Publication date May 9, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC TUNING OF LARGER PAGES DURING RUNTIME
- Publication number 20240134805
- Publication date Apr 25, 2024
- International Business Machines Corporation
- Naijie Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHER WITH MULTI- LEVEL TLB...
- Publication number 20230418763
- Publication date Dec 28, 2023
- Benoy Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ARRAY PAGE TABLE WALK
- Publication number 20230401158
- Publication date Dec 14, 2023
- Micron Technology, Inc.
- Perry V. Lea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Handling Memory Requests
- Publication number 20230119485
- Publication date Apr 20, 2023
- Imagination Technologies Limited
- Mark Landers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACKING MEMORY BLOCK ACCESS FREQUENCY IN PROCESSOR-BASED DEVICES
- Publication number 20230107660
- Publication date Apr 6, 2023
- Microsoft Technology Licensing, LLC
- Andrew Joseph RUSHING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESS LOG AND ADDRESS TRANSLATION LOG FOR A PROCESSOR
- Publication number 20220269620
- Publication date Aug 25, 2022
- ADVANCED MICRO DEVICES, INC.
- Benjamin T. SANDER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAGE TABLE WALKER WITH PAGE TABLE ENTRY (PTE) PHYSICAL ADDRESS PRED...
- Publication number 20220100653
- Publication date Mar 31, 2022
- ADVANCED MICRO DEVICES, INC.
- Gabriel H. Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ARRAY PAGE TABLE WALK
- Publication number 20220075733
- Publication date Mar 10, 2022
- Micron Technology, Inc.
- Perry V. Lea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
JUST-IN-TIME SYNONYM HANDLING FOR A VIRTUALLY-TAGGED CACHE
- Publication number 20220004501
- Publication date Jan 6, 2022
- Ampere Computing LLC
- John Gregory Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINED OUT OF ORDER PAGE MISS HANDLER
- Publication number 20210406194
- Publication date Dec 30, 2021
- Intel Corporation
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR PERFORMING PAGE F...
- Publication number 20210374071
- Publication date Dec 2, 2021
- The Texas A&M University System
- Narasimha Reddy Annapareddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...
- Publication number 20210209025
- Publication date Jul 8, 2021
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Handling Memory Requests
- Publication number 20210132984
- Publication date May 6, 2021
- Imagination Technologies Limited
- Mark Landers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE USING A LOGICAL DIRECTORY
- Publication number 20210026771
- Publication date Jan 28, 2021
- International Business Machines Corporation
- Christian Jacobi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECULATIVE ADDRESS TRANSLATION REQUESTS PERTAINING TO INSTRUCTION...
- Publication number 20200409864
- Publication date Dec 31, 2020
- International Business Machines Corporation
- Naga P. GORTI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD ENABLING VIRTUAL PAGES TO BE ALLOCATED WITH NONCONTIGUOUS BA...
- Publication number 20200320016
- Publication date Oct 8, 2020
- ADVANCED MICRO DEVICES, INC.
- Alexander D. Breslow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CPU-EFFICIENT CACHE REPLACMENT WITH TWO-PHASE EVICTION
- Publication number 20200242034
- Publication date Jul 30, 2020
- VMware, Inc.
- Wenguang WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER AND MEMORY PAGE MANAGEMENT METHOD
- Publication number 20200201782
- Publication date Jun 25, 2020
- Industrial Technology Research Institute
- Che-Wei Tsao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSLATION LOOKASIDE BUFFER CACHE MARKER SCHEME FOR EMULATING SING...
- Publication number 20200192818
- Publication date Jun 18, 2020
- QUALCOMM Incorporated
- Vipul Gandhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-ENGINE ADDRESS TRANSLATION FACILITY
- Publication number 20200159670
- Publication date May 21, 2020
- International Business Machines Corporation
- Uwe BRANDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTITIONING TLB OR CACHE ALLOCATION
- Publication number 20200151111
- Publication date May 14, 2020
- ARM Limited
- Steven Douglas KRUEGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND C...
- Publication number 20200143275
- Publication date May 7, 2020
- KABUSHIKI KAISHA TOSHIBA
- Yusuke SHIROTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING A UNIFIED PAGE WA...
- Publication number 20200125496
- Publication date Apr 23, 2020
- International Business Machines Corporation
- DWAIN A. HICKS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR AN EFFICIENT TLB LOOKUP
- Publication number 20200110711
- Publication date Apr 9, 2020
- International Business Machines Corporation
- Michael Johannes Jaspers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...
- Publication number 20200089621
- Publication date Mar 19, 2020
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR REDUCING PIPELINE STALLS DUE TO A...
- Publication number 20200065260
- Publication date Feb 27, 2020
- QUALCOMM Incorporated
- Pritha GHOSHAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR SETTING A 2-LEVEL AUTO-CLOSE TIMER TO ACCESS A MEMOR...
- Publication number 20200019513
- Publication date Jan 16, 2020
- Intel Corporation
- Vivek KOZHIKKOTTU
- G06 - COMPUTING CALCULATING COUNTING

TLB miss handling

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Memory array page table walk

Dynamic tuning of larger pages during runtime

Method and apparatus for shared virtual memory to manage data coher...

Access log and address translation log for a processor

Supporting secure memory intent

Handling memory requests

Method and apparatus for shared virtual memory to manage data coher...

Tracking memory block access frequency in processor-based devices

Supervisory memory management unit

Memory array page table walk

Handling memory requests

Page table walker with page table entry (PTE) physical address pred...

Methods, systems, and computer readable media for performing page f...

Fine-grained access memory controller

Cache structure using a logical directory

Supporting secure memory intent

Active side-channel attack prevention

Method and apparatus for an efficient TLB lookup

Memory controller and memory page management method

Tablewalk takeover

Access log and address translation log for a processor

Partitioning TLB or cache allocation

Techniques for setting a 2-level auto-close timer to access a memor...

Memory array page table walk

Operation of a multi-slice processor implementing a unified page wa...

Heat-based load balancing

Speculative address translation requests pertaining to instruction...

Configurable skewed associativity in a translation lookaside buffer

CPU-efficient cache replacment with two-phase eviction

Multi-core computer systems with private/shared cache line indicators

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...

DYNAMIC TUNING OF LARGER PAGES DURING RUNTIME

METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...

DYNAMIC TUNING OF LARGER PAGES DURING RUNTIME

TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHER WITH MULTI- LEVEL TLB...

MEMORY ARRAY PAGE TABLE WALK

Handling Memory Requests

TRACKING MEMORY BLOCK ACCESS FREQUENCY IN PROCESSOR-BASED DEVICES

ACCESS LOG AND ADDRESS TRANSLATION LOG FOR A PROCESSOR

PAGE TABLE WALKER WITH PAGE TABLE ENTRY (PTE) PHYSICAL ADDRESS PRED...

MEMORY ARRAY PAGE TABLE WALK

JUST-IN-TIME SYNONYM HANDLING FOR A VIRTUALLY-TAGGED CACHE

PIPELINED OUT OF ORDER PAGE MISS HANDLER

METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR PERFORMING PAGE F...

METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...

Handling Memory Requests

CACHE STRUCTURE USING A LOGICAL DIRECTORY

SPECULATIVE ADDRESS TRANSLATION REQUESTS PERTAINING TO INSTRUCTION...

METHOD ENABLING VIRTUAL PAGES TO BE ALLOCATED WITH NONCONTIGUOUS BA...

CPU-EFFICIENT CACHE REPLACMENT WITH TWO-PHASE EVICTION

MEMORY CONTROLLER AND MEMORY PAGE MANAGEMENT METHOD

TRANSLATION LOOKASIDE BUFFER CACHE MARKER SCHEME FOR EMULATING SING...

MULTI-ENGINE ADDRESS TRANSLATION FACILITY

PARTITIONING TLB OR CACHE ALLOCATION

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND C...

OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING A UNIFIED PAGE WA...

METHOD AND APPARATUS FOR AN EFFICIENT TLB LOOKUP

METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...

METHOD, APPARATUS, AND SYSTEM FOR REDUCING PIPELINE STALLS DUE TO A...

TECHNIQUES FOR SETTING A 2-LEVEL AUTO-CLOSE TIMER TO ACCESS A MEMOR...