to perform miscellaneous control operations

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CPC
G06F9/30076

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

Current Industry

G06F9/30076to perform miscellaneous control operations

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Comparing hash values computed at function entry and exit for incre...
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- International Business Machines Corporation
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- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accessing a parametric field within a specialized context
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- Issue date Nov 12, 2024
- Oracle International Corporation
- John Robert Rose
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Information Patent Grant
Convolutional neural network operation grouping based on memory uni...
- Patent number 12,131,182
- Issue date Oct 29, 2024
- NANJING HORIZON ROBOTICS TECHNOLOGY CO., LTD.
- Zhenjiang Wang
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Information Patent Grant
Core processor and redundant branch processor with control flow att...
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- Issue date Oct 8, 2024
- Ceremorphic, Inc.
- Lizy Kurian John
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Information Patent Grant
User timer directly programmed by application
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- Rajesh Sankaran
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Information Patent Grant
Processor having multiple cores, shared core extension logic, and s...
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- Issue date Sep 10, 2024
- Intel Corporation
- Eran Shifer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor, processing method, and related device for accelerating g...
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- Issue date Sep 10, 2024
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- Xiping Zhou
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Information Patent Grant
PC-based instruction group permissions
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Information Patent Grant
Streaming engine with fetch ahead hysteresis
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Information Patent Grant
Compiler device, instruction generation method, program, compiling...
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Information Patent Grant
Methods, apparatus, and instructions for user-level thread suspension
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Information Patent Grant
Method and system for on demand control of hardware support for sof...
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Information Patent Grant
Implicit program order
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Information Patent Grant
Determining different resolution states for a parametric constant i...
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Information Patent Grant
Apparatuses, methods, and systems for instructions to request a his...
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Information Patent Grant
Implementing a type restriction that restricts to a singleton value...
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- Issue date Apr 23, 2024
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Information Patent Grant
Conditional execution specification of instructions using condition...
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- Issue date Apr 16, 2024
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Information Patent Grant
Low-latency register error correction
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Information Patent Grant
Job modification to present a user interface based on a user interf...
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- Adobe Inc.
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- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Advancing a program counter to a start of a subsequent cache line b...
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Information Patent Grant
Method performed by a microcontroller for managing a NOP instructio...
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- Issue date Mar 5, 2024
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- Giulio Martinozzi
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Information Patent Grant
Accessing a parametric field within a specialized context
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Information Patent Grant
Apparatuses, methods, and systems for hardware control of processor...
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- Eliezer Weissmann
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Information Patent Grant
Similarity scores of rules in information technology workflows
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Information Patent Grant
Systolic multiply delayed accumulate processor architecture
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- Thomas Elmer
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Information Patent Grant
Arithmetic processing device and semiconductor device with improved...
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- Yuhei Takata
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Information Patent Grant
Data object delivery for distributed cluster computing
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Information Patent Grant
Implementing a type restriction that restricts to a maximum or spec...
- Patent number 11,836,552
- Issue date Dec 5, 2023
- Oracle International Corporation
- John Robert Rose
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Information Patent Grant
Hardware security hardening for processor devices
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- Issue date Nov 7, 2023
- Advanced Micro Devices, Inc.
- Harry J. Wise
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Information Patent Grant
Instantiating a parametric class within a specialized context
- Patent number 11,789,793
- Issue date Oct 17, 2023
- Oracle International Corporation
- John Robert Rose
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS
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ACCELERATOR INCLUDING HIERARCHICAL MEMORY
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APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HIS...
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APPARATUSES, METHODS, AND SYSTEMS FOR HARDWARE CONTROL OF PROCESSOR...
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CONDITIONAL EXECUTION SPECIFICATION OF INSTRUCTIONS USING CONDITION...
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Information Patent Application
Job Modification To Present A User Interface Based On A User Interf...
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UNKNOWN OBJECT SUB-CLASS IDENTIFICATION
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INSTRUCTION AND LOGIC FOR TRACKING FETCH PERFORMANCE BOTTLENECKS
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- Ahmad Yasin
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Control Transfer Termination Instructions Of An Instruction Set Arc...
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MECHANISM TO HANDLE BREAKPOINTS IN A MULTI-ELEMENT PROCESSOR
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- Micron Technology, Inc.
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Information Patent Application
Accessing A Parametric Field Within A Specialized Context
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- Publication date Feb 22, 2024
- ORACLE INTERNATIONAL CORPORATION
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METHODS FOR CONTROLLING APPLICATION INSTANCE TO BE ONLINE OR OFFLIN...
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- BOE TECHNOLOGY GROUP CO., LTD.
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PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A P...
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- Publication date Dec 21, 2023
- HYPERION CORE, INC.
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Information Patent Application
SYSTEMS AND METHODS FOR COMPUTING DOT PRODUCTS OF NIBBLES IN TWO TI...
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- Intel Corporation
- Raanan Sade
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Information Patent Application
METHOD AND APPARATUS FOR GENERATING CONTROL INSTRUCTION
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- Suzhou Touchair Technology Co., Ltd
- Guangsong Liu
- G06 - COMPUTING CALCULATING COUNTING
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FUSING NO-OP (NOP) INSTRUCTIONS
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- ADVANCED MICRO DEVICES, INC.
- Kai Troester
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APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HIS...
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- Intel Corporation
- ELIEZER WEISSMANN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPH COMPUTING APPARATUS, PROCESSING METHOD, AND RELATED DEVICE
- Publication number 20230195526
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- Huawei Technologies Co., Ltd
- Ruoyu ZHOU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD PERFORMED BY A MICROCONTROLLER FOR MANAGING A NOP INSTRUCTIO...
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- SK HYNIX INC.
- Giulio MARTINOZZI
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METHOD OF IMPLEMENTING AN ARM64-BIT FLOATING POINT EMULATOR ON A LI...
- Publication number 20230176869
- Publication date Jun 8, 2023
- Airoha Technology (Suzhou) Limited
- Fei YAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPILER DEVICE, INSTRUCTION GENERATION METHOD, PROGRAM, COMPILING...
- Publication number 20230131430
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- Preferred Networks, Inc.
- Shogo MURAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXECUTING MULTIPLE PROGRAMS SIMULTANEOUSLY ON A PROCESSOR CORE
- Publication number 20230106990
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- Microsoft Technology Licensing, LLC
- Gagan Gupta
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Information Patent Application
Core Processor and Redundant Branch Processor with Control Flow Att...
- Publication number 20230098640
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Information Patent Application
LOW-LATENCY REGISTER ERROR CORRECTION
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- Publication date Mar 30, 2023
- Micron Technology, Inc.
- Dean E. Walker
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Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HIS...
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- Intel Corporation
- ELIEZER WEISSMANN
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PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...
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- Intel Corporation
- Eran SHIFER
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Data Object Delivery for Distributed Cluster Computing
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- Publication date Jan 5, 2023
- Citrix Systems, Inc
- Zhuzhang Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONDITIONAL EXECUTION SPECIFICATION OF INSTRUCTIONS USING CONDITION...
- Publication number 20220357952
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- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY-IMPOSED FIELD AND METHOD TYPE RESTRICTIONS FOR MANAGED...
- Publication number 20220300263
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- ORACLE INTERNATIONAL CORPORATION
- Daniel Lee Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER-BASED MATRIX MULTIPLICATION
- Publication number 20220291923
- Publication date Sep 15, 2022
- ARM Limited
- David Hennah MANSELL
- G06 - COMPUTING CALCULATING COUNTING

to perform miscellaneous control operations

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Comparing hash values computed at function entry and exit for incre...

Accessing a parametric field within a specialized context

Convolutional neural network operation grouping based on memory uni...

Core processor and redundant branch processor with control flow att...

User timer directly programmed by application

Processor having multiple cores, shared core extension logic, and s...

Processor, processing method, and related device for accelerating g...

PC-based instruction group permissions

Streaming engine with fetch ahead hysteresis

Compiler device, instruction generation method, program, compiling...

Methods, apparatus, and instructions for user-level thread suspension

Method and system for on demand control of hardware support for sof...

Implicit program order

Determining different resolution states for a parametric constant i...

Apparatuses, methods, and systems for instructions to request a his...

Implementing a type restriction that restricts to a singleton value...

Conditional execution specification of instructions using condition...

Low-latency register error correction

Job modification to present a user interface based on a user interf...

Advancing a program counter to a start of a subsequent cache line b...

Method performed by a microcontroller for managing a NOP instructio...

Accessing a parametric field within a specialized context

Apparatuses, methods, and systems for hardware control of processor...

Similarity scores of rules in information technology workflows

Systolic multiply delayed accumulate processor architecture

Arithmetic processing device and semiconductor device with improved...

Data object delivery for distributed cluster computing

Implementing a type restriction that restricts to a maximum or spec...

Hardware security hardening for processor devices

Instantiating a parametric class within a specialized context

Patents Applicationslast 30 patents

CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS

ACCELERATOR INCLUDING HIERARCHICAL MEMORY

APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HIS...

APPARATUSES, METHODS, AND SYSTEMS FOR HARDWARE CONTROL OF PROCESSOR...

CONDITIONAL EXECUTION SPECIFICATION OF INSTRUCTIONS USING CONDITION...

Job Modification To Present A User Interface Based On A User Interf...

UNKNOWN OBJECT SUB-CLASS IDENTIFICATION

INSTRUCTION AND LOGIC FOR TRACKING FETCH PERFORMANCE BOTTLENECKS

Control Transfer Termination Instructions Of An Instruction Set Arc...

MECHANISM TO HANDLE BREAKPOINTS IN A MULTI-ELEMENT PROCESSOR

Accessing A Parametric Field Within A Specialized Context

METHODS FOR CONTROLLING APPLICATION INSTANCE TO BE ONLINE OR OFFLIN...

PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A P...

SYSTEMS AND METHODS FOR COMPUTING DOT PRODUCTS OF NIBBLES IN TWO TI...

METHOD AND APPARATUS FOR GENERATING CONTROL INSTRUCTION

FUSING NO-OP (NOP) INSTRUCTIONS

APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HIS...

GRAPH COMPUTING APPARATUS, PROCESSING METHOD, AND RELATED DEVICE

METHOD PERFORMED BY A MICROCONTROLLER FOR MANAGING A NOP INSTRUCTIO...

METHOD OF IMPLEMENTING AN ARM64-BIT FLOATING POINT EMULATOR ON A LI...

COMPILER DEVICE, INSTRUCTION GENERATION METHOD, PROGRAM, COMPILING...

EXECUTING MULTIPLE PROGRAMS SIMULTANEOUSLY ON A PROCESSOR CORE

Core Processor and Redundant Branch Processor with Control Flow Att...

LOW-LATENCY REGISTER ERROR CORRECTION

APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HIS...

PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...

Data Object Delivery for Distributed Cluster Computing

CONDITIONAL EXECUTION SPECIFICATION OF INSTRUCTIONS USING CONDITION...

DYNAMICALLY-IMPOSED FIELD AND METHOD TYPE RESTRICTIONS FOR MANAGED...

REGISTER-BASED MATRIX MULTIPLICATION