using a cache

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G06F15/8069

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F15/00Digital computers in general Data processing equipment in general

Current Industry

G06F15/8069using a cache

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalar core integration
- Patent number 12,117,962
- Issue date Oct 15, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip memory system for a reconfigurable parallel processor
- Patent number 12,093,214
- Issue date Sep 17, 2024
- AzurEngine Technologies, Inc.
- Ryan Braidwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 12,072,814
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,007,907
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache that supports draining write-miss entries
- Patent number 12,001,345
- Issue date Jun 4, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable parallel processing
- Patent number 11,971,847
- Issue date Apr 30, 2024
- XDL Technologies Inc.
- Yuan Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce read-modify-write cycles for non-al...
- Patent number 11,940,929
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 11,940,930
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
No-locality hint vector memory access processors, methods, systems,...
- Patent number 11,892,952
- Issue date Feb 6, 2024
- Intel Corporation
- Christopher J Hughes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 11,886,353
- Issue date Jan 30, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 11,868,272
- Issue date Jan 9, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
General-purpose systolic array
- Patent number 11,829,321
- Issue date Nov 28, 2023
- Google LLC
- Reginald Clifford Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 11,803,486
- Issue date Oct 31, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic compare and swap in cach...
- Patent number 11,775,446
- Issue date Oct 3, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different tags
- Patent number 11,762,780
- Issue date Sep 19, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalar core integration
- Patent number 11,762,804
- Issue date Sep 19, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate fully pipelined read-modify-wri...
- Patent number 11,741,020
- Issue date Aug 29, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 11,714,760
- Issue date Aug 1, 2023
- Texas Instmments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate write miss caching in cache system
- Patent number 11,693,790
- Issue date Jul 4, 2023
- Texas Instmments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache that supports draining write-miss entries
- Patent number 11,693,791
- Issue date Jul 4, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 11,640,357
- Issue date May 2, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for inflight data forwarding and invalidation...
- Patent number 11,636,040
- Issue date Apr 25, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESS REQUEST DYNAMIC MULTILEVEL ARBITRATION
- Publication number 20240272905
- Publication date Aug 15, 2024
- Akeana, Inc.
- Sanjay Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reconfigurable Parallel Processing
- Publication number 20240264975
- Publication date Aug 8, 2024
- XDL Technologies Inc.
- Yuan Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20240264952
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...
- Publication number 20240232100
- Publication date Jul 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE
- Publication number 20240193098
- Publication date Jun 13, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-CHIP MEMORY SYSTEM FOR A RECONFIGURABLE PARALLEL PROCESSOR
- Publication number 20240160601
- Publication date May 16, 2024
- AzurEngine Technologies Zhuhai Inc.
- Ryan Braidwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20240143516
- Publication date May 2, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20240104026
- Publication date Mar 28, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
General-Purpose Systolic Array
- Publication number 20240078212
- Publication date Mar 7, 2024
- Google LLC
- Reginald Clifford Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS
- Publication number 20240078190
- Publication date Mar 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALAR CORE INTEGRATION
- Publication number 20240045830
- Publication date Feb 8, 2024
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20240028523
- Publication date Jan 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20240020242
- Publication date Jan 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE MERGING ON STORES WITH DIFFERENT TAGS
- Publication number 20240004800
- Publication date Jan 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20230401162
- Publication date Dec 14, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20230342305
- Publication date Oct 26, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE WRITE MISS CACHING IN CACHE SYSTEM
- Publication number 20230333991
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
General-Purpose Systolic Array
- Publication number 20230325347
- Publication date Oct 12, 2023
- Google LLC
- Reginald Clifford Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20230281126
- Publication date Sep 7, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20230236974
- Publication date Jul 27, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20230108306
- Publication date Apr 6, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NO-LOCALITY HINT VECTOR MEMORY ACCESS PROCESSORS, METHODS, SYSTEMS,...
- Publication number 20230052652
- Publication date Feb 16, 2023
- Intel Corporation
- Christopher J. Hughes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20230032348
- Publication date Feb 2, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALAR CORE INTEGRATION
- Publication number 20230029176
- Publication date Jan 26, 2023
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING

using a cache

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Aggressive write flush scheme for a victim cache

Methods and apparatus to reduce bank pressure using aggressive writ...

Fully pipelined read-modify-write support

Methods and apparatus for allocation in a victim cache system

Methods and apparatus for read-modify-write support in multi-banked...

Victim cache with dynamic allocation of entries

Atomic operations and histogram operations in a cache pipeline

Scalar core integration

Methods and apparatus for eviction in dual datapath victim cache sy...

On-chip memory system for a reconfigurable parallel processor

Methods and apparatus to facilitate read-modify-write support in a...

Victim cache with write miss merging

Victim cache that supports draining write-miss entries

Reconfigurable parallel processing

Methods and apparatus to reduce read-modify-write cycles for non-al...

Methods and apparatus to facilitate atomic operations in victim cache

No-locality hint vector memory access processors, methods, systems,...

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus for allocation in a victim cache system

General-purpose systolic array

Write merging on stores with different privilege levels

Methods and apparatus to facilitate atomic compare and swap in cach...

Write merging on stores with different tags

Scalar core integration

Methods and apparatus to facilitate fully pipelined read-modify-wri...

Methods and apparatus to reduce bank pressure using aggressive writ...

Methods and apparatus to facilitate write miss caching in cache system

Victim cache that supports draining write-miss entries

Methods and apparatus to facilitate read-modify-write support in a...

Methods and apparatus for inflight data forwarding and invalidation...

Patents Applicationslast 30 patents

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

VICTIM CACHE WITH WRITE MISS MERGING

ACCESS REQUEST DYNAMIC MULTILEVEL ARBITRATION

Reconfigurable Parallel Processing

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...

METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE

ON-CHIP MEMORY SYSTEM FOR A RECONFIGURABLE PARALLEL PROCESSOR

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

General-Purpose Systolic Array

WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS

SCALAR CORE INTEGRATION

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

WRITE MERGING ON STORES WITH DIFFERENT TAGS

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

METHODS AND APPARATUS TO FACILITATE WRITE MISS CACHING IN CACHE SYSTEM

General-Purpose Systolic Array

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

NO-LOCALITY HINT VECTOR MEMORY ACCESS PROCESSORS, METHODS, SYSTEMS,...

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

SCALAR CORE INTEGRATION