using carry completion detection, either over all stages or at sample stages only

Industry

CPC
G06F7/5052

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F7/5052using carry completion detection, either over all stages or at sample stages only

Industries

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Patents Grantslast 30 patents

Information Patent Grant
In-memory bit-serial addition system
- Patent number 12,118,328
- Issue date Oct 15, 2024
- Purdue Research Foundation
- Mustafa Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-memory bit-serial addition system
- Patent number 11,669,302
- Issue date Jun 6, 2023
- Purdue Research Foundation
- Mustafa Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calculating unit and method for subtracting
- Patent number 6,970,899
- Issue date Nov 29, 2005
- Infineon Technologies AG
- Astrid Elbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calculating unit and method for adding
- Patent number 6,965,910
- Issue date Nov 15, 2005
- Infineon Technologies AG
- Astrid Elbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention threshold gate
- Patent number 6,900,658
- Issue date May 31, 2005
- Theseus Logic Inc.
- Gerald E. Sobelman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder circuit, integrating circuit which uses the adder circuit, an...
- Patent number 6,647,405
- Issue date Nov 11, 2003
- Fujitsu Limited
- Koichi Kuroiwa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder circuit
- Patent number 6,438,571
- Issue date Aug 20, 2002
- NEC Corporation
- Michio Shimada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encryption processor with shared memory interconnect
- Patent number 6,434,699
- Issue date Aug 13, 2002
- MOSAID Technologies Inc.
- David E. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous completion prediction
- Patent number 6,369,614
- Issue date Apr 9, 2002
- Sun Microsystems, Inc.
- Stuart Alexander Ridgway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous logic with intermediate value between data and null va...
- Patent number 6,333,640
- Issue date Dec 25, 2001
- Theseus Logic, Inc.
- Karl M. Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic circuit and method for designing the same
- Patent number 6,101,621
- Issue date Aug 8, 2000
- Kabushiki Kaisha Toshiba
- Yoshihisa Kondo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encryption processor with shared memory interconnect
- Patent number 6,088,800
- Issue date Jul 11, 2000
- Mosaid Technologies, Incorporated
- David E. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous register
- Patent number 6,052,770
- Issue date Apr 18, 2000
- Theseus Logic, Inc.
- Karl Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look up table threshold gates
- Patent number 6,020,754
- Issue date Feb 1, 2000
- Theseus Logic, Inc.
- Gerald Edward Sobelman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention register file
- Patent number 5,896,541
- Issue date Apr 20, 1999
- Theseus Logic, Inc.
- Karl M. Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention logic system
- Patent number 5,828,228
- Issue date Oct 27, 1998
- Theseus Logic, Inc.
- Karl M. Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention bus
- Patent number 5,796,962
- Issue date Aug 18, 1998
- Theeus Logic
- Karl M. Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention adder
- Patent number 5,793,662
- Issue date Aug 11, 1998
- Theseus Research, Inc.
- David A. Duncan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous processors
- Patent number 5,752,070
- Issue date May 12, 1998
- California Institute of Technology
- A. J. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention threshold gate
- Patent number 5,664,211
- Issue date Sep 2, 1997
- Theseus Research, Inc.
- Gerald Sobelman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
NULL convention logic system
- Patent number 5,664,212
- Issue date Sep 2, 1997
- Theseus Research, Inc.
- Karl M. Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention threshold gate
- Patent number 5,656,948
- Issue date Aug 12, 1997
- Theseus Research, Inc.
- Gerald E. Sobelman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous register for null convention logic systems
- Patent number 5,652,902
- Issue date Jul 29, 1997
- Theseus Research, Inc.
- Karl Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Current mode null convention threshold gate
- Patent number 5,640,105
- Issue date Jun 17, 1997
- Theseus Research, Inc.
- Gerald E. Sobelman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention logic system
- Patent number 5,305,463
- Issue date Apr 19, 1994
- Theseus Research
- Karl M. Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder control method and adder control circuit
- Patent number 5,065,353
- Issue date Nov 12, 1991
- Hitachi, Ltd.
- Tohru Nojiri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ALU with carry length detection
- Patent number 4,623,981
- Issue date Nov 18, 1986
- Digital Equipment Corporation
- Gilbert Wolrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous adder circuit
- Patent number 4,338,676
- Issue date Jul 6, 1982
- Bell Telephone Laboratories, Incorporated
- Bruce E. Briley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary parallel computing arrangement for additions or subtractions
- Patent number 3,947,671
- Issue date Mar 30, 1976
- International Business Machines Corporation
- Hellmuth Roland Geng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3535695
- Patent number 3,535,695
- Issue date Oct 20, 1970
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
IN-MEMORY BIT-SERIAL ADDITION SYSTEM
- Publication number 20230305804
- Publication date Sep 28, 2023
- Purdue Research Foundation
- Mustafa Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-MEMORY BIT-SERIAL ADDITION SYSTEM
- Publication number 20210117156
- Publication date Apr 22, 2021
- Purdue Research Foundation
- Mustafa Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Calculating unit and method for subtracting
- Publication number 20050097156
- Publication date May 5, 2005
- Infineon Technologies AG
- Astrid Elbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Calculating unit and method for adding
- Publication number 20050097157
- Publication date May 5, 2005
- Infineon Technologies AG
- Astrid Elbe
- G06 - COMPUTING CALCULATING COUNTING

using carry completion detection, either over all stages or at sample stages only

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

In-memory bit-serial addition system

In-memory bit-serial addition system

Calculating unit and method for subtracting

Calculating unit and method for adding

Null convention threshold gate

Adder circuit, integrating circuit which uses the adder circuit, an...

Adder circuit

Encryption processor with shared memory interconnect

Asynchronous completion prediction

Asynchronous logic with intermediate value between data and null va...

Logic circuit and method for designing the same

Encryption processor with shared memory interconnect

Asynchronous register

Look up table threshold gates

Null convention register file

Null convention logic system

Null convention bus

Null convention adder

Asynchronous processors

Null convention threshold gate

NULL convention logic system

Null convention threshold gate

Asynchronous register for null convention logic systems

Current mode null convention threshold gate

Null convention logic system

Adder control method and adder control circuit

ALU with carry length detection

Asynchronous adder circuit

Binary parallel computing arrangement for additions or subtractions

3535695

Patents Applicationslast 30 patents

IN-MEMORY BIT-SERIAL ADDITION SYSTEM

IN-MEMORY BIT-SERIAL ADDITION SYSTEM

Calculating unit and method for subtracting

Calculating unit and method for adding