using instruction pipelines

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CPC
G06F9/3867

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

Current Industry

G06F9/3867using instruction pipelines

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Patents Grantslast 30 patents

Information Patent Grant
Analytics, algorithm architecture, and data processing system and m...
- Patent number 12,271,636
- Issue date Apr 8, 2025
- Robert Bismuth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache size change
- Patent number 12,271,314
- Issue date Apr 8, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Re-triggering wake-up to handle time skew between scalar and vector...
- Patent number 12,265,829
- Issue date Apr 1, 2025
- SiFive, Inc.
- Kuan Lin Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying compressed stream fused with copy or transform operations
- Patent number 12,242,851
- Issue date Mar 4, 2025
- Intel Corporation
- Vinodh Gopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data initialization techniques
- Patent number 12,242,414
- Issue date Mar 4, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two address translations from a single table look-aside buffer read
- Patent number 12,235,773
- Issue date Feb 25, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for deep learning network execution pipeline...
- Patent number 12,229,569
- Issue date Feb 18, 2025
- Intel Corporation
- Liu Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method of optimizing divergent processing in thread g...
- Patent number 12,223,325
- Issue date Feb 11, 2025
- ARM Limited
- Daren Croxford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CPUs with capture queues to save and restore intermediate results a...
- Patent number 12,223,327
- Issue date Feb 11, 2025
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tenancy data analytics platform
- Patent number 12,210,532
- Issue date Jan 28, 2025
- Fidelity Information Services, LLC
- Aaron David Colcord
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing instructions in a microprocessor
- Patent number 12,210,908
- Issue date Jan 28, 2025
- International Business Machines Corporation
- Brian W. Thompto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybridized storage optimization for genomic workloads
- Patent number 12,210,904
- Issue date Jan 28, 2025
- International Business Machines Corporation
- Sasikanth Eda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inserting predefined pad values into a stream of vectors
- Patent number 12,204,905
- Issue date Jan 21, 2025
- Texas Instruments Incorporated
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache support for indirect loads and indirect stores in graph appli...
- Patent number 12,204,901
- Issue date Jan 21, 2025
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic designation of instructions as sensitive for constraining i...
- Patent number 12,204,904
- Issue date Jan 21, 2025
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence signaling protocol
- Patent number 12,197,331
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Continuous integration emulator
- Patent number 12,190,138
- Issue date Jan 7, 2025
- SAP SE
- Anurag Negi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing call and return information due to a branch prediction e...
- Patent number 12,190,115
- Issue date Jan 7, 2025
- Fujitsu Limited
- Chunye You
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tracking streaming engine vector predicates to control processor ex...
- Patent number 12,164,438
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Duc Quang Bui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor that executes instruction that specifies instruction conc...
- Patent number 12,153,929
- Issue date Nov 26, 2024
- Texas Instruments Incorporated
- Horst Diewald
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic thread count optimizations
- Patent number 12,147,814
- Issue date Nov 19, 2024
- Microsoft Technology Licensing, LLC
- Thomas James Ootjers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelized scrubbing transactions
- Patent number 12,147,301
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- David Matthew Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global coherence operations
- Patent number 12,141,601
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence shared state suppression
- Patent number 12,135,646
- Issue date Nov 5, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital messages in a load control system
- Patent number 12,127,317
- Issue date Oct 22, 2024
- Lutron Technology Company LLC
- Brian Michael Courtney
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250117356
- Publication date Apr 10, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENTERING PROTECTED PIPELINE MODE WITHOUT ANNULLING PENDING INSTRUCT...
- Publication number 20250117247
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Duc BUI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODEL TRAINING METHODS AND APPARATUS
- Publication number 20250111226
- Publication date Apr 3, 2025
- Beijing Volcano Engine Technology Co., Ltd.
- Han QIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH TARGET BUFFER VICTIM CACHE
- Publication number 20250110743
- Publication date Apr 3, 2025
- Microsoft Technology Licensing, LLC
- Julio Gago Alonso
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20250103546
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EX...
- Publication number 20250103510
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Duc Quang Bui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250103547
- Publication date Mar 27, 2025
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSOLIDATION AND SHARING OF PIPELINES ACROSS PROJECTS IN A COMPUTI...
- Publication number 20250068428
- Publication date Feb 27, 2025
- VMware, Inc.
- ADITI SRINIVAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESOURCE BALANCING FOR WORKLOAD MANAGEMENT IN NETWORKED SYSTEMS
- Publication number 20250060969
- Publication date Feb 20, 2025
- Wells Fargo Bank, N.A.
- Mark Jonathan Austin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital Messages in a Load Control System
- Publication number 20250048521
- Publication date Feb 6, 2025
- Lutron Technology Company
- Brian Michael Courtney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PADDING IN A STREAM OF MATRIX ELEMENTS
- Publication number 20250036411
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Son Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLELIZED SCRUBBING TRANSACTIONS
- Publication number 20250036522
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- David Matthew THOMPSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AVOIDING THE USE OF A RESULT CROSSBAR WHEN DOWN CONVERTING TO PACKE...
- Publication number 20250036412
- Publication date Jan 30, 2025
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
- Publication number 20250028675
- Publication date Jan 23, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBAL COHERENCE OPERATIONS
- Publication number 20250028551
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR INTER-PIPELINE DATA HAZARD AVOIDANCE
- Publication number 20250021340
- Publication date Jan 16, 2025
- Imagination Technologies Limited
- Luca Iuliano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE SHARED STATE SUPPRESSION
- Publication number 20250013569
- Publication date Jan 9, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING
- Publication number 20250013518
- Publication date Jan 9, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING INTEGRATION OF NEW DATA FOR DATA PIPELINES
- Publication number 20250004908
- Publication date Jan 2, 2025
- Dell Products L.P.
- OFIR EZRIELEV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTITIONING FOR AN EXECUTION PIPELINE
- Publication number 20250005455
- Publication date Jan 2, 2025
- Microsoft Technology Licensing, LLC
- Ryota TOMIOKA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250004981
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CURATING ANOMALOUS DATA FOR USE IN A DATA PIPELINE THROUGH INTERACT...
- Publication number 20250004783
- Publication date Jan 2, 2025
- Dell Products L.P.
- OFIR EZRIELEV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR VECTOR PERMUTATION
- Publication number 20240419606
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT
- Publication number 20240411703
- Publication date Dec 12, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE LATENCY INSTRUCTIONS
- Publication number 20240411559
- Publication date Dec 12, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. ANDERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION TECHNIQUES
- Publication number 20240403259
- Publication date Dec 5, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS
- Publication number 20240403055
- Publication date Dec 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Network Device with Programmable Action Processing
- Publication number 20240394060
- Publication date Nov 28, 2024
- MELLANOX TECHNOLOGIES, LTD.
- Ariel Shahar
- G06 - COMPUTING CALCULATING COUNTING

using instruction pipelines

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Analytics, algorithm architecture, and data processing system and m...

Cache size change

Re-triggering wake-up to handle time skew between scalar and vector...

Verifying compressed stream fused with copy or transform operations

Data initialization techniques

Two address translations from a single table look-aside buffer read

Methods and apparatus for deep learning network execution pipeline...

Apparatus and method of optimizing divergent processing in thread g...

CPUs with capture queues to save and restore intermediate results a...

Systems and methods for improving cache efficiency and utilization

Multi-tenancy data analytics platform

Routing instructions in a microprocessor

Hybridized storage optimization for genomic workloads

Inserting predefined pad values into a stream of vectors

Graphics processor data access and sharing

Cache support for indirect loads and indirect stores in graph appli...

Dynamic designation of instructions as sensitive for constraining i...

Hardware coherence signaling protocol

Continuous integration emulator

Processing call and return information due to a branch prediction e...

Multi-tile memory management

Tracking streaming engine vector predicates to control processor ex...

Processor that executes instruction that specifies instruction conc...

Cache structure and utilization

Dynamic thread count optimizations

Parallelized scrubbing transactions

Global coherence operations

Systolic disaggregation within a matrix accelerator architecture

Cache coherence shared state suppression

Digital messages in a load control system

Patents Applicationslast 30 patents

MULTI-TILE MEMORY MANAGEMENT

ENTERING PROTECTED PIPELINE MODE WITHOUT ANNULLING PENDING INSTRUCT...

MODEL TRAINING METHODS AND APPARATUS

BRANCH TARGET BUFFER VICTIM CACHE

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

CACHE STRUCTURE AND UTILIZATION

TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EX...

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

CONSOLIDATION AND SHARING OF PIPELINES ACROSS PROJECTS IN A COMPUTI...

RESOURCE BALANCING FOR WORKLOAD MANAGEMENT IN NETWORKED SYSTEMS

Digital Messages in a Load Control System

PADDING IN A STREAM OF MATRIX ELEMENTS

PARALLELIZED SCRUBBING TRANSACTIONS

AVOIDING THE USE OF A RESULT CROSSBAR WHEN DOWN CONVERTING TO PACKE...

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

GLOBAL COHERENCE OPERATIONS

METHODS AND SYSTEMS FOR INTER-PIPELINE DATA HAZARD AVOIDANCE

CACHE COHERENCE SHARED STATE SUPPRESSION

STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING

MANAGING INTEGRATION OF NEW DATA FOR DATA PIPELINES

PARTITIONING FOR AN EXECUTION PIPELINE

MULTI-TILE MEMORY MANAGEMENT

CURATING ANOMALOUS DATA FOR USE IN A DATA PIPELINE THROUGH INTERACT...

METHOD AND APPARATUS FOR VECTOR PERMUTATION

PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT

CACHE STRUCTURE AND UTILIZATION

VARIABLE LATENCY INSTRUCTIONS

COMPRESSION TECHNIQUES

DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS

Network Device with Programmable Action Processing