with reset of the frequency divider or the counter

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H03L7/199

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HELECTRICITY H03Electronic circuits H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES H03L7/00Automatic control of frequency or phase Synchronisation

Current Industry

H03L7/199with reset of the frequency divider or the counter

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Generating divided signals from phase-locked loop (PLL) output when...
- Patent number 12,149,255
- Issue date Nov 19, 2024
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Raja Prabhu J
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock synchronization in a network using a distributed pulse signal
- Patent number 11,967,964
- Issue date Apr 23, 2024
- Amazon Technologies, Inc.
- Noam Katz
- G11 - INFORMATION STORAGE
Information Patent Grant
Generating divided signals from phase-locked loop (PLL) output when...
- Patent number 11,967,965
- Issue date Apr 23, 2024
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Raja Prabhu J
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pulse signal generation circuit and method, and memory
- Patent number 11,671,106
- Issue date Jun 6, 2023
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Enpeng Gao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital sampling techniques
- Patent number 11,569,824
- Issue date Jan 31, 2023
- ARM Limited
- Shidhartha Das
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for fractional synchronization using direct d...
- Patent number 11,538,511
- Issue date Dec 27, 2022
- Ciena Corporation
- Soheyl Ziabakhsh Shalmani
- G11 - INFORMATION STORAGE
Information Patent Grant
Hitless switching by resetting multi-modulus feedback divider
- Patent number 11,108,400
- Issue date Aug 31, 2021
- RENESAS ELECTRONICS AMERICA INC.
- Greg Armstrong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock data recovery circuit and apparatus including the same
- Patent number 10,924,119
- Issue date Feb 16, 2021
- Samsung Electronics Co., Ltd.
- Geumyoung Tak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-locked loop circuit for high bit-rate and low consumption tra...
- Patent number 10,879,909
- Issue date Dec 29, 2020
- FONDAZIONE ISTITUTO ITALIANO DI TECNOLOGIA
- Marco Crepaldi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-chip timing alignment to a common reference signal
- Patent number 10,496,127
- Issue date Dec 3, 2019
- Linear Technology Holding LLC
- Michael Dean Womac
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Video processing device
- Patent number 10,462,335
- Issue date Oct 29, 2019
- Fujitsu Ten Limited
- Yasuhiro Fukuda
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital phase locked loop circuit adjusting digital gain to maintai...
- Patent number 10,193,562
- Issue date Jan 29, 2019
- Samsung Electronics Co., Ltd.
- Kangyeop Choo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adjusting the magnitude of a capacitance of a digitally controlled...
- Patent number 9,954,486
- Issue date Apr 24, 2018
- International Business Machines Corporation
- Herschel A. Ainspan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adjusting the magnitude of a capacitance of a digitally controlled...
- Patent number 9,837,959
- Issue date Dec 5, 2017
- International Business Machines Corporation
- Herschel A. Ainspan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for synchronizing phase-locked loops
- Patent number 9,503,109
- Issue date Nov 22, 2016
- Analog Devices Global
- David J McLaurin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-locked loop device with synchronization means
- Patent number 9,024,666
- Issue date May 5, 2015
- Fabrice Jovenin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for adjusting phases of clock signals
- Patent number 8,860,475
- Issue date Oct 14, 2014
- Altera Corporation
- Tze Yi Yeoh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLL dual edge lock detector
- Patent number 8,749,283
- Issue date Jun 10, 2014
- Marvell World Trade Ltd.
- Xiaoyue Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High jitter and frequency drift tolerant clock data recovery
- Patent number 8,681,918
- Issue date Mar 25, 2014
- STMicroelectronics International N.V.
- Nitin Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
PLL dual edge lock detector
- Patent number 8,624,642
- Issue date Jan 7, 2014
- Marvell World Trade Ltd.
- Xiaoyue Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLL dual edge lock detector
- Patent number 8,519,756
- Issue date Aug 27, 2013
- Marvell World Trade Ltd.
- Xiaoyue Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High jitter and frequency drift tolerant clock data recovery
- Patent number 8,411,811
- Issue date Apr 2, 2013
- STMicroelectronics Pvt. Ltd.
- Nitin Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for multi-point calibration for synthesizing v...
- Patent number 8,362,843
- Issue date Jan 29, 2013
- QUALCOMM Incorporated
- Brian Kaczynski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLL frequency synthesizer
- Patent number 8,138,842
- Issue date Mar 20, 2012
- Fujitsu Limited
- Masafumi Kondou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Calibration techniques for frequency synthesizers
- Patent number 8,019,301
- Issue date Sep 13, 2011
- QUALCOMM Incorporated
- Jeremy D. Dunworth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock data recovery circuitry associated with programmable logic de...
- Patent number 7,684,532
- Issue date Mar 23, 2010
- Altera Corporation
- Edward Aung
- G11 - INFORMATION STORAGE
Information Patent Grant
Calibration techniques for frequency synthesizers
- Patent number 7,546,097
- Issue date Jun 9, 2009
- QUALCOMM Incorporated
- Jeremy D. Dunworth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Edge alignment for frequency synthesizers
- Patent number 7,532,077
- Issue date May 12, 2009
- ZeroG Wireless, Inc.
- Stanley Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for tuning a frequency generator using an LC osci...
- Patent number 7,512,390
- Issue date Mar 31, 2009
- GCT Semiconductor, Inc.
- Kang Yoon Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low phase noise phase locked loops with minimum lock time
- Patent number 7,486,147
- Issue date Feb 3, 2009
- Broadcom Corporation
- Shahla Khorram
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
GENERATING DIVIDED SIGNALS FROM PHASE-LOCKED LOOP (PLL) OUTPUT WHEN...
- Publication number 20240154617
- Publication date May 9, 2024
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Raja Prabhu J
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONTROL OF SKEW BETWEEN MULTIPLE DATA LANES
- Publication number 20240039545
- Publication date Feb 1, 2024
- STMicroelectronics International N.V.
- Rupesh Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
GENERATING DIVIDED SIGNALS FROM PHASE-LOCKED LOOP (PLL) OUTPUT WHEN...
- Publication number 20230136353
- Publication date May 4, 2023
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Raja Prabhu J
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL SAMPLING TECHNIQUES
- Publication number 20220399895
- Publication date Dec 15, 2022
- ARM Limited
- Shidhartha Das
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and Methods for Fractional Synchronization Using Direct D...
- Publication number 20220254394
- Publication date Aug 11, 2022
- CIENA CORPORATION
- Soheyl Ziabakhsh Shalmani
- G11 - INFORMATION STORAGE
Information Patent Application
PULSE SIGNAL GENERATION CIRCUIT AND METHOD, AND MEMORY
- Publication number 20220158645
- Publication date May 19, 2022
- CHANGXIN MEMORY TECHNOLOGIES, INC
- Enpeng GAO
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK AND DATA RECOVERY CIRCUIT, MEMORY STORAGE DEVICE AND FLASH ME...
- Publication number 20200252072
- Publication date Aug 6, 2020
- PHISON ELECTRONICS CORP.
- Jen-Chu Wu
- G11 - INFORMATION STORAGE
Information Patent Application
A Phase-Locked Loop Circuit for High Bit-Rate and Low Consumption T...
- Publication number 20200106449
- Publication date Apr 2, 2020
- Fondazione Istituto Italiano Di Tecnologia
- Marco Crepaldi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTI-CHIP TIMING ALIGNMENT TO A COMMON REFERENCE SIGNAL
- Publication number 20190369657
- Publication date Dec 5, 2019
- Linear Technology Holding LLC
- Michael Dean WOMAC
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL PHASE LOCKED LOOP CIRCUIT ADJUSTING DIGITAL GAIN TO MAINTAI...
- Publication number 20180367154
- Publication date Dec 20, 2018
- Samsung Electronics Co., Ltd.
- Kangyeop CHOO
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
VIDEO PROCESSING DEVICE
- Publication number 20180063385
- Publication date Mar 1, 2018
- FUJITSU TEN LIMITED
- Yasuhiro FUKUDA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PROGRAMMABLE FREQUENCY DIVIDER, PLL SYNTHESIZER AND RADAR DEVICE
- Publication number 20170366193
- Publication date Dec 21, 2017
- Fujitsu Limited
- Hiroshi Matsumura
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHODS FOR SYNCHRONIZING PHASE-LOCKED LOOPS
- Publication number 20150263742
- Publication date Sep 17, 2015
- ANALOG DEVICES GLOBAL
- David J. McLaurin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHASE-LOCKED LOOP DEVICE WITH SYNCHRONIZATION MEANS
- Publication number 20140361817
- Publication date Dec 11, 2014
- ASAHI KASEI MICRODEVICES CORPORATION
- Fabrice Jovenin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLL DUAL EDGE LOCK DETECTOR
- Publication number 20140097879
- Publication date Apr 10, 2014
- Marvell World Trade Ltd.
- Xiaoyue Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLL DUAL EDGE LOCK DETECTOR
- Publication number 20130307596
- Publication date Nov 21, 2013
- Marvell World Trade Ltd.
- Xiaoyue Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH JITTER AND FREQUENCY DRIFT TOLERANT CLOCK DATA RECOVERY
- Publication number 20130181754
- Publication date Jul 18, 2013
- STMicroelectronics Pvt. Ltd.
- Nitin GUPTA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR MULTI-POINT CALIBRATION FOR SYNTHESIZING V...
- Publication number 20120154064
- Publication date Jun 21, 2012
- Brian KACZYNSKI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLL DUAL EDGE LOCK DETECTOR
- Publication number 20120098570
- Publication date Apr 26, 2012
- Xiaoyue Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH JITTER AND FREQUENCY DRIFT TOLERANT CLOCK DATA RECOVERY
- Publication number 20110273215
- Publication date Nov 10, 2011
- STMICROELECTRONICS PVT. LTD.
- Nitin Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PLL FREQUENCY SYNTHESIZER
- Publication number 20100007425
- Publication date Jan 14, 2010
- FUJITSU LIMITED
- Masafumi KONDOU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Edge alignment for frequency synthesizers
- Publication number 20080278243
- Publication date Nov 13, 2008
- ZeroG Wireless, Inc. Delaware Corporation
- Stanley Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Wireless communication semiconductor integrated circuit device and...
- Publication number 20080278245
- Publication date Nov 13, 2008
- Toshiya Uozumi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CALIBRATION TECHNIQUES FOR FREQUENCY SYNTHESIZERS
- Publication number 20080248771
- Publication date Oct 9, 2008
- QUALCOMM Incorporated
- Jeremy D. Dunworth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low phase noise phase locked loops with minimum lock time
- Publication number 20080136535
- Publication date Jun 12, 2008
- BROADCOM CORPORATION
- Shahla Khorram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase-locked loop circuit
- Publication number 20080063131
- Publication date Mar 13, 2008
- NEC Electronics Corporation
- Manabu Furuta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLL circuit
- Publication number 20080036513
- Publication date Feb 14, 2008
- FUJITSU LIMITED
- Yoshito Koyama
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock data recovery circuitry associated with programmable logic de...
- Publication number 20080031385
- Publication date Feb 7, 2008
- Altera Corporation
- Edward Aung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PHASE- OR FREQUENCY-LOCKED LOOP CIRCUIT HAVING A GLITCH DETECTOR FO...
- Publication number 20070120584
- Publication date May 31, 2007
- International Business Machines Corporation
- Paul S. Carlile
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Wireless communication system
- Publication number 20070087716
- Publication date Apr 19, 2007
- Masumi Kasahara
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

with reset of the frequency divider or the counter

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Generating divided signals from phase-locked loop (PLL) output when...

Clock synchronization in a network using a distributed pulse signal

Generating divided signals from phase-locked loop (PLL) output when...

Pulse signal generation circuit and method, and memory

Digital sampling techniques

Apparatus and methods for fractional synchronization using direct d...

Hitless switching by resetting multi-modulus feedback divider

Clock data recovery circuit and apparatus including the same

Phase-locked loop circuit for high bit-rate and low consumption tra...

Multi-chip timing alignment to a common reference signal

Video processing device

Digital phase locked loop circuit adjusting digital gain to maintai...

Adjusting the magnitude of a capacitance of a digitally controlled...

Adjusting the magnitude of a capacitance of a digitally controlled...

Apparatus and methods for synchronizing phase-locked loops

Phase-locked loop device with synchronization means

Techniques for adjusting phases of clock signals

PLL dual edge lock detector

High jitter and frequency drift tolerant clock data recovery

PLL dual edge lock detector

PLL dual edge lock detector

High jitter and frequency drift tolerant clock data recovery

Method and apparatus for multi-point calibration for synthesizing v...

PLL frequency synthesizer

Calibration techniques for frequency synthesizers

Clock data recovery circuitry associated with programmable logic de...

Calibration techniques for frequency synthesizers

Edge alignment for frequency synthesizers

System and method for tuning a frequency generator using an LC osci...

Low phase noise phase locked loops with minimum lock time

Patents Applicationslast 30 patents

GENERATING DIVIDED SIGNALS FROM PHASE-LOCKED LOOP (PLL) OUTPUT WHEN...

CONTROL OF SKEW BETWEEN MULTIPLE DATA LANES

GENERATING DIVIDED SIGNALS FROM PHASE-LOCKED LOOP (PLL) OUTPUT WHEN...

DIGITAL SAMPLING TECHNIQUES

Apparatus and Methods for Fractional Synchronization Using Direct D...

PULSE SIGNAL GENERATION CIRCUIT AND METHOD, AND MEMORY

CLOCK AND DATA RECOVERY CIRCUIT, MEMORY STORAGE DEVICE AND FLASH ME...

A Phase-Locked Loop Circuit for High Bit-Rate and Low Consumption T...

MULTI-CHIP TIMING ALIGNMENT TO A COMMON REFERENCE SIGNAL

DIGITAL PHASE LOCKED LOOP CIRCUIT ADJUSTING DIGITAL GAIN TO MAINTAI...

VIDEO PROCESSING DEVICE

PROGRAMMABLE FREQUENCY DIVIDER, PLL SYNTHESIZER AND RADAR DEVICE

APPARATUS AND METHODS FOR SYNCHRONIZING PHASE-LOCKED LOOPS

PHASE-LOCKED LOOP DEVICE WITH SYNCHRONIZATION MEANS

PLL DUAL EDGE LOCK DETECTOR

PLL DUAL EDGE LOCK DETECTOR

HIGH JITTER AND FREQUENCY DRIFT TOLERANT CLOCK DATA RECOVERY

METHOD AND APPARATUS FOR MULTI-POINT CALIBRATION FOR SYNTHESIZING V...

PLL DUAL EDGE LOCK DETECTOR

HIGH JITTER AND FREQUENCY DRIFT TOLERANT CLOCK DATA RECOVERY

PLL FREQUENCY SYNTHESIZER

Edge alignment for frequency synthesizers

Wireless communication semiconductor integrated circuit device and...

CALIBRATION TECHNIQUES FOR FREQUENCY SYNTHESIZERS

Low phase noise phase locked loops with minimum lock time

Phase-locked loop circuit

PLL circuit

Clock data recovery circuitry associated with programmable logic de...

PHASE- OR FREQUENCY-LOCKED LOOP CIRCUIT HAVING A GLITCH DETECTOR FO...

Wireless communication system