with simultaneous carry generation for, or propagation over, two or more stages

Industry

CPC
G06F7/506

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F7/506with simultaneous carry generation for, or propagation over, two or more stages

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Compaction of multiplier and adder circuits
- Patent number 11,768,663
- Issue date Sep 26, 2023
- Xilinx, Inc.
- Srijan Tiwary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder circuitry for very large integers
- Patent number 11,662,979
- Issue date May 30, 2023
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-memory full adder
- Patent number 11,604,850
- Issue date Mar 14, 2023
- GSI Technology Inc.
- LeeLean Shu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefix network-directed addition
- Patent number 11,334,318
- Issue date May 17, 2022
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel-prefix adder and method
- Patent number 11,010,133
- Issue date May 18, 2021
- Marvell Asia Pte, Ltd.
- Ranjan B. Lokappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA logic cell with improved support for counters
- Patent number 10,936,286
- Issue date Mar 2, 2021
- MICROSEMI SOC CORP.
- Jonathan W. Greene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder circuitry for very large integers
- Patent number 10,873,332
- Issue date Dec 22, 2020
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic logic unit for single-cycle fusion operations
- Patent number 10,768,897
- Issue date Sep 8, 2020
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High spurious-free dynamic-range line driver
- Patent number 10,715,147
- Issue date Jul 14, 2020
- Analog Devices International Unlimited Company
- Jose Tejada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel-prefix adder and method
- Patent number 10,705,797
- Issue date Jul 7, 2020
- Marvell International Ltd.
- Ranjan B. Lokappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic logic unit for single-cycle fusion operations
- Patent number 10,545,727
- Issue date Jan 28, 2020
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Energy-efficient variable power adder and methods of use thereof
- Patent number 10,223,071
- Issue date Mar 5, 2019
- QUALCOMM Incorporated
- Hari Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, method and program for calculating the result of a repea...
- Patent number 9,933,999
- Issue date Apr 3, 2018
- ARM Limited
- Andreas Due Engh-Halstvedt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single-pass parallel prefix scan with dynamic look back
- Patent number 9,928,033
- Issue date Mar 27, 2018
- NVIDIA Corporation
- Duane Merrill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel self-timed adder (PASTA)
- Patent number 9,928,211
- Issue date Mar 27, 2018
- Mohammed Ziaur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for vector processing
- Patent number 9,916,130
- Issue date Mar 13, 2018
- ARM Limited
- David Raymond Lutz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Exponent monitoring
- Patent number 9,886,239
- Issue date Feb 6, 2018
- ARM Limited
- Guy Larri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for performing conversion operation
- Patent number 9,778,906
- Issue date Oct 3, 2017
- ARM Limited
- David Raymond Lutz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Vector operands with component representing different significance...
- Patent number 9,766,858
- Issue date Sep 19, 2017
- ARM Limited
- David Raymond Lutz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data processing apparatus and method using programmable significanc...
- Patent number 9,766,857
- Issue date Sep 19, 2017
- ARM Limited
- David Raymond Lutz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Exception generation when generating a result value with programmab...
- Patent number 9,703,529
- Issue date Jul 11, 2017
- ARM Limited
- David Raymond Lutz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Significance alignment
- Patent number 9,690,543
- Issue date Jun 27, 2017
- ARM Limited
- David Raymond Lutz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for performing conversion operation
- Patent number 9,665,347
- Issue date May 30, 2017
- ARM Limited
- David Raymond Lutz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Arithmetic circuit and arithmetic method
- Patent number 9,632,751
- Issue date Apr 25, 2017
- Kabushiki Kaisha Toshiba
- Koichiro Ban
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable IC's with large carry chains
- Patent number 9,489,175
- Issue date Nov 8, 2016
- Altera Corporation
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Three-term predictive adder and/or subtracter
- Patent number 9,448,767
- Issue date Sep 20, 2016
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing apparatus and method for performing a narrowing-and...
- Patent number 9,262,123
- Issue date Feb 16, 2016
- ARM Limited
- Neil Burgess
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a fast 3x multiplicand term for radix-8 booth multiplica...
- Patent number 9,146,707
- Issue date Sep 29, 2015
- International Business Machines Corporation
- Deepak K. Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable IC's with large carry chains
- Patent number 8,797,062
- Issue date Aug 5, 2014
- Tabula, Inc.
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Three-term predictive adder and/or subtracter
- Patent number 8,713,086
- Issue date Apr 29, 2014
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HIGH SPEED RIPPLE ADDER
- Publication number 20240256222
- Publication date Aug 1, 2024
- Sehat Sutardja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIGNUM ADDITION AND/OR SUBTRACTION WITH CARRY PROPAGATION
- Publication number 20240111489
- Publication date Apr 4, 2024
- Onur Kayiran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LARGE INTEGER MULTIPLICATION ENHANCEMENTS FOR GRAPHICS ENVIRONMENT
- Publication number 20220413848
- Publication date Dec 29, 2022
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEW LOW POWER ADDER TREE STRUCTURE
- Publication number 20220253282
- Publication date Aug 11, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chia-Fu Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDER CIRCUITRY FOR VERY LARGE INTEGERS
- Publication number 20210075425
- Publication date Mar 11, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL-PREFIX ADDER AND METHOD
- Publication number 20200334014
- Publication date Oct 22, 2020
- GLOBALFOUNDRIES INC.
- Ranjan B. Lokappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL-PREFIX ADDER AND METHOD
- Publication number 20200167127
- Publication date May 28, 2020
- GLOBALFOUNDRIES INC.
- Ranjan B. Lokappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FPGA LOGIC CELL WITH IMPROVED SUPPORT FOR COUNTERS
- Publication number 20200150925
- Publication date May 14, 2020
- Microsemi SoC Corp.
- Jonathan W. Greene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-DESTRUCTIVE MEMORY ARRAY TO IMPLEMENT A FULL ADDER
- Publication number 20200151236
- Publication date May 14, 2020
- GSI Technology Inc.
- LeeLean SHU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARITHMETIC LOGIC UNIT FOR SINGLE-CYCLE FUSION OPERATIONS
- Publication number 20200019376
- Publication date Jan 16, 2020
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARITHMETIC LOGIC UNIT FOR SINGLE-CYCLE FUSION OPERATIONS
- Publication number 20190212984
- Publication date Jul 11, 2019
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable IC's With Large Carry Chains
- Publication number 20150137851
- Publication date May 21, 2015
- Tabula, Inc.
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE-PASS PARALLEL PREFIX SCAN WITH DYNAMIC LOOK BACK
- Publication number 20140380317
- Publication date Dec 25, 2014
- NVIDIA Corporation
- Duane MERRILL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATING A FAST 3x MULTIPLAND TERM FOR RADIX-8 BOOTH MULTIPLICATION
- Publication number 20140358979
- Publication date Dec 4, 2014
- Deepak K. Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARITHMETIC CIRCUIT AND ARITHMETIC METHOD
- Publication number 20140181170
- Publication date Jun 26, 2014
- Kabushiki Kaisha Toshiba
- Koichiro BAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Three-Term Predictive Adder and/or Subtracter
- Publication number 20140181165
- Publication date Jun 26, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE WITH LOGIC CIRCUITRY SUPPORTING QUATERNARY ADDITION
- Publication number 20130311534
- Publication date Nov 21, 2013
- Altera Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL SELF-TIMER ADDER (PASTA)
- Publication number 20130117345
- Publication date May 9, 2013
- UNIVERSITY OF MALAYA
- Mohammed Ziaur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE IC'S WITH LARGE CARRY CHAINS
- Publication number 20130038347
- Publication date Feb 14, 2013
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE-TERM PREDICTIVE ADDER AND/OR SUBTRACTER
- Publication number 20130013656
- Publication date Jan 10, 2013
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID ADDER USING DYNAMIC AND STATIC CIRCUITS
- Publication number 20120311009
- Publication date Dec 6, 2012
- Ben D. Jarrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Use with Automated Circuit Design and Simulations
- Publication number 20120066279
- Publication date Mar 15, 2012
- Ken S. McElvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOOK UP TABLE STRUCTURE SUPPORTING QUATERNARY ADDERS
- Publication number 20110238718
- Publication date Sep 29, 2011
- Altera Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Sum of Address Compare Write Recode and C...
- Publication number 20110228580
- Publication date Sep 22, 2011
- QUALCOMM Incorporated
- Timothy Edward Ozimek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF USING COMMON ADDER CIRCUITRY FOR BOTH A HORIZO...
- Publication number 20110099214
- Publication date Apr 28, 2011
- VIA Technologies, Inc.
- Rochelle L. Stortz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE IC'S WITH LARGE CARRY CHAINS
- Publication number 20110031998
- Publication date Feb 10, 2011
- Jason Redgrave
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address Generation Unit with Pseudo Sum to Accelerate Load/Store Op...
- Publication number 20110022824
- Publication date Jan 27, 2011
- Rajat Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE CARRY SCHEME FOR FIELD PROGRAMMABLE GATE ARRAYS
- Publication number 20100100864
- Publication date Apr 22, 2010
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACROCELL AND METHOD FOR ADDING
- Publication number 20100026341
- Publication date Feb 4, 2010
- INFINEON TECHNOLOGIES AG
- Thomas Kuenemund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC I...
- Publication number 20090289660
- Publication date Nov 26, 2009
- Tony Ngai
- G06 - COMPUTING CALCULATING COUNTING

with simultaneous carry generation for, or propagation over, two or more stages

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Compaction of multiplier and adder circuits

Adder circuitry for very large integers

In-memory full adder

Prefix network-directed addition

Parallel-prefix adder and method

FPGA logic cell with improved support for counters

Adder circuitry for very large integers

Arithmetic logic unit for single-cycle fusion operations

High spurious-free dynamic-range line driver

Parallel-prefix adder and method

Arithmetic logic unit for single-cycle fusion operations

Energy-efficient variable power adder and methods of use thereof

Apparatus, method and program for calculating the result of a repea...

Single-pass parallel prefix scan with dynamic look back

Parallel self-timed adder (PASTA)

Apparatus and method for vector processing

Exponent monitoring

Apparatus and method for performing conversion operation

Vector operands with component representing different significance...

Data processing apparatus and method using programmable significanc...

Exception generation when generating a result value with programmab...

Significance alignment

Apparatus and method for performing conversion operation

Arithmetic circuit and arithmetic method

Configurable IC's with large carry chains

Three-term predictive adder and/or subtracter

Data processing apparatus and method for performing a narrowing-and...

Generating a fast 3x multiplicand term for radix-8 booth multiplica...

Configurable IC's with large carry chains

Three-term predictive adder and/or subtracter

Patents Applicationslast 30 patents

HIGH SPEED RIPPLE ADDER

BIGNUM ADDITION AND/OR SUBTRACTION WITH CARRY PROPAGATION

LARGE INTEGER MULTIPLICATION ENHANCEMENTS FOR GRAPHICS ENVIRONMENT

NEW LOW POWER ADDER TREE STRUCTURE

ADDER CIRCUITRY FOR VERY LARGE INTEGERS

PARALLEL-PREFIX ADDER AND METHOD

PARALLEL-PREFIX ADDER AND METHOD

FPGA LOGIC CELL WITH IMPROVED SUPPORT FOR COUNTERS

NON-DESTRUCTIVE MEMORY ARRAY TO IMPLEMENT A FULL ADDER

ARITHMETIC LOGIC UNIT FOR SINGLE-CYCLE FUSION OPERATIONS

ARITHMETIC LOGIC UNIT FOR SINGLE-CYCLE FUSION OPERATIONS

Configurable IC's With Large Carry Chains

SINGLE-PASS PARALLEL PREFIX SCAN WITH DYNAMIC LOOK BACK

GENERATING A FAST 3x MULTIPLAND TERM FOR RADIX-8 BOOTH MULTIPLICATION

ARITHMETIC CIRCUIT AND ARITHMETIC METHOD

Three-Term Predictive Adder and/or Subtracter

DEVICE WITH LOGIC CIRCUITRY SUPPORTING QUATERNARY ADDITION

PARALLEL SELF-TIMER ADDER (PASTA)

CONFIGURABLE IC'S WITH LARGE CARRY CHAINS

THREE-TERM PREDICTIVE ADDER AND/OR SUBTRACTER

HYBRID ADDER USING DYNAMIC AND STATIC CIRCUITS

Techniques for Use with Automated Circuit Design and Simulations

LOOK UP TABLE STRUCTURE SUPPORTING QUATERNARY ADDERS

Methods and Apparatus for Sum of Address Compare Write Recode and C...

SYSTEM AND METHOD OF USING COMMON ADDER CIRCUITRY FOR BOTH A HORIZO...

CONFIGURABLE IC'S WITH LARGE CARRY CHAINS

Address Generation Unit with Pseudo Sum to Accelerate Load/Store Op...

FLEXIBLE CARRY SCHEME FOR FIELD PROGRAMMABLE GATE ARRAYS

MACROCELL AND METHOD FOR ADDING

INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC I...