Write with the simultaneous writing of a plurality of cells

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G11C2013/0088Write with the simultaneous writing of a plurality of cells

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Patents Grantslast 30 patents

Information Patent Grant
Distinct chip identifier sequence utilizing unclonable characterist...
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- Issue date Apr 23, 2024
- Crossbar, Inc.
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Information Patent Grant
2T-1R architecture for resistive ram
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- Issue date Feb 20, 2024
- Hefei Reliance Memory Limited
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Information Patent Grant
2T-1R architecture for resistive RAM
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- Issue date Jan 31, 2023
- Hefei Reliance Memory Limited
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Information Patent Grant
Distinct chip identifier sequence utilizing unclonable characterist...
- Patent number 11,450,384
- Issue date Sep 20, 2022
- Crossbar, Inc.
- Sung Hyun Jo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Distinct chip identifier sequence utilizing unclonable characterist...
- Patent number 11,437,100
- Issue date Sep 6, 2022
- Crossbar, Inc.
- Sung Hyun Jo
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Information Patent Grant
Distinct chip identifier sequence utilizing unclonable characterist...
- Patent number 11,430,517
- Issue date Aug 30, 2022
- Crossbar, Inc.
- Sung Hyun Jo
- G11 - INFORMATION STORAGE
Information Patent Grant
Distinct chip identifier sequence utilizing unclonable characterist...
- Patent number 11,430,516
- Issue date Aug 30, 2022
- Crossbar, Inc.
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- G11 - INFORMATION STORAGE
Information Patent Grant
Distinct chip identifier sequence utilizing unclonable characterist...
- Patent number 11,423,984
- Issue date Aug 23, 2022
- Crossbar, Inc.
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Information Patent Grant
System and method for performing memory operations in RRAM cells
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- Issue date Jun 28, 2022
- Hefei Reliance Memory Limited
- Brent Steven Haukness
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Synapse memory cell driver
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- Issue date May 3, 2022
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Memory devices and memory operational methods
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Information Patent Grant
1T-1R architecture for resistive random access memory
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- Issue date Oct 19, 2021
- Hefei Reliance Memory Limited
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Information Patent Grant
2T-1R architecture for resistive RAM
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- Issue date Aug 3, 2021
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Information Patent Grant
Data state synchronization
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Neural network circuit
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Memory circuit and formation method thereof
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Information Patent Grant
Memory circuit and formation method thereof
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- Issue date Dec 29, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Chun-Yang Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Accessing memory cells in parallel in a cross-point array
- Patent number 10,854,287
- Issue date Dec 1, 2020
- Micron Technology, Inc.
- Hernan A. Castro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
1T-1R architecture for resistive random access memory
- Patent number 10,783,964
- Issue date Sep 22, 2020
- Hefei Reliance Memory Limited
- Deepak Chandra Sekar
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive memory device and resistive memory system including a plu...
- Patent number 10,741,245
- Issue date Aug 11, 2020
- Samsung Electronics Co., Ltd.
- Eun-chu Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for performing memory operations in RRAM cells
- Patent number 10,714,173
- Issue date Jul 14, 2020
- Hefei Reliance Memory Limited
- Brent Steven Haukness
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2T-1R architecture for resistive ram
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- Issue date Apr 14, 2020
- Hefei Reliance Memory Limited
- Deepak Chandra Sekar
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Information Patent Grant
Memory systems and memory writing methods
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- Issue date Apr 14, 2020
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- Wataru Otsuka
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Information Patent Grant
Data state synchronization
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- Issue date Feb 25, 2020
- Micron Technology, Inc.
- Marco Dallabora
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Information Patent Grant
Memory circuit having concurrent writes and method therefor
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- Issue date Feb 11, 2020
- NXP USA, INC.
- Perry H. Pelley
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Information Patent Grant
RRAM array with current limiting element
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- Issue date Dec 17, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chia-Fu Lee
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Memory circuit and formation method thereof
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- Issue date Oct 29, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chun-Yang Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory devices and methods of writing memory cells at different mom...
- Patent number 10,438,661
- Issue date Oct 8, 2019
- Micron Technology, Inc.
- Wataru Otsuka
- G11 - INFORMATION STORAGE
Information Patent Grant
1T-1R architecture for resistive random access memory
- Patent number 10,388,372
- Issue date Aug 20, 2019
- Hefei Reliance Memory Limited
- Deepak Chandra Sekar
- G11 - INFORMATION STORAGE
Information Patent Grant
Accessing memory cells in parallel in a cross-point array
- Patent number 10,360,975
- Issue date Jul 23, 2019
- Micron Technology, Inc.
- Hernan A. Castro
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
2T-1R ARCHITECTURE FOR RESISTIVE RAM
- Publication number 20230154531
- Publication date May 18, 2023
- Hefei Reliance Memory Limited
- Deepak Chandra SEKAR
- G11 - INFORMATION STORAGE
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DISTINCT CHIP IDENTIFIER SEQUENCE UTILIZING UNCLONABLE CHARACTERIST...
- Publication number 20230005538
- Publication date Jan 5, 2023
- CROSSBAR, INC.
- Sung Hyun Jo
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DISTINCT CHIP IDENTIFIER SEQUENCE UTILIZING UNCLONABLE CHARACTERIST...
- Publication number 20210314177
- Publication date Oct 7, 2021
- Crossbar, Inc.
- Sung Hyun Jo
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2T-1R ARCHITECTURE FOR RESISTIVE RAM
- Publication number 20210295913
- Publication date Sep 23, 2021
- Hefei Reliance Memory Limited
- Deepak Chandra SEKAR
- G11 - INFORMATION STORAGE
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SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS IN RRAM CELLS
- Publication number 20200294589
- Publication date Sep 17, 2020
- Hefei Reliance Memory Limited
- Brent Steven HAUKNESS
- G11 - INFORMATION STORAGE
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2T-1R ARCHITECTURE FOR RESISTIVE RAM
- Publication number 20200211644
- Publication date Jul 2, 2020
- Hefei Reliance Memory Limited
- Deepak Chandra SEKAR
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DATA STATE SYNCHRONIZATION
- Publication number 20200152267
- Publication date May 14, 2020
- Micron Technology, Inc.
- Marco Dallabora
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MEMORY CIRCUIT AND FORMATION METHOD THEREOF
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- Publication date Jan 23, 2020
- Taiwan Semiconductor Manufacturing Co., LTD
- Chun-Yang Tsai
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1T-1R ARCHITECTURE FOR RESISTIVE RANDOM ACCESS MEMORY
- Publication number 20190355414
- Publication date Nov 21, 2019
- Hefei Reliance Memory Limited
- Deepak Chandra SEKAR
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ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY
- Publication number 20190341102
- Publication date Nov 7, 2019
- Micron Technology, Inc.
- Hernan A. Castro
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Memory Devices and Memory Operational Methods
- Publication number 20190318782
- Publication date Oct 17, 2019
- Micron Technology, Inc.
- Wataru Otsuka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS IN RRAM CELLS
- Publication number 20190172533
- Publication date Jun 6, 2019
- Hefei Reliance Memory Limited
- Brent Steven HAUKNESS
- G11 - INFORMATION STORAGE
Information Patent Application
2T-1R ARCHITECTURE FOR RESISTIVE RAM
- Publication number 20190156886
- Publication date May 23, 2019
- Hefei Reliance Memory Limited
- Deepak Chandra SEKAR
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RRAM ARRAY WITH CURRENT LIMITING ELEMENT
- Publication number 20190139604
- Publication date May 9, 2019
- Taiwan Semiconductor Manufacturing Co., LTD
- Chia-Fu Lee
- G11 - INFORMATION STORAGE
Information Patent Application
RESISTIVE MEMORY DEVICE AND RESISTIVE MEMORY SYSTEM INCLUDING A PLU...
- Publication number 20190051353
- Publication date Feb 14, 2019
- Samsung Electronics Co., Ltd.
- Eun-chu OH
- G06 - COMPUTING CALCULATING COUNTING
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DATA STATE SYNCHRONIZATION
- Publication number 20190035461
- Publication date Jan 31, 2019
- Micron Technology, Inc.
- Marco Dallabora
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT HAVING CONCURRENT WRITES AND METHOD THEREFOR
- Publication number 20180366191
- Publication date Dec 20, 2018
- NXP USA, Inc.
- Perry H. PELLEY
- G11 - INFORMATION STORAGE
Information Patent Application
RRAM, and Methods of Storing and Retrieving Information for RRAM
- Publication number 20180358095
- Publication date Dec 13, 2018
- Micron Technology, Inc.
- Adam Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY
- Publication number 20180190349
- Publication date Jul 5, 2018
- Micron Technology, Inc.
- Hernan A. Castro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RRAM, and Methods of Storing and Retrieving Information for RRAM
- Publication number 20180122475
- Publication date May 3, 2018
- Micron Technology, Inc.
- Adam Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
RRAM, and Methods of Storing and Retrieving Information for RRAM
- Publication number 20180122476
- Publication date May 3, 2018
- Micron Technology, Inc.
- Adam Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
RRAM ARRAY WITH CURRENT LIMITING ELEMENT
- Publication number 20180102171
- Publication date Apr 12, 2018
- Taiwan Semiconductor Manufacturing Co., LTD
- Chia-Fu Lee
- G11 - INFORMATION STORAGE
Information Patent Application
BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGR...
- Publication number 20180019009
- Publication date Jan 18, 2018
- III Holdings 1, LLC
- Robert Norman
- G11 - INFORMATION STORAGE
Information Patent Application
BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGR...
- Publication number 20180019008
- Publication date Jan 18, 2018
- III Holdings 1, LLC
- Robert Norman
- G11 - INFORMATION STORAGE
Information Patent Application
ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY
- Publication number 20170352410
- Publication date Dec 7, 2017
- Micron Technology, Inc.
- Hernan A. Castro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMRISTIVE DOT PRODUCT ENGINE WITH A NULLING AMPLIFIER
- Publication number 20170249989
- Publication date Aug 31, 2017
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- John Paul STRACHAN
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS ON RRAM CELLS
- Publication number 20170178723
- Publication date Jun 22, 2017
- RAMBUS INC.
- Brent Steven Haukness
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20150221368
- Publication date Aug 6, 2015
- KABUSHIKI KAISHA TOSHIBA
- Hiroshi KANNO
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING VARIABLE RESISTAN...
- Publication number 20140376303
- Publication date Dec 25, 2014
- KABUSHIKI KAISHA TOSHIBA
- Akira TAKASHIMA
- G11 - INFORMATION STORAGE
Information Patent Application
DATA ENCODING FOR NON-VOLATILE MEMORY
- Publication number 20140379961
- Publication date Dec 25, 2014
- SANDISK TECHNOLOGIES INC.
- MENAHEM LASSER
- G06 - COMPUTING CALCULATING COUNTING

Write with the simultaneous writing of a plurality of cells

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Distinct chip identifier sequence utilizing unclonable characterist...

2T-1R architecture for resistive ram

2T-1R architecture for resistive RAM

Distinct chip identifier sequence utilizing unclonable characterist...

Distinct chip identifier sequence utilizing unclonable characterist...

Distinct chip identifier sequence utilizing unclonable characterist...

Distinct chip identifier sequence utilizing unclonable characterist...

Distinct chip identifier sequence utilizing unclonable characterist...

System and method for performing memory operations in RRAM cells

Synapse memory cell driver

Memory devices and memory operational methods

1T-1R architecture for resistive random access memory

2T-1R architecture for resistive RAM

Data state synchronization

Neural network circuit

Memory circuit and formation method thereof

Memory circuit and formation method thereof

Accessing memory cells in parallel in a cross-point array

1T-1R architecture for resistive random access memory

Resistive memory device and resistive memory system including a plu...

System and method for performing memory operations in RRAM cells

2T-1R architecture for resistive ram

Memory systems and memory writing methods

Data state synchronization

Memory circuit having concurrent writes and method therefor

RRAM array with current limiting element

Memory circuit and formation method thereof

Memory devices and methods of writing memory cells at different mom...

1T-1R architecture for resistive random access memory

Accessing memory cells in parallel in a cross-point array

Patents Applicationslast 30 patents

2T-1R ARCHITECTURE FOR RESISTIVE RAM

DISTINCT CHIP IDENTIFIER SEQUENCE UTILIZING UNCLONABLE CHARACTERIST...

DISTINCT CHIP IDENTIFIER SEQUENCE UTILIZING UNCLONABLE CHARACTERIST...

2T-1R ARCHITECTURE FOR RESISTIVE RAM

SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS IN RRAM CELLS

2T-1R ARCHITECTURE FOR RESISTIVE RAM

DATA STATE SYNCHRONIZATION

MEMORY CIRCUIT AND FORMATION METHOD THEREOF

1T-1R ARCHITECTURE FOR RESISTIVE RANDOM ACCESS MEMORY

ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY

Memory Devices and Memory Operational Methods

SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS IN RRAM CELLS

2T-1R ARCHITECTURE FOR RESISTIVE RAM

RRAM ARRAY WITH CURRENT LIMITING ELEMENT

RESISTIVE MEMORY DEVICE AND RESISTIVE MEMORY SYSTEM INCLUDING A PLU...

DATA STATE SYNCHRONIZATION

MEMORY CIRCUIT HAVING CONCURRENT WRITES AND METHOD THEREFOR

RRAM, and Methods of Storing and Retrieving Information for RRAM

ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY

RRAM, and Methods of Storing and Retrieving Information for RRAM

RRAM, and Methods of Storing and Retrieving Information for RRAM

RRAM ARRAY WITH CURRENT LIMITING ELEMENT

BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGR...

BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGR...

ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY

MEMRISTIVE DOT PRODUCT ENGINE WITH A NULLING AMPLIFIER

SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS ON RRAM CELLS

SEMICONDUCTOR MEMORY DEVICE

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING VARIABLE RESISTAN...

DATA ENCODING FOR NON-VOLATILE MEMORY