Σ-Δ difference-of-squares RMS to DC converter with multiple feedback paths

Abstract

Architectures of ΣΔ difference-of-squares RMS-to-digital converters employing multiple feedback paths. Additional feedback paths enable a stable ΣΔ closed-loop behavior in different topologies where the RMS level of the quantization error processed by the squaring non-linearity is minimized. Such feedback paths include lowpass filtered and constant gain feedback paths, lowpass and highpass filtered paths or multiple lowpass filtered paths. These can be combined with multiple integrators in the forward path, with frequency compensation provided by additional feedforward or feedback paths. Electronic configurability can further extend the total input referred dynamic range (DR) of such architectures.

Description

FIELD OF THE INVENTION

The present invention relates to sigma-delta modulators, and in particular, to sigma-delta modulators used for converting root-mean-square (RMS) signal values to direct current (DC) signals.

RELATED ART

Digital RMS-to-DC converters are electronic circuits that generate a digitally encoded output signal, whose average (DC-level) is proportional to the Root-Mean-Square value (the square-root of the power) of the input signal. RMS-to-DC converters are used in a variety of applications, such as test and measurement, and communications, were a measure of the signal strength is important. A specific property of such devices is that their response is insensitive to crest factor variations. This is especially important in applications were the converter input signals can attain multiple different formats (modulation parameters, variable coding, etc. . . . ). In the context of mobile communication equipments (e.g. cellular telephones and base stations), the power level that is transmitted via the antenna needs to be measured accurately.

The block diagram in FIG. 1 illustrates the back-end section of a handset. The antenna is connected to a duplexer, i.e. a switch to redirect either the signal to be transmitted to the antenna or to redirect the received signal from the antenna to the receiver circuit (Rx). The power amplifier (PA) that supplies the RF signal to be transmitted is connected via a coupler to the antenna. The coupler feeds a fixed portion (on the order of 10%) of the transmitted power to the digital power detector. The detector provides a digitally encoded estimation of the transmitted power to the digital control block. Based on the measurement results obtained from this detector, the variable gain amplifier (VGA) is controlled to obtain the required transmit-power level. Alternatively, in order to increase the PA efficiency, the detector output can be used directly to control the PA's power supply adjustable DC-DC converter unity (SUPA)

Over the years, several types of analog RF power detectors have been used. These detectors range from a single diode to complex systems with higher accuracy and temperature stability.

The ΣΔ modulator can be combined with the difference-of-squares RMS-to-DC converter, resulting in an RMS-to-DC converter with intrinsic digital output. This mixed-signal system is named “ΣΔ difference-of-squares RMS-to-DC converter” and is described in U.S. Pat. Nos. 7,545,302 and 7,545,303 (the disclosures of which are incorporated herein by reference). In this architecture, the measured RMS level of the RF input is coded as the DC level of the modulator digital output bitstream y[k]. The ΣΔ difference-of-squares RMS-to-DC converter can be implemented based on feedforward and feedback squaring operations as depicted in FIG. 2A, or around a forward path multiplier as depicted in FIG. 2B.

The large-signal operation of ΣΔ RMS-to-DC converters is similar to the operation of their analog counterparts. In FIGS. 2A and 2B, the error signal e(t) is proportional to the difference between the squared input signal x(t)² and the squared feedback signal y(t)². The feedback signal y(t)=y_DC+q(t) is the analog version of the digital output y[k], where y_DC is the DC level of the modulator output and q(t) is the quantization error added during the internal analog-to-digital conversion of the integrator output u(t). Based on the relation between y(t), x(t) and u(t), the large-signal static transfer of the ΣΔ difference-of-squares RMS-to-DC converter can be calculated:

$\begin{array}{cc}{y}_{\mathrm{DC}}=\frac{-1}{2{\mathrm{AK}}_y}+\sqrt{\frac{1}{{\left(2{\mathrm{AK}}_y\right)}^2}+\frac{K_x}{K_y}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q\left(t\right)}^2}}& \left(1A\right)\\ y_{\mathrm{DC}}=\frac{-1}{2{\mathrm{AK}}_m{\beta }_y^2}+\sqrt{\frac{1}{{\left(2{\mathrm{AK}}_m{\beta }_y^2\right)}^2}+\frac{{\beta }_x^2}{{\beta }_y^2}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q\left(t\right)}^2}}& \left(1B\right)\end{array}$ where A is the actual integrator DC-gain, expression (1A) was obtained based on FIG. 2A and expression (1B) was obtained based on FIG. 2B. When A approaches infinity, (1A) and (1B) become:

$\begin{array}{cc}\underset{A->\infty }{\lim }{y}_{\mathrm{DC}}=\sqrt{\frac{K_x}{K_y}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q\left(t\right)}^2}}=\sqrt{\frac{K_x}{K_y}{x}_{\mathrm{RMS}}^2-q_{\mathrm{RMS}}^2}& \left(2A\right)\\ \underset{A->\infty }{\lim }{y}_{\mathrm{DC}}=\sqrt{\frac{{\beta }_x^2}{{\beta }_y^2}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q\left(t\right)}^2}}=\sqrt{\frac{{\beta }_x^2}{{\beta }_y^2}{x}_{\mathrm{RMS}}^2-q_{\mathrm{RMS}}^2}& \left(2B\right)\end{array}$

The steady-state DC solution for the ΣΔ RMS-to-DC converter depicted in FIGS. 2A and 2B is very similar to the solution obtained for analog RMS-to-DC converters. The major difference is the additional term accounting for the quantization error mean-square value q_RMS². This term arises from the fact that the feedback bitstream, containing both the measured input RMS level at DC and the added quantization error at high frequencies, is squared. In practice, the value of q_RMS² influences the law-conformance error for small input-power levels and defines the lower limit of the input-referred dynamic range. When q_RMS²>x_RMS², expressions (2A) and (2B) are no longer valid and the integrator's output u(t) clips to the negative supply voltage.

The addition of a filter in the feedback path allows an effective reduction of the quantization error mean-square value before the squaring operation. This technique is especially useful in the case of single-bit (M=1) internal quantization. The block diagrams of ΣΔ RMS-to-DC converters employing filtering in the feedback path are depicted in FIGS. 3A and 3B.

Based on FIGS. 3A and 3B, the large-signal static transfer of the ΣΔ difference-of-squares RMS-to-DC converters can be again calculated (A→∞):

$\begin{array}{cc}\underset{A->\infty }{\lim }{y}_{\mathrm{DC}}=\sqrt{\frac{K_x}{K_y}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_f\left(t\right)}^2}}& \left(3A\right)\\ \underset{A->\infty }{\lim }{y}_{\mathrm{DC}}=\sqrt{\frac{{\beta }_x^2}{{\beta }_y^2}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_f\left(t\right)}^2}}& \left(3B\right)\end{array}$ where q_f(t)=y_f(t)−y_DC is the filtered quantization noise error. Because the mean-square value of the filtered quantization error is smaller ( q_f(t)²< q(t)²), the digital detector's output dynamic range is extended. However, the addition of a filter in the feedback path may impact the stability of the ΣΔ RMS-to-DC converter. In order to analyze the converter's closed loop stability, the signal-dependent AC-gain k associated with the non-linear feedback and feedforward squaring operations has to be defined. When the ΣΔ difference-of-squares modulator is implemented with two squaring cells, as in FIGS. 2A and 3A, k is given by (K_x=K_y):

$\begin{array}{cc}k=\frac{d}{dv}\left(K_x·v^2\right){❘}_{v=x_{\mathrm{RMS}}}=2·K_x·x_{\mathrm{RMS}}& \left(4A\right)\end{array}$

When the ΣΔ difference-of-squares modulator is implemented with a forward path multiplier, as in FIGS. 2B and 3B, k is given by (β_x=β_y):

$\begin{array}{cc}k=\frac{d}{dv}\left(K_m·{\beta }_x^2·v^2\right){❘}_{v=x_{\mathrm{RMS}}}=2·K_m·{\beta }_x^2·x_{\mathrm{RMS}}& \left(4B\right)\end{array}$

The mean-square value of the filtered quantization noise q_f(t) is minimized in ΣΔ RMS-to-DC converter architectures shown in FIGS. 3A and 3B when the chosen feedback filter is an N^th-order lowpass filter (LPF) with −20*N dB/dec attenuation. FIG. 4 shows the AC linearized model for this situation.

Based on FIG. 4, the signal-dependent feedback loop filter L₁(s) can be expressed:

$\begin{array}{cc}{L}_1\left(s\right)=\frac{U\left(s\right)}{Y\left(s\right)}=-\frac{k{\omega }_1}{{s\left(s{\tau }_P+1\right)}^N}& \left(5\right)\end{array}$

Because (5) contains N+1 poles and no zeros, the choice of a LPF (of any order N) in the feedback path of the architecture shown in FIGS. 3A and 3B always yields unstable ΣΔ RMS-to-DC converters. In order to implement stable ΣΔ RMS-to-DC converters, the N^th-order feedback LPF should be compensated with N high-frequency zeros as depicted in FIG. 5.

Based on FIG. 5, the signal-dependent feedback loop filter L₁(s) can be again expressed:

$\begin{array}{cc}{L}_1\left(s\right)=\frac{U\left(s\right)}{Y\left(s\right)}=-\frac{k{\omega }_1}{s}·\frac{{\left(s{\tau }_Z+1\right)}^N}{{\left(s{\tau }_P+1\right)}^N}& \left(6\right)\end{array}$

Because (5) contains N+1 poles and N zeros, it is possible to design and implement stable ΣΔ RMS-to-DC converters based on the architecture shown in FIGS. 3A and 3B when the feedback filter contains N poles and zeros. The price paid for the stability of the closed loop system is an increase on the obtained mean-square value of the filtered quantization noise q_f(t). This happens because the pole-zero filter −20*N dB/dec attenuation roll-off takes place only within a limited frequency range below half the system's sampling frequency (f_s/2).

SUMMARY

Architectures of ΣΔ difference-of-squares RMS-to-digital converters employing multiple feedback paths. Additional feedback paths enable a stable ΣΔ closed-loop behavior in different topologies where the RMS level of the quantization error processed by the squaring non-linearity is minimized. Such feedback paths include lowpass filtered and constant gain feedback paths, lowpass and highpass filtered paths or multiple lowpass filtered paths. These can be combined with multiple integrators in the forward path, with frequency compensation provided by additional feedforward or feedback paths. Electronic configurability can further extend the total input referred dynamic range (DR) of such architectures.

In accordance with one embodiment of the presently claimed invention, a sigma-delta difference-of-squares RMS-to-DC converter includes:

analog signal multiplication and combining circuitry responsive to an analog input signal and at least first and second analog feedback signals by providing a resultant analog signal that includes at least one signal component corresponding to a difference between a square of the analog input signal, a square of the first analog feedback signal and the second analog feedback signal;

analog signal filter circuitry coupled to the analog signal multiplication and combining circuitry, and responsive to the resultant analog signal by providing a filtered analog signal;

analog-to-digital conversion (ADC) circuitry coupled to the analog signal filter circuitry and responsive to the filtered analog signal by providing a related digital output signal;

digital-to-analog conversion (DAC) circuitry coupled to the ADC circuitry and responsive to the digital output signal by providing an analog signal;

first feedback circuitry coupled between the DAC circuitry and the analog signal multiplication and combining circuitry, and responsive to the analog signal by providing the first analog feedback signal; and

second feedback circuitry coupled between the DAC circuitry and the analog signal multiplication and combining circuitry, and responsive to the analog signal by providing the second analog feedback signal.

In accordance with another embodiment of the presently claimed invention, a sigma-delta difference-of-squares RMS-to-DC converter includes:

analog signal multiplier and combiner means for multiplying and combining an analog input signal and at least first and second analog feedback signals to provide a resultant analog signal that includes at least one signal component corresponding to a difference between a square of the analog input signal, a square of the first analog feedback signal and the second analog feedback signal;

analog signal filter means for filtering the resultant analog signal to provide a filtered analog signal;

analog-to-digital converter (ADC) means for converting the filtered analog signal to a related digital output signal;

digital-to-analog converter (DAC) means for converting the digital output signal to an analog signal;

first feedback means for processing the analog signal to provide the first analog feedback signal; and

second feedback means for processing the analog signal to provide the second analog feedback signal.

In accordance with another embodiment of the presently claimed invention, a method for performing a sigma-delta difference-of-squares RMS-to-DC conversion includes:

multiplying and combining an analog input signal and at least first and second analog feedback signals to provide a resultant analog signal that includes at least one signal component corresponding to a difference between a square of the analog input signal, a square of the first analog feedback signal and the second analog feedback signal;

filtering the resultant analog signal to provide a filtered analog signal;

converting the filtered analog signal to a related digital output signal;

converting the digital output signal to an analog signal;

processing the analog signal to provide the first analog feedback signal; and

processing the analog signal to provide the second analog feedback signal.

In accordance with another embodiment of the presently claimed invention, a sigma-delta difference-of-squares RMS-to-DC converter includes:

analog signal multiplication and combining circuitry responsive to an analog input signal and a first analog feedback signal by providing a resultant analog signal that includes at least one signal component corresponding to a difference between a square of the analog input signal and a square of the first analog feedback signal;

analog signal filtering and combining circuitry coupled to the analog signal multiplication and combining circuitry, and responsive to the resultant analog signal and at least a second analog feedback signal by providing a feedforward signal;

analog-to-digital conversion (ADC) circuitry coupled to the analog signal filtering and combining circuitry and responsive to the feedforward signal by providing a related digital output signal; and

feedback circuitry, including digital-to-analog conversion (DAC) circuitry, coupled between the ADC circuitry, the analog signal multiplication and combining circuitry and the analog signal combining circuitry, and responsive to the digital output signal by providing the first analog feedback signal and the at least a second analog feedback signal.

In accordance with another embodiment of the presently claimed invention, a sigma-delta difference-of-squares RMS-to-DC converter includes:

analog signal multiplier and combiner means for multiplying and combining an analog input signal and a first analog feedback signal to provide a resultant analog signal that includes at least one signal component corresponding to a difference between a square of the analog input signal and a square of the first analog feedback signal;

analog signal filter and combiner means for filtering and combining the resultant analog signal and at least a second analog feedback signal to provide a feedforward signal;

analog-to-digital converter (ADC) means for converting the feedforward signal to a related digital output signal; and

feedback means, including digital-to-analog converter (DAC) means, for converting the digital output signal to the first analog feedback signal and the at least a second analog feedback signal.

In accordance with another embodiment of the presently claimed invention, a method for performing a sigma-delta difference-of-squares RMS-to-DC conversion includes:

multiplying and combining an analog input signal and a first analog feedback signal to provide a resultant analog signal that includes at least one signal component corresponding to a difference between a square of the analog input signal and a square of the first analog feedback signal;

filtering and combining the resultant analog signal and at least a second analog feedback signal to provide a feedforward signal;

converting the feedforward signal to a related digital output signal; and

converting the digital output signal to the first analog feedback signal and the at least a second analog feedback signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a typical application diagram of a digital RF power detector.

FIG. 2A depicts a ΣΔ difference-of-squares RMS-to-DC converter using two squaring circuits.

FIG. 2B depicts a ΣΔ difference-of-squares RMS-to-DC converter based on forward path multiplier.

FIG. 3A depicts a ΣΔ difference-of-squares RMS-to-DC converter using two squaring circuits and filtering in the feedback path.

FIG. 3B depicts a ΣΔ difference-of-squares RMS-to-DC converter based on forward path multiplier and filtering in the feedback path.

FIG. 4 depicts a ΣΔ difference-of-squares RMS-to-DC converter small-signal linear model with N^th-order LPF in the feedback path.

FIG. 5 depicts a ΣΔ difference-of-squares RMS-to-DC converter small-signal linear model with N^th-order Pole-Zero filter in the feedback path.

FIG. 6 depicts a ΣΔ difference-of-squares RMS-to-DC converter small-signal linear model for the architecture depicted in FIGS. 7A/7B.

FIG. 7A depicts a ΣΔ difference-of-squares RMS-to-DC converter using two squaring circuits with additional constant feedback path.

FIG. 7B depicts a ΣΔ difference-of-squares RMS-to-DC converter based on forward path multiplier with additional constant feedback path.

FIG. 8 depicts a simulated output spectrum of the ΣΔ RMS-to-DC converter architectures depicted in FIGS. 7A/7B for a 1^st-order LPF, K_c=K_y/50=β_y²K_m/50 and P_in=0 dBm or −30 dBm.

FIG. 9 depicts a simulated transfer curve and law-conformance error of the ΣΔ RMS-to-DC converter architectures depicted in FIGS. 7A/7B for a 1^st-order LPF and K_c=K_y/50=β_y²K_m/50.

FIG. 10A depicts a ΣΔ difference-of-squares RMS-to-DC converter using two squaring circuits with lowpass and highpass filtered feedback paths.

FIG. 10B depicts a ΣΔ difference-of-squares RMS-to-DC converter based on forward path multiplier with lowpass and highpass filtered feedback paths.

FIG. 11 depicts a simulated transfer curve and law-conformance error of the ΣΔ RMS-to-DC converter architectures depicted in FIGS. 10A/10B for 1^st-order LPF/HPF (f_cHPF=f_cLPF) and K_q=K_y/50=β_y²K_m/50.

FIG. 12 depicts a simulated transfer curve and law-conformance error of the ΣΔ RMS-to-DC converter architectures depicted in FIGS. 10A/10B for 1^st-order LPF/HPF (f_cHPF=5f_cLPF) and K_q=K_y/50=β_y²K_m/50.

FIG. 13 depicts a ΣΔ difference-of-squares RMS-to-DC converter small-signal linear model for the architecture depicted in FIGS. 10A/10B with 1^st-order LPF and HPF (f_cHPF=f_cLPF).

FIG. 14 depicts a simulated output spectrum of the ΣΔ RMS-to-DC converter architectures depicted in FIGS. 10A/10B for 1^st-order LPF/HPF (f_cHPF=f_cLPF), K_q=K_y/50=β_y²K_m/50 and P_in=0 dBm or −30 dBm.

FIG. 15 depicts a ΣΔ difference-of-squares RMS-to-DC converter small-signal linear model for the architecture depicted in FIGS. 10A/10B with N^th-order LPF and HPF (f_cHPF=f_cLPF).

FIG. 16 depicts a ΣΔ difference-of-squares RMS-to-DC converter small-signal linear model for the architecture depicted in FIGS. 10A/10B with N^th-order LPF and HPF (f_cHPF=f_cLPF).

FIG. 17 depicts a ΣΔ difference-of-squares RMS-to-DC converter small-signal linear model for the architecture depicted in FIGS. 21A/21B.

FIG. 18 depicts a simulated output spectrum of the ΣΔ RMS-to-DC converter architectures depicted in FIGS. 21A/21B for 1^st-order LPF, K_L=16K_y=β_y²K_m and P_in=0 dBm or −30 dBm.

FIG. 19 depicts a simulated output spectrum of the ΣΔ RMS-to-DC converter architectures depicted in FIGS. 21A/21B for 1^st-order LPF, K_L=4K_y=4β_y²K_m and P_in=0 dBm or −30 dBm.

FIG. 20 depicts a simulated output spectrum of the ΣΔ RMS-to-DC converter architectures depicted in FIGS. 21A/21B for 1^st-order LPF, K_L=K_y=β_y²K_m and P_in=0 dBm or −30 dBm.

FIG. 21A depicts a ΣΔ difference-of-squares RMS-to-DC converter using two squaring circuits with lowpass filtered feedback paths.

FIG. 21B depicts a ΣΔ difference-of-squares RMS-to-DC converter based on forward path multiplier with lowpass filtered feedback paths.

FIG. 22 depicts a simulated transfer curve and law-conformance error of the ΣΔ RMS-to-DC converter architectures depicted in FIGS. 21A/21B for a 1^st-order LPF and K_L=4K_y or 16K_y.

FIG. 23 depicts a simulated transfer curve and law-conformance error of the ΣΔ RMS-to-DC converter architectures depicted in FIGS. 21A/21B for K_L=4K_y and A=100 dB, 80 dB or 60 dB.

FIG. 24 depicts a ΣΔ difference-of-squares RMS-to-DC converter small-signal linear model with multiple lowpass filtered feedback paths.

FIG. 25A depicts a ΣΔ difference-of-squares RMS-to-DC converter using two squaring circuits with multiple lowpass filtered feedback paths.

FIG. 25B depicts a ΣΔ difference-of-squares RMS-to-DC converter based on forward path multiplier with multiple lowpass filtered feedback paths.

FIG. 26A depicts a ΣΔ difference-of-squares RMS-to-DC converter using two squaring circuits with two integrators (feedforward compensation) and, lowpass and highpass filtered feedback paths.

FIG. 26B depicts a ΣΔ difference-of-squares RMS-to-DC converter based on forward path multiplier with two integrators (feedforward compensation) and, lowpass and highpass filtered feedback paths.

FIG. 27 depicts a ΣΔ difference-of-squares RMS-to-DC converter small-signal linear model with L integrators (feedforward compensation) and N^th-order feedback LPF/HPF.

FIG. 28A depicts a ΣΔ difference-of-squares RMS-to-DC converter using two squaring circuits with two integrators (feedforward compensation) and lowpass filtered feedback paths.

FIG. 28B depicts a ΣΔ difference-of-squares RMS-to-DC converter based on forward path multiplier with two integrators (feedforward compensation) and lowpass filtered feedback paths.

FIG. 29 depicts a ΣΔ difference-of-squares RMS-to-DC converter small-signal linear model with L integrators (feedforward compensation) and N^th-order feedback LPF.

FIG. 30A depicts a ΣΔ difference-of-squares RMS-to-DC converter using two squaring circuits with L integrators (feedback compensation).

FIG. 30B depicts a ΣΔ difference-of-squares RMS-to-DC converter based on forward path multiplier with L integrators (feedback compensation).

FIG. 31A depicts a ΣΔ difference-of-squares RMS-to-DC converter using two squaring circuits with two integrators (feedback compensation) and, lowpass and highpass filtered feedback paths.

FIG. 31B depicts a ΣΔ difference-of-squares RMS-to-DC converter based on forward path multiplier with two integrators (feedback compensation) and, lowpass and highpass filtered feedback paths.

FIG. 32 depicts a ΣΔ difference-of-squares RMS-to-DC converter small-signal linear model with L integrators (feedback compensation) and N^th-order feedback LPF/HPF.

FIG. 33A depicts a ΣΔ difference-of-squares RMS-to-DC converter using two squaring circuits with two integrators (feedback compensation) and lowpass filtered feedback path.

FIG. 33B depicts a ΣΔ difference-of-squares RMS-to-DC converter based on forward path multiplier with two integrators (feedback compensation) and lowpass filtered feedback path.

FIG. 34 depicts a ΣΔ difference-of-squares RMS-to-DC converter small-signal linear model with N integrators (feedback compensation) and N^th-order feedback LPF.

FIG. 35 depicts a configurable ΣΔ difference-of-squares RMS-to-DC converter using two squaring circuits with two integrators (feedback compensation) and lowpass filtered feedback path.

FIG. 36 depicts a configurable ΣΔ difference-of-squares RMS-to-DC converter based on forward path multiplier with two integrators (feedforward compensation) and, lowpass and highpass filtered feedback paths.

FIG. 37 depicts a configurable ΣΔ difference-of-squares RMS-to-DC converter.

FIG. 38 depicts a possible electronic implementation of the ΣΔ difference-of-squares RMS-to-DC converter architecture depicted in FIGS. 21A/21B.

DETAILED DESCRIPTION

The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention.

Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. Further, while the present invention has been discussed in the context of implementations using discrete electronic circuitry (preferably in the form of one or more integrated circuit chips), the functions of any part of such circuitry may alternatively be implemented using one or more appropriately programmed processors, depending upon the signal frequencies or data rates to be processed. Moreover, to the extent that the Figures illustrate diagrams of the functional blocks of various embodiments, the functional blocks are not necessarily indicative of the division between hardware circuitry. Thus, for example, one or more of the functional blocks (e.g., processors, memories, etc.) may be implemented in a single piece of hardware (e.g., a general purpose signal processor, random access memory, hard disk drive, etc.). Similarly, any programs described may be standalone programs, may be incorporated as subroutines in an operating system, may be functions in an installed software package, etc.

Discussed below are several architectures of ΣΔ difference-of-squares RMS-to-DC converters with multiple feedback paths for providing multiple processed (e.g., filtered, scaled, or filtered and scaled) feedback signals. The addition of extra feedback paths allows the design of stable ΣΔ RMS to digital converters where the main feedback path feeding the non-linear squaring operation contains an N^th-order LPF with −20*N dB/dec roll-off attenuation for frequencies far beyond the system sampling frequency (f_s). Described below is a ΣΔ RMS-to-DC converter with lowpass filtered and constant gain feedback paths. Also described below is a ΣΔ RMS-to-DC converter with lowpass and highpass filtered feedback paths. Also described below is a ΣΔ RMS-to-DC converter with multiple lowpass filtered feedback paths. Also described below is how these techniques are combined with multiple integrators stabilized by, respectively, additional feedforward and feedback paths. As also described below, the concept of configurability is applied to all architectures previously described.

The simplest way to stabilize the ΣΔ RMS-to-DC converter architecture depicted in FIG. 4, without compromising the high-frequency quantization error attenuation as in FIG. 5, is to add a second feedback path with signal scaling, e.g., provided by an amplifier with constant gain K_c. This situation is depicted in FIG. 6 where a generic N^th-order LPF is in series with the feedback path connected to the non-linear squaring operation (represented by the linearized AC-gain k).

Based on FIG. 6, the signal-dependent feedback loop filter L₁(s) can be expressed:

$\begin{array}{cc}{L}_1\left(s\right)=\frac{U\left(s\right)}{Y\left(s\right)}=-\frac{{\omega }_1}{s}·\left(\frac{k+K_c·{\left(s{\tau }_P+1\right)}^N}{{\left(s{\tau }_P+1\right)}^N}\right)& \left(7\right)\end{array}$

The resulting transfer function contains N+1 poles and N zeros, and it can be designed to be conditionally stable for a certain range of input power levels (k∝x_RMS). The greater the filter order N is, the more difficult it becomes to design a stable loop filter for high input power levels (k→∞):

$\begin{array}{cc}\underset{k>>K_c}{\lim }{L}_1\left(s\right)=-\frac{k{\omega }_1}{s}·\frac{1}{{\left(s{\tau }_P+1\right)}^N}& \left(8\right)\end{array}$ In the case of very small input power levels (k→0), L₁(s) becomes an always stable 1^st order loop filter:

$\begin{array}{cc}\underset{k<<K_c}{\lim }{L}_1\left(s\right)=-\frac{K_c{\omega }_1}{s}& \left(9\right)\end{array}$ FIGS. 7A and 7B show the main possible implementations of a ΣΔ difference-of-squares RMS-to-DC converter based on the linearized closed loop system in FIG. 6. Equivalent implementations can be achieved when two separated feedback DACs are employed and/or the LPF is implemented in the digital domain. The LPF transfer function, depicted as an N^th-order binomial in the above calculations, can be implemented with any different set of coefficients (e.g. Butterworth, Chebyshev, etc. . . . ).

The simulated output spectrum of the ΣΔ RMS-to-DC converter architectures depicted in FIGS. 7A/7B is shown in FIG. 8 when a 1^st-order LPF is employed in the feedback path and V_ref (the ADC/DAC reference voltage) is set to 1.6V. For P_in=0 dBm, the modulator output is stable and the quantization noise presents a 2^nd-order roll-off (40 dB/dec) as predicted by (7). For P_in=−30 dBm, the quantization noise presents a 1^st-order roll-off (20 dB/dec) as predicted by (9)

Based on the relation between y(t), x(t) and u(t), the large-signal static transfer of the ΣΔ difference-of-squares RMS-to-DC converters shown in FIGS. 7A and 7B can be calculated:

$\begin{array}{cc}{y}_{\mathrm{DC}}=-\left(\frac{1}{2{\mathrm{AK}}_y}+\frac{K_c}{2K_y}\right)+\sqrt{{\left(\frac{1}{2{\mathrm{AK}}_y}+\frac{K_c}{2K_y}\right)}^2+\frac{K_x}{K_y}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(10A\right)\\ y_{\mathrm{DC}}=-\left(\frac{1}{2{\mathrm{AK}}_m{\beta }_y^2}+\frac{K_c}{2K_m{\beta }_y^2}\right)+\sqrt{{\left(\frac{1}{2{\mathrm{AK}}_m{\beta }_y^2}+\frac{K_c}{2K_m{\beta }_y^2}\right)}^2+\frac{{\beta }_x^2}{{\beta }_x^2}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(10B\right)\end{array}$ where A is the actual integrator DC-gain, q_lp(t)=y_lp(t)−y_DC is the lowpass filtered quantization noise error, expression (10A) was obtained based on FIG. 7A and expression (10B) was obtained based on FIG. 7B. When A approaches infinity, (10A) and (10B) become:

$\begin{array}{cc}\underset{A\to \infty }{\lim }{y}_{\mathrm{DC}}=-\frac{K_c}{2K_y}+\sqrt{{\left(\frac{K_c}{2K_y}\right)}^2+\frac{K_x}{K_y}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(11A\right)\\ \underset{A\to \infty }{\lim }{y}_{\mathrm{DC}}=\frac{-K_c}{2K_m{\beta }_y^2}+\sqrt{{\left(\frac{K_c}{2K_m{\beta }_y^2}\right)}^2+\frac{{\beta }_x^2}{{\beta }_y^2}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(11B\right)\end{array}$

The steady-state DC solution for the ΣΔ RMS-to-DC converters depicted in FIGS. 7A and 7B present two main characteristics. First, the RMS level of the squared quantization error is reduced ( q_lp(t)²< q(t)²) by the feedback LPF. Second, an undesirable systematic error proportional to K_c is added to the converter's DC transfer characteristic. The simulated transfer curve and the law-conformance error for these ΣΔ RMS-to-DC converter architectures are shown in FIG. 9 when a 1^st-order LPF is employed in the feedback path and K_c=K_y/50=β_y²K_m/50.

The major drawback of the ΣΔ RMS-to-DC converter architectures shown is FIGS. 7A and 7B is the presence of a systematic error proportional to K_c in the converter's output. This problem can be solved if a highpass filter (HPF) is placed in series with the additional feedback path. FIGS. 10A and 10B illustrate the main possible implementations based on this concept. Equivalent implementations can be achieved when two separated feedback DACs are employed and/or the LPF and HPF are implemented in the digital domain.

Based on the relation between y(t), x(t) and u(t), the large-signal static transfer of the ΣΔ difference-of-squares RMS-to-DC converters depicted in FIGS. 10A and 10B can be calculated (A→∞):

$\begin{array}{cc}\underset{A\to \infty }{\lim }{y}_{\mathrm{DC}}=\sqrt{\frac{K_x}{K_y}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(12A\right)\\ \underset{A\to \infty }{\lim }{y}_{\mathrm{DC}}=\sqrt{\frac{{\beta }_x^2}{{\beta }_y^2}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(12B\right)\end{array}$ where q_lp(t)=y_lp(t)−y_DC is the lowpass filtered quantization noise error, expression (12A) was obtained based on FIG. 10A and expression (12B) was obtained based on FIG. 10B. Again the RMS level of the squared quantization error is reduced by the feedback LPF. In this case however, because the additional feedback path can be considered “open” for DC signals, no systematic error proportional to the constant gain K_q is added to the converter's DC transfer characteristic. The simulated transfer curve and the law-conformance error for these ΣΔ RMS-to-DC converter architectures are shown in FIG. 11 when 1^st-order LPF/HPF are employed in the feedback paths and K_q=K_y/50=β_y²K_m/50. In this simulation, both feedback LPF and HPF have the same cut-off frequency (f_cHPF=f_cLPF). In comparison with FIG. 9, it is possible to notice how the law-conformance error is minimized by the addition of the feedback HPF.

FIG. 11 also shows the law-conformance error (dashed curves, right plot) for the architecture depicted in FIGS. 3A/3B when a 1^st-order pole-zero filter is employed in the single feedback path (FIG. 5). Due to the additional quantization noise filtering ( q_lp(t)²< q_f(t)²), the input referred DR is greatly enlarged. At low power levels and low V_ref values however, a residual systematic error limits this improvement. This residual systematic error is not predicted by expressions (12A) and (12B), but it can be reduced by increasing the HPF cut-off frequency (f_cHPF). This residual DC error is reduced when the low-frequency attenuation through the high-frequency feedback path is increased. FIG. 12 shows the simulated transfer curve and the law-conformance error in the case f_cHPF=5f_cLPF. For V_ref=0.1V, the output DR is larger in FIG. 12 (compared to FIG. 11) because the residual systematic error has been reduced.

The small-signal AC model for this ΣΔ RMS-to-DC converter architecture is shown in FIG. 13 for the case of 1^st-order feedback LPF and HPF (f_cHPF=f_cLPF).

Based on FIG. 13, the signal-dependent feedback loop filter L₁(s) can be expressed:

$\begin{array}{cc}{L}_1\left(s\right)=\frac{U\left(s\right)}{Y\left(s\right)}=-\frac{{\omega }_1}{s}·\left(\frac{k+K_q·s{\tau }_P}{s{\tau }_P+1}\right)& \left(13\right)\end{array}$

The resulting transfer function contains 2 poles and 1 zero, and it can be designed to be conditionally stable for a certain range of input power levels (k∝x_RMS). When the squaring non-linearity small-signal gain k equals the constant gain K_q, L₁(s) becomes a stable 1^st order loop filter:

$\begin{array}{cc}\underset{k\to K_q}{\lim }{L}_1\left(s\right)=-\frac{K_q{\omega }_1}{s}& \left(14\right)\end{array}$

When the input power level is very high (k→∞), L₁(s) becomes an unstable 2^nd-order loop filter:

$\begin{array}{cc}\underset{k>>K_q}{\lim }{L}_1\left(s\right)=-\frac{k{\omega }_1}{s}·\frac{1}{s{\tau }_P+1}& \left(15\right)\end{array}$

In the case of very small input power levels (k→0), L₁(s) is a stable 1^st order loop filter with a finite DC-gain:

$\begin{array}{cc}\underset{k<<K_q}{\lim }{L}_1\left(s\right)=-\frac{K_q{\omega }_1}{s+1/{\tau }_P}& \left(16\right)\end{array}$

The simulated output spectrum of the ΣΔ RMS-to-DC converter architectures depicted in FIGS. 10A/10B is shown in FIG. 14 when 1^St-order LPF/HPF are employed in the feedback paths (FIG. 13). For P_in=0 dBm, the modulator output is stable and the quantization noise presents a 2^nd-order roll-off (40 dB/dec) as predicted by (13). For P_in=−30 dBm, the quantization noise presents a 1^st-order roll-off (20 dB/dec) as predicted by (16)

The ΣΔ RMS-to-DC converter architectures depicted in FIGS. 10A/10B can be generalized regarding the order of the feedback filtering. The small-signal AC model in this case is shown in FIG. 15 for the case of N^th-order LPF and HPF (f_cHPF=f_cLPF).

Based on FIG. 15, the signal-dependent feedback loop filter L₁(s) can be expressed:

$\begin{array}{cc}{L}_1\left(s\right)=\frac{U\left(s\right)}{Y\left(s\right)}=-\frac{{\omega }_1}{s}·\left(\frac{k+K_q·{\left(s{\tau }_P\right)}^N}{{\left(s{\tau }_P+1\right)}^N}\right)& \left(17\right)\end{array}$

In this case however (FIG. 15), because L₁(s) does not converge to a 1^st-order loop filter when k→K_q, it is harder to design a conditionally stable (N+1)^th-order ΣΔ RMS-to-DC converter with a DR that is large enough to be practical. An alternative approach, where L₁(s) is a 1^st-order loop filter for k=K_q, is depicted FIG. 16.

Based on FIG. 16, the signal-dependent feedback loop filter L₁(s) can be expressed again:

$\begin{array}{cc}{L}_1\left(s\right)=\frac{U\left(s\right)}{Y\left(s\right)}=-\frac{{\omega }_1}{s}·\left(\frac{k+K_q·{\left(s{\tau }_P+1\right)}^N-K_q}{{\left(s{\tau }_P+1\right)}^N}\right)& \left(18\right)\end{array}$

When the input power level is very high (k→∞), L₁(s) becomes an unstable (N+1)^th-order loop filter:

$\begin{array}{cc}\underset{k>>K_q}{\lim }{L}_1\left(s\right)=-\frac{k{\omega }_1}{s}·\frac{1}{{\left(s{\tau }_P+1\right)}^N}& \left(19\right)\end{array}$

When the squaring non-linearity small-signal gain k equals the constant gain K_q, L₁(s) is an always stable 1^st-order loop filter as in (14):

$\begin{array}{cc}\underset{k\to K_q}{\lim }{L}_1\left(s\right)=-\frac{K_q{\omega }_1}{s}& \left(20\right)\end{array}$

In the case of very small input power levels (k→0), L₁(s) approaches a 1^st-order loop filter when the feedback filter time-constant τ_p is large enough:

$\begin{array}{cc}\underset{k<<K_q}{\lim }{L}_1\left(s\right)=-\frac{K_q{\omega }_1}{s}·\frac{{\left(s+1/{\tau }_P\right)}^N-{\left(1/{\tau }_P\right)}^N}{{\left(s+1/{\tau }_P\right)}^N}& \left(21\right)\end{array}$

The resulting loop filter transfer function L₁(s) converges to a 1^st-order loop filter when k≦K_q. As a result, the closed loop system can be designed to be conditionally stable for a certain range of input power levels (k∝x_RMS). The LPF/HPF transfer functions, depicted as N^th-order binomials in the above calculations, can be implemented with any different set of coefficients (e.g. Butterworth, Chebyshev, etc. . . . ). In order to reduce the residual systematic error, the LPF and the HPF can have different cut-off frequencies (f_cHPF≠f_cLPF) at the expense of a less stable closed loop behavior.

The ΣΔ RMS-to-DC converter architectures shown is FIGS. 10A and 10B require a LPF and a HPF in order to achieve a large input-referred DR. A similar result can be achieved with a single LPF if the additional feedback path is connected after the loop filter integrator. The small-signal AC model illustrating this situation is depicted in FIG. 17 for a 1^st-order LPF.

The small-signal model in FIG. 17 can be easily obtained from the small-signal model in FIG. 13 (f_cHPF=f_cLPF). Based on FIG. 17, the signal-dependent feedback loop filter L₁(s) can be expressed:

$\begin{array}{cc}{L}_1\left(s\right)=\frac{U\left(s\right)}{Y\left(s\right)}=-\frac{{\omega }_1}{s}·\left(\frac{k+s·K_L/{\omega }_1}{s{\tau }_P+1}\right)& \left(22\right)\end{array}$ where K_L=K_qω₁τ_P. The resulting transfer function contains 2 poles and 1 zero, and it can be designed to be conditionally stable for a certain range of input power levels (k∝x_RMS). When the input power level is very high (k→∞), L₁(s) becomes an unstable 2^nd-order loop filter:

$\begin{array}{cc}\underset{k>>K_q}{\lim }{L}_1\left(s\right)=-\frac{k{\omega }_1}{s}·\frac{1}{s{\tau }_P+1}& \left(23\right)\end{array}$

When the squaring non-linearity small-signal gain k equals K_L/(ω₁τ_P), L₁(s) is a stable 1^st order loop filter:

$\begin{array}{cc}\underset{k->K_q}{\lim }{L}_1\left(s\right)=-\frac{K_L/{\tau }_P}{s}& \left(24\right)\end{array}$

In the case of very small input power levels (k→0), L₁(s) becomes a stable 1^st order loop filter with a finite DC-gain:

$\begin{array}{cc}\underset{k<<K_q}{\lim }{L}_1\left(s\right)=-\frac{K_L/{\tau }_P}{s+1/{\tau }_P}& \left(25\right)\end{array}$

The simulated output spectrum of the ΣΔ RMS-to-DC converter architecture depicted in FIG. 17 (also in FIGS. 21A/21B) is shown in FIGS. 18, 19 and 20 when a 1^st-order LPF is employed in the feedback path. For the simulation results shown in FIG. 18, K_L=16K_y and L₁(s) is a 1^st-order loop filter (20 dB/dec roll-off) for the whole range of input power levels as predicted by (24) and (25). However, as can be seen in the plot for P_in=0 dBm, the measured RMS voltage (DC level) is below −10 dB and consequently the law-conformance error is very large (see also FIG. 22).

FIG. 19 shows the simulation results obtained with K_L=4K_y. For P_in=0 dBm, the modulator output is stable and the quantization noise presents a 2^nd-order roll-off (40 dB/dec) as predicted by (22). In this case, the output DC level is 0 dB and consequently the law-conformance error is very small (see also FIG. 22). For P_in=−30 dBm, the quantization noise presents a 1^st-order roll-off (20 dB/dec) as predicted by (25)

For the simulation results shown in FIG. 20, K_L=K_y and L₁(s) is a 2^nd-order loop filter (40 dB/dec roll-off) for the whole range of input power levels as predicted by (22) and (23). However, as can be seen in the plot for P_in=0 dBm, the ΣΔ RMS-to-DC converter approaches an unstable behavior.

The parameter K_L, the gain factor of the constant feedback path in FIGS. 17 and 21A/21B, controls the trade-off between DC accuracy and stability. For K_L>>K_y, the closed-loop system is very stable but the law-conformance error is degraded for high input-power levels. For K_L→K_y, the closed-loop system is closer to instability but the law-conformance error is very small for high input-power levels

FIGS. 21A and 21B show the main possible implementations of a ΣΔ difference-of-squares RMS-to-DC converter based on the linearized closed loop system in FIG. 17. Equivalent implementations can be achieved when two separated sets of feedback DAC/LPF are employed and/or the LPF(s) is(are) implemented in the digital domain.

Based on the relation between y(t), x(t) and u(t), the large-signal static transfer of the ΣΔ difference-of-squares RMS-to-DC converters in FIGS. 21A/21B can be calculated:

$\begin{array}{cc}{y}_{\mathrm{DC}}=\frac{-\left(1+K_L\right)}{2{\mathrm{AK}}_y}+\sqrt{{\left(\frac{1+K_L}{2{\mathrm{AK}}_y}\right)}^2+\frac{K_x}{K_y}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(26A\right)\\ y_{\mathrm{DC}}=\frac{-\left(1+K_L\right)}{2{\mathrm{AK}}_m{\beta }_y^2}+\sqrt{{\left(\frac{1+K_L}{2{\mathrm{AK}}_m{\beta }_y^2}\right)}^2+\frac{{\beta }_x^2}{{\beta }_y^2}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(26B\right)\end{array}$ where A is the actual integrator DC-gain, q_lp(t)=y_lp(t)−y_DC is the lowpass filtered quantization noise error, expression (26A) was obtained based on FIG. 21A and expression (26B) was obtained based on FIG. 21B. Again the RMS level of the squared quantization error is reduced by the feedback LPF. In this case however, because the additional feedback path can be considered a “short” for DC signals, a systematic error proportional to the ratio K_L/AK_y=K_L/AK_mβ_y² is added to the converter's DC transfer characteristic. The simulated transfer curve and the law-conformance error for this ΣΔ RMS-to-DC converter architecture are shown in FIG. 22 for K_L/K_y=4 and K_L/K_y=16. In the first case, the output DR was greatly enlarged compared to FIG. 9. In the second case however, at low power levels and low V_ref values this improvement is reduced by the systematic error proportional to K_L/K_y. The maximum detectable input power level is also reduced for K_L/K_y=16.

All simulation results presented in FIGS. 18, 19, 20 and 22 were obtained with an ideal integrator model (A=∞). However, the residual DC error in expressions (26A) and (26B) is inversely proportional to the integrator actual finite DC-gain A. FIG. 23 shows the simulated transfer curves and the law-conformance error for K_L/K_y=4 and A=100 dB, 80 dB or 60 dB.

As predicted by expressions (26A) and (26B), the output DR is maximized for A→∞. For low values of A the systematic DC component, not the quantization error mean square value, is the dominant error source in the law conformance error plots.

The ΣΔ RMS-to-DC converter architecture depicted in FIGS. 17, 21A and 21B can be generalized in order to have multiple feedback paths and N^th-order lowpass filtering in the low-frequency path connected to the squaring non-linearity. The small-signal AC model illustrating this situation is depicted in FIG. 24.

When the coefficients K_Li are equal to K_qω₁τ_P, the feedback loop filter transfer function L₁(s) for the architecture in FIG. 24 is the same as obtained with the architecture in FIG. 16. In this case, expressions (18) to (21) are equally valid for the architecture with multiple lowpass filtered feedback paths as the resulting loop filter transfer function L₁(s) converges to a 1^st-order loop filter when k≦K_Li/ω₁τ_P and τ_P is large enough. As a result, the closed loop system can be designed to be conditionally stable for a certain range of input power levels (k∝x_RMS).

FIGS. 25A and 25B show the main possible implementations of a ΣΔ difference-of-squares RMS-to-DC converter based on the linearized closed loop system in FIG. 24. Equivalent implementations can be achieved when multiple separated sets of feedback DAC/LPF are employed and/or the LPFs are implemented in the digital domain.

Based on the relation between y(t), x(t) and u(t), the large-signal static transfer of the ΣΔ difference-of-squares RMS-to-DC converters in FIGS. 25A/25B can be calculated:

$\begin{array}{cc}{y}_{\mathrm{DC}}=\frac{-\left(1+N·K_L\right)}{2{\mathrm{AK}}_y}+\sqrt{{\left(\frac{1+N·K_L}{2{\mathrm{AK}}_y}\right)}^2+\frac{K_x}{K_y}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lpN}}\left(t\right)}^2}}& \left(27A\right)\\ y_{\mathrm{DC}}=\frac{-\left(1+N·K_L\right)}{2{\mathrm{AK}}_m{\beta }_y^2}+\sqrt{{\left(\frac{1+N·K_L}{2{\mathrm{AK}}_m{\beta }_y^2}\right)}^2+\frac{{\beta }_x^2}{{\beta }_y^2}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lpN}}\left(t\right)}^2}}& \left(27B\right)\end{array}$ where A is the actual integrator DC-gain, K_L=K_qω₁τ_P, q_lpN(t)=y_lpN(t)−y_DC is the N^th-order lowpass filtered quantization noise error, expression (27A) was obtained based on FIG. 25A and expression (27B) was obtained based on FIG. 25B. The DC solution obtained for the generalized architecture is very similar to the case where a single 1^st-order LPF is employed (FIGS. 21A/21B), with two major differences. First, the quantization error mean-square value is attenuated by an N^th-order LPF. Second, a residual systematic error proportional to the ratio NK_L/AK_y=NK_L/AK_mβ_y² is added to the converter's DC transfer characteristic. Therefore, a trade-off exists between the reduction of the quantization error mean-square value and the increase of the residual systematic error.

All architectures described above can be implemented with multiple integrators. In this case however, the ΣΔ RMS-to-DC converter's forward path also needs to be stabilized with high-frequency zeros. Several architectures are described herein where the frequency compensation is implemented with multiple forward paths.

The feedforward compensated loop filter can be combined with lowpass and highpass filtered feedback paths, or with lowpass filtered and constant-gain feedback paths. FIGS. 26A and 26B illustrate the main possible implementations based on this concept. Equivalent implementations can be achieved when more than two integrators are employed, the highpass filtered feedback path is replaced by a constant-gain (K_c) path, two separated feedback DACs are employed and/or the LPF and HPF are implemented in the digital domain.

Based on the relation between y(t), x(t) and u(t), the large-signal static transfer of the ΣΔ difference-of-squares RMS-to-DC converters in FIGS. 26A/26B can be calculated:

$\begin{array}{cc}{y}_{\mathrm{DC}}=\frac{-1}{2A_{\mathrm{FF}}{K}_y}+\sqrt{{\left(\frac{1}{2A_{\mathrm{FF}}{K}_y}\right)}^2+\frac{K_x}{K_y}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(28A\right)\\ y_{\mathrm{DC}}=\frac{-1}{2A_{\mathrm{FF}}{K}_m{\beta }_y^2}+\sqrt{{\left(\frac{1}{2A_{\mathrm{FF}}{K}_m{\beta }_y^2}\right)}^2+\frac{{\beta }_x^2}{{\beta }_y^2}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(28B\right)\\ A_{\mathrm{FF}}=A_1\left(a_1+a_2{A}_2\right)& \left(29\right)\end{array}$ where A_FF is the combined DC-gain of the integrators stabilized with feedforward paths, A₁ is the actual DC-gain of the 1^st-integrator, A₂ is the actual DC-gain of the 2^nd-integrator, a_i are the feedforward coefficients, q_lp(t)=y_lp(t)−y_DC is the lowpass filtered quantization noise error, expression (28A) was obtained based on FIG. 26A and expression (28B) was obtained based on FIG. 26B. The main advantage of employing multiple integrators in the feedforward path is to increase the attenuation of the systematic component in expressions (28A)/(28B).

FIG. 27 shows the generalized AC small-signal model for the architecture depicted in FIGS. 26A/26B. This closed loop system with L integrators and N^th-order feedback LPF/HPF is characterized by a (L+N)^th-order noise shaping.

Based on FIG. 27, the signal-dependent feedback loop filter L₁(s) can be expressed again:

$\begin{array}{cc}{L}_1\left(s\right)=\frac{U\left(s\right)}{Y\left(s\right)}=-\left(\frac{s^{L-1}{a}_1{\omega }_1+s^{L-2}{a}_2{\omega }_2{\omega }_1+\dots +a_L\prod _{i=1}^L{\omega }_i}{s^L}\right)·\left(\frac{k+K_q·{\left(s{\tau }_P+1\right)}^N-K_q}{{\left(s{\tau }_P+1\right)}^N}\right)& \left(30\right)\end{array}$

The resulting loop filter transfer function L₁(s) converges to an L^th-order stable loop filter when k≦K_q. As a result, the closed loop system can be designed to be conditionally stable for a certain range of input power levels (k∝x_RMS). The LPF/HPF transfer functions, depicted as N^th-order binomials in FIG. 27, can be implemented with any different set of coefficients (e.g. Butterworth, Chebyshev, etc. . . . ) and with different cut-off frequencies (f_cHPF≠f_cLPF) at the expense of a less stable closed loop behavior.

The feedforward compensated loop filter can be combined with multiple lowpass filtered feedback paths. FIGS. 28A and 28B illustrate the main possible implementations based on this concept. Equivalent implementations can be achieved when more than two integrators are employed, more than two LPFs are employed, multiple feedback DACs are employed and/or the LPFs are implemented in the digital domain.

Based on the relation between y(t), x(t) and u(t), the large-signal static transfer of the ΣΔ difference-of-squares RMS-to-DC converters in FIGS. 28A/28B can be calculated:

$\begin{array}{cc}{y}_{\mathrm{DC}}=\frac{-\left(\frac{1}{A_{\mathrm{FF}}}+\frac{K_{L1}+K_{L2}}{A_1}\right)}{2K_y}+\sqrt{\frac{{\left(\frac{1}{A_{\mathrm{FF}}}+\frac{K_{L1}+K_{L2}}{A_1}\right)}^2}{4K_y^2}+\frac{K_x}{K_y}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}2}\left(t\right)}^2}}& \left(31A\right)\\ y_{\mathrm{DC}}=\frac{-\left(\frac{1}{A_{\mathrm{FF}}}+\frac{K_{L1}+K_{L2}}{A_1}\right)}{2K_m{\beta }_y^2}+\sqrt{\frac{{\left(\frac{1}{A_{\mathrm{FF}}}+\frac{K_{L1}+K_{L2}}{A_1}\right)}^2}{4K_m^2{\beta }_y^4}+\frac{{\beta }_x^2}{{\beta }_y^2}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}2}\left(t\right)}^2}}& \left(31B\right)\end{array}$ where A_FF is the combined DC-gain of the integrators stabilized with feedforward paths, A₁ is the actual DC-gain of the 1^st-integrator, q_lp2(t)=y_lp2(t)−y_DC is the lowpass filtered quantization noise error, expression (31A) was obtained based on FIG. 28A and expression (31B) was obtained based on FIG. 28B. Besides the fact that this architecture can employ multiple integrators in the feedforward path, the systematic error component proportional to K_L1+K_L2 ( . . . +K_LN) is only attenuated by the gain A₁ of the 1^st-integrator.

FIG. 29 shows the generalized AC small-signal model for the architecture depicted in FIGS. 28A/28B. This closed loop system with L integrators and N^th-order feedback LPF is characterized by a (L+N)^th-order noise shaping.

When the coefficients K_Li are equal to K_qω₁τ_P, the feedback loop filter transfer function L₁(s) for the architecture in FIG. 29 is the same as obtained with the architecture in FIG. 27. In this case, expression (30) is equally valid for the architecture with multiple lowpass filtered feedback paths and the resulting loop filter transfer function L₁(s) converges to an L^th-order loop filter when k≦K_Li/ω₁τ_P. As a result, the closed loop system can be designed to be conditionally stable for a certain range of input power levels (k∝x_RMS).

All architectures described above can be implemented with multiple integrators. In this case however, the ΣΔ RMS-to-DC converter's forward path also needs to be stabilized with high frequency zeros. Several architectures are described herein where the frequency compensation is implemented with multiple feedback paths. The basic L^th-order feedback-compensated ΣΔ RMS-to-DC converter is depicted in FIGS. 30A/30B. In order to decrease the quantization noise power being squared, a LPF or a pole-zero filter can be placed before the feedback squaring non-linearity (as in FIGS. 3A/3B).

Based on the relation between y(t), x(t) and u(t), the large-signal static transfer of the ΣΔ difference-of-squares RMS-to-DC converters in FIGS. 30A/30B can be calculated:

$\begin{array}{cc}{y}_{\mathrm{DC}}=\frac{-\left(1+b_{L-1}{A}_L+\dots +b_1\prod _{i=2}^L{A}_i\right)}{2A_{\mathrm{FB}}{K}_y}+\sqrt{{\left(\frac{1+b_{L-1}{A}_L+\dots +b_1\prod _{i=2}^L{A}_i}{2A_{\mathrm{FB}}{K}_y}\right)}^2+\frac{K_x}{K_y}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q\left(t\right)}^2}}& \left(32A\right)\\ y_{\mathrm{DC}}=\frac{-\left(1+b_{L-1}{A}_L+\dots +b_1\prod _{i=2}^L{A}_i\right)}{2A_{\mathrm{FB}}{K}_m{\beta }_y^2}+\sqrt{{\left(\frac{1+b_{L-1}{A}_L+\dots +b_1\prod _{i=2}^L{A}_i}{2A_{\mathrm{FB}}{K}_m{\beta }_y^2}\right)}^2+\frac{{\beta }_x^2}{{\beta }_y^2}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q\left(t\right)}^2}}& \left(32B\right)\\ A_{\mathrm{FB}}=A_1·A_2·\dots ·A_L& \left(33\right)\end{array}$ where A_FB is the product of all integrators' DC-gains, A_i is the actual DC-gain of the i_th-integrator and b_i are the feedback coefficients. In this architecture, corresponds to each additional integrator a component of the residual systematic error due to the required feedback path. The systematic error due to the l^th integrator (l>1) is given by:

$\begin{array}{cc}\frac{b_{l-1}\prod _{j=l}^L{A}_l}{2A_{\mathrm{FB}}{K}_y}=\frac{b_{l-1}\prod _{j=l}^L{A}_l}{2A_{\mathrm{FB}}{K}_m{\beta }_y^2}& \left(34\right)\end{array}$

The feedback compensated loop filter can be combined with lowpass and highpass filtered feedback paths, or with lowpass filtered and constant-gain feedback paths. FIGS. 31A and 31B illustrate the main possible implementations based on this concept. Equivalent implementations can be achieved when more than two integrators are employed, the highpass filtered feedback path is replaced by a constant-gain (K_c) path, two separated feedback DACs are employed and/or the LPF and HPF are implemented in the digital domain.

Based on the relation between y(t), x(t) and u(t), the large-signal static transfer of the ΣΔ difference-of-squares RMS-to-DC converters in FIGS. 31A/31B can be calculated:

$\begin{array}{cc}{y}_{\mathrm{DC}}=\frac{-\left(1+A_2{b}_1\right)}{2A_{\mathrm{FB}}{K}_y}+\sqrt{{\left(\frac{1+A_2{b}_1}{2A_{\mathrm{FB}}{K}_y}\right)}^2+\frac{K_x}{K_y}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(35A\right)\\ y_{\mathrm{DC}}=\frac{-\left(1+A_2{b}_1\right)}{2A_{\mathrm{FB}}{K}_m{\beta }_y^2}+\sqrt{{\left(\frac{1+A_2{b}_1}{2A_{\mathrm{FB}}{K}_m{\beta }_y^2}\right)}^2+\frac{{\beta }_x^2}{{\beta }_y^2}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(35B\right)\end{array}$ where A_FB=A₁A₂ is the combined DC-gain of the integrators stabilized with feedback paths, A₁ is the actual DC-gain of the 1^st-integrator, A₂ is the actual DC-gain of the 2^nd-integrator, b₁ and K_q are the feedback coefficients, q_lp(t)=y_lp(t)−y_DC is the lowpass filtered quantization noise error, expression (35A) was obtained based on FIG. 31A and expression (35B) was obtained based on FIG. 31B.

FIG. 32 shows the generalized AC small-signal model for the architecture depicted in FIGS. 31A/31B. This closed loop system with L integrators and N^th-order feedback LPF/HPF is characterized by a (L+N)^th-order noise shaping.

Based on FIG. 32, the signal-dependent feedback loop filter L₁(s) can be expressed again:

$\begin{array}{cc}-L_1\left(s\right)=-\frac{U\left(s\right)}{Y\left(s\right)}=\frac{b_{L-1}{\omega }_L}{s}+\dots +\frac{b_1·\prod _{i=2}^L{\omega }_i}{s^{L-1}}+\frac{\prod _{i=1}^L{\omega }_i}{s^L}\left(\frac{k+K_q·{\left(s{\tau }_P+1\right)}^N-K_q}{{\left(s{\tau }_P+1\right)}^N}\right)& \left(36\right)\end{array}$

The resulting loop filter transfer function L₁(s) converges to an L^th-order stable loop filter when k≦K_q. As a result, the closed loop system can be designed to be conditionally stable for a certain range of input power levels (k∝x_RMS). The LPF/HPF transfer functions, depicted as N^th-order binomials in FIG. 32, can be implemented with any different set of coefficients (e.g. Butterworth, Chebyshev, etc. . . . ) and with different cut-off frequencies (f_cHPF≠f_cLPF) at the expense of a less stable closed loop behavior.

The feedback compensated loop filter can be combined with multiple lowpass filtered feedback paths. FIGS. 33A and 33B illustrate the main possible implementations based on this concept. Equivalent implementations can be achieved when more than two integrators are employed, multiple feedback DACs are employed and/or the LPFs are implemented in the digital domain.

Based on the relation between y(t), x(t) and u(t), the large-signal static transfer of the ΣΔ difference-of-squares RMS-to-DC converters in FIGS. 33A/33B can be calculated:

$\begin{array}{cc}{y}_{\mathrm{DC}}=\frac{-\left(1+K_{L2}+A_2\left(b_1+K_{L1}\right)\right)}{2A_{\mathrm{FB}}{K}_y}+\sqrt{{\left(\frac{1+K_{L2}+A_2\left(b_1+K_{L1}\right)}{2A_{\mathrm{FB}}{K}_y}\right)}^2+\frac{K_x}{K_y}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(37A\right)\\ y_{\mathrm{DC}}=\frac{-\left(1+K_{L2}+A_2\left(b_1+K_{L1}\right)\right)}{2A_{\mathrm{FB}}{K}_m{\beta }_y^2}+\sqrt{{\left(\frac{1+K_{L2}+A_2\left(b_1+K_{L1}\right)}{2A_{\mathrm{FB}}{K}_m{\beta }_y^2}\right)}^2+\frac{{\beta }_x^2}{{\beta }_y^2}\stackrel{\_}{{x\left(t\right)}^2}-\stackrel{\_}{{q_{\mathrm{lp}}\left(t\right)}^2}}& \left(37B\right)\end{array}$ where A_FB=A₁A₂ is the combined DC-gain of the integrators stabilized with feedback paths, A₁ is the actual DC-gain of the 1^st-integrator, A₂ is the actual DC-gain of the 2^nd-integrator, b₁ and K_Lj are the feedback coefficients, q_lp(t)=y_lp(t)−y_DC is the lowpass filtered quantization noise error, expression (37A) was obtained based on FIG. 33A and expression (37B) was obtained based on FIG. 33B. In this architecture, corresponds to each integrator a component of the residual systematic error due to two feedback paths (except the last integrator). The systematic error added after the l^th integrator (l>1) is given by:

$\begin{array}{cc}\frac{\left(K_{L\left(l-1\right)}+b_{l-1}\right)\prod _{j=l}^L{A}_l}{2A_{\mathrm{FB}}{K}_y}=\frac{\left(K_{L\left(l-1\right)}+b_{l-1}\right)\prod _{j=l}^L{A}_l}{2A_{\mathrm{FB}}{K}_m{\beta }_y^2}& \left(38\right)\end{array}$

The major advantage of the architecture depicted in FIGS. 33A/33B compared to the architecture depicted in FIGS. 28A/28B and 25A/25B is the fact that the systematic error contribution due to the feedback coefficient K_Lj is divided by the total DC-gain from all previous integrator (from A₁ to A_j). Therefore, the trade-off between the reduction of the quantization error mean-square value via feedback filtering and the increase of the residual systematic error due to the additional feedback paths (present on the previous architectures) is greatly reduced.

FIG. 34 shows the generalized AC small-signal model for the architecture depicted in FIGS. 33A/33B. This closed loop system with N integrators and N^th-order feedback LPF is characterized by a 2N^th-order noise shaping.

The feedback loop filter transfer function L₁(s) for the architecture in FIG. 34 is the same as obtained with the architecture in FIG. 32 if L=N and:

$\begin{array}{cc}{K}_{\mathrm{Lj}}=K_q·{\tau }_P^j·\frac{N!}{j!\left(N-j\right)!}·\prod _{i=1}^j{\omega }_i& \left(39\right)\end{array}$

In this case, expression (36) is equally valid for the architecture with multiple lowpass filtered feedback paths and the resulting loop filter transfer function L₁(s) converges to an N^th-order stable loop filter when k≦K_q. As a result, the closed loop system can be designed to be conditionally stable for a certain range of input power levels (k∝x_RMS). The LPF transfer function, depicted as an N^th-order binomial in FIG. 34, can be implemented with any different set of coefficients (e.g. Butterworth, Chebyshev, etc. . . . ) and/or in the digital domain.

All the ΣΔ difference-of-squares RMS-to-DC converter architectures described herein present a conditionally stable behavior. This means that their respective closed-loop systems are only stable for certain range of input power levels. In order to be able to properly operate through a wide range of power levels, some topologies require certain implementation parameters to be optimized according to the order of magnitude of the input signal (e.g. high power levels, intermediate power levels or low power levels). Configurability is especially useful in high-order (L+N>2) ΣΔ RMS-to-DC converters.

The tuning of a ΣΔ RMS-to-DC converter to measure a certain range of input power levels can be achieved through the electronic configuration of any internal parameter of the implementation. FIGS. 35 and 36 depict examples of configurable ΣΔ RMS-to-DC converters. Internal parameters like voltage/current gains, time-constants, transconductances, filter order and cut-off frequency, sampling frequency, reference voltages, etc. . . . can be configured to minimize the law-conformance error and/or to guarantee a stable ΣΔ closed-loop behavior. Furthermore, certain signal-paths can be connected/disconnected (turned on/off) according to the range of power levels to be measured. In a broader sense, all architectures presented herein can be combined with some kind of configurability.

Based on the principle of configurability and on all previous architectures described herein, a general description of a ΣΔ difference-of-squares RMS-to-DC converter is depicted in FIG. 37. Equivalent descriptions can be obtained when a part of the feedback and feedforward filters are implemented in the digital domain or as analog switched circuitry (e.g. switched capacitors), and/or multiple feedback DACs are employed.

All ΣΔ RMS-to-DC converter architectures described herein are fully compatible with the chopper-stabilization techniques presented in U.S. Pat. Nos. 7,545,302 and 7,545,303. For example, a possible electronic implementation of the architecture depicted in FIGS. 21A/21B, where commutators are employed to reduce the effect of DC-offsets in the output DR, is shown in FIG. 38.

Based upon the discussion hereinabove, it can be seen that embodiments of the presently claimed invention provide a number of advantageous features including, without limitation, the following: a ΣΔ difference-of-squares RMS-to-digital converter, based on two squaring cells or a single forward path multiplier, with lowpass filtered and constant gain feedback paths (e.g., as depicted in FIGS. 7A/7B); a ΣΔ difference-of-squares RMS-to-digital converter, based on two squaring cells or a single forward path multiplier, with lowpass and highpass filtered feedback paths (e.g., as depicted in FIGS. 10A/10B); a ΣΔ difference-of-squares RMS-to-digital converter, based on two squaring cells or a single forward path multiplier, with multiple lowpass filtered feedback paths (e.g., as depicted in FIGS. 21A/21B and 25A/25B); a ΣΔ difference-of-squares RMS-to-digital converter with multiple integrators stabilized by additional feedforward paths, based on two squaring cells or a single forward path multiplier, with lowpass filtered and constant gain feedback paths; a ΣΔ difference-of-squares RMS-to-digital converter with multiple integrators stabilized by additional feedforward paths, based on two squaring cells or a single forward path multiplier, with lowpass and highpass filtered feedback paths (e.g., as depicted in FIGS. 26A/26B); a ΣΔ difference-of-squares RMS-to-digital converter with multiple integrators stabilized by additional feedforward paths, based on two squaring cells or a single forward path multiplier, with multiple lowpass filtered feedback paths (e.g., as depicted in FIGS. 28A/28B); a ΣΔ difference-of-squares RMS-to-digital converter with multiple integrators stabilized by additional feedback paths, based on two squaring cells or a single forward path multiplier, with a single feedback path where no-filtering is employed (e.g., as depicted in FIGS. 30A/30B); a ΣΔ difference-of-squares RMS-to-digital converter with multiple integrators stabilized by additional feedback paths, based on two squaring cells or a single forward path multiplier, with a single feedback path where a LPF or Pole-Zero filter is employed; a ΣΔ difference-of-squares RMS-to-digital converter with multiple integrators stabilized by additional feedback paths, based on two squaring cells or a single forward path multiplier, with lowpass filtered and constant gain feedback paths; a ΣΔ difference-of-squares RMS-to-digital converter with multiple integrators stabilized by additional feedback paths, based on two squaring cells or a single forward path multiplier, with lowpass and highpass filtered feedback paths (e.g., as depicted in FIGS. 31A/31B); a ΣΔ difference-of-squares RMS-to-digital converter with multiple integrators stabilized by additional feedback paths, based on two squaring cells or a single forward path multiplier, with multiple lowpass filtered feedback paths (e.g., as depicted in FIGS. 33A/33B); a ΣΔ difference-of-squares RMS-to-digital converter with electronically configurable parameters (e.g., as depicted in FIGS. 35, 36 and 37); and a ΣΔ difference-of-squares RMS-to-digital converter employing chopper-stabilization (e.g., as depicted in FIG. 38) as described in U.S. Pat. Nos. 7,545,302 and 7,545,303.

Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.

Claims

1. An apparatus including a sigma-delta difference-of-squares RMS-to-DC converter, comprising: analog signal multiplication and combining circuitry responsive to an analog input signal and at least first and second analog feedback signals by providing a resultant analog signal that includes at least one signal component corresponding to a difference between a square of said analog input signal, a square of said first analog feedback signal and said second analog feedback signal;analog signal filter circuitry coupled to said analog signal multiplication and combining circuitry, and responsive to said resultant analog signal by providing a filtered analog signal;analog-to-digital conversion (ADC) circuitry coupled to said analog signal filter circuitry and responsive to said filtered analog signal by providing a related digital output signal;digital-to-analog conversion (DAC) circuitry coupled to said ADC circuitry and responsive to said digital output signal by providing an analog signal;first feedback circuitry coupled between said DAC circuitry and said analog signal multiplication and combining circuitry, and responsive to said analog signal by providing said first analog feedback signal; andsecond feedback circuitry coupled between said DAC circuitry and said analog signal multiplication and combining circuitry, and responsive to said analog signal by providing said second analog feedback signal.

2. The apparatus of claim 1, wherein said analog signal multiplication and combining circuitry comprises: first analog signal multiplication circuitry responsive to said analog input signal by providing a first analog product signal;second analog signal multiplication circuitry responsive to said first analog feedback signal by providing a second analog product signal; andanalog signal combining circuitry coupled to said first and second analog signal multiplication circuitries, and responsive to said first and second analog product signals and said second analog feedback signal by providing said resultant analog signal.

3. The apparatus of claim 1, wherein said analog signal multiplication and combining circuitry comprises: analog input signal router circuitry responsive to an analog input signal by providing first and second routed analog input signals related to said analog input signal;analog feedback signal router circuitry responsive to said first analog feedback signal by providing first and second routed analog feedback signals related to said first analog feedback signal;first analog signal combining circuitry coupled to said analog input signal router circuitry and said analog feedback signal router circuitry, and responsive to said first and second routed analog input signals and said first and second routed analog feedback signals by providing first and second combined analog signals related to combinations of said first routed analog input and feedback signals and said second routed analog input and feedback signals, respectively;analog signal multiplication circuitry coupled to said first analog signal combining circuitry and responsive to said first and second combined analog signals by providing an analog product signal that includes at least one signal component corresponding to a difference between a product of said first and second routed analog input signals and a product of said first and second routed analog feedback signals; andsecond analog signal combining circuitry coupled to said analog signal multiplication circuitry and responsive to said analog product signal and said second analog feedback signal by providing said resultant analog signal.

4. The apparatus of claim 1, wherein said analog signal filter circuitry comprises: first filter circuitry responsive to said resultant analog signal by providing a first intermediate signal;second filter circuitry coupled to said first filter circuitry and responsive to said first filtered signal by providing a second intermediate signal;scaling circuitry coupled to said first filter circuitry and responsive to said first intermediate signal by providing a third intermediate signal; andanalog signal combining circuitry coupled to said second filter circuitry and said scaling circuitry, and responsive to said second and third intermediate signals by providing said filtered analog signal.

5. The apparatus of claim 1, further comprising third feedback circuitry coupled between said DAC circuitry and said analog signal filter circuitry, and responsive to said analog signal by providing a third analog feedback signal, wherein said analog signal filter circuitry includes: first filter circuitry responsive to said resultant analog signal by providing an intermediate filtered signal;analog signal combining circuitry coupled to said first filter circuitry and said third feedback circuitry, and responsive to said intermediate filtered signal and said third analog feedback signal by providing a combined analog signal; andsecond filter circuitry coupled to said analog signal combining circuitry and responsive to said combined analog signal by providing said filtered analog signal.

6. The apparatus of claim 1, wherein said first feedback circuitry comprises signal filtering circuitry.

7. The apparatus of claim 1, wherein said second feedback circuitry comprises signal scaling circuitry.

8. The apparatus of claim 7, wherein said second feedback circuitry further comprises signal filtering circuitry serially coupled with said signal scaling circuitry.

9. The apparatus of claim 8, wherein said analog signal filter circuitry comprises: first filter circuitry responsive to said resultant analog signal by providing a first intermediate signal;second filter circuitry coupled to said first filter circuitry and responsive to said first filtered signal by providing a second intermediate signal;scaling circuitry coupled to said first filter circuitry and responsive to said first intermediate signal by providing a third intermediate signal; andanalog signal combining circuitry coupled to said second filter circuitry and said scaling circuitry, and responsive to said second and third intermediate signals by providing said filtered analog signal.

10. The apparatus of claim 8, further comprising third feedback circuitry coupled between said DAC circuitry and said analog signal filter circuitry, and responsive to said analog signal by providing a third analog feedback signal, wherein said analog signal filter circuitry includes: first filter circuitry responsive to said resultant analog signal by providing an intermediate filtered signal;analog signal combining circuitry coupled to said first filter circuitry and said third feedback circuitry, and responsive to said intermediate filtered signal and said third analog feedback signal by providing a combined analog signal; andsecond filter circuitry coupled to said analog signal combining circuitry and responsive to said combined analog signal by providing said filtered analog signal.

11. An apparatus including a sigma-delta difference-of-squares RMS-to-DC converter, comprising: analog signal multiplier and combiner means for multiplying and combining an analog input signal and at least first and second analog feedback signals to provide a resultant analog signal that includes at least one signal component corresponding to a difference between a square of said analog input signal, a square of said first analog feedback signal and said second analog feedback signal;analog signal filter means for filtering said resultant analog signal to provide a filtered analog signal;analog-to-digital converter (ADC) means for converting said filtered analog signal to a related digital output signal;digital-to-analog converter (DAC) means for converting said digital output signal to an analog signal;first feedback means for processing said analog signal to provide said first analog feedback signal; andsecond feedback means for processing said analog signal to provide said second analog feedback signal.

12. A method for performing a sigma-delta difference-of-squares RMS-to-DC conversion, comprising: multiplying and combining an analog input signal and at least first and second analog feedback signals to provide a resultant analog signal that includes at least one signal component corresponding to a difference between a square of said analog input signal, a square of said first analog feedback signal and said second analog feedback signal;filtering said resultant analog signal to provide a filtered analog signal;converting said filtered analog signal to a related digital output signal;converting said digital output signal to an analog signal;processing said analog signal to provide said first analog feedback signal; andprocessing said analog signal to provide said second analog feedback signal.

13. An apparatus including a sigma-delta difference-of-squares RMS-to-DC converter, comprising: analog signal multiplication and combining circuitry responsive to an analog input signal and a first analog feedback signal by providing a resultant analog signal that includes at least one signal component corresponding to a difference between a square of said analog input signal and a square of said first analog feedback signal;analog signal filtering and combining circuitry coupled to said analog signal multiplication and combining circuitry, and responsive to said resultant analog signal and at least a second analog feedback signal by providing a feedforward signal;analog-to-digital conversion (ADC) circuitry coupled to said analog signal filtering and combining circuitry and responsive to said feedforward signal by providing a related digital output signal; andfeedback circuitry, including digital-to-analog conversion (DAC) circuitry, coupled between said ADC circuitry, said analog signal multiplication and combining circuitry and said analog signal combining circuitry, and responsive to said digital output signal by providing said first analog feedback signal and said at least a second analog feedback signal.

14. The apparatus of claim 13, wherein: said analog signal filtering and combining circuitry comprises forward signal filtering circuitry responsive to said resultant analog signal by providing a filtered analog signal, andanalog signal combining circuitry coupled to said analog signal filtering circuitry and responsive to said filtered analog signal and said second analog feedback signal by providing a combined analog signal as said feedforward signal; andsaid feedback circuitry comprises said DAC circuitry, responsive to said digital output signal by providing an analog signal,feedback signal filtering circuitry coupled to said DAC circuitry and responsive to said analog signal by providing a filtered analog signal as said first analog feedback signal, andfeedback signal scaling circuitry coupled to said feedback signal filtering circuitry and responsive to said first analog feedback signal by providing said second analog feedback signal.

15. The apparatus of claim 13, wherein said at least a second analog feedback signal comprises at least second and third analog feedback signals, and said feedback circuitry comprises: said DAC circuitry, responsive to said digital output signal by providing an analog signal;feedback signal filtering circuitry coupled to said DAC circuitry and responsive to said analog signal by providing a plurality of successively filtered analog signals, wherein one of said successively filtered analog signals is provided as said first analog feedback signal; andfeedback signal scaling circuitry coupled to said feedback signal filtering circuitry and responsive to at least a portion of said plurality of successively filtered analog signals by providing said at least second and third analog feedback signals.

16. The apparatus of claim 15, wherein: a first portion of said analog signal filtering and combining circuitry comprises a first analog signal filter circuit responsive to said resultant analog signal by providing a first filtered analog signal;a second portion of said analog signal filtering and combining circuitry comprises a first analog signal combining circuit coupled to said first analog signal filter circuit and responsive to said first filtered analog signal and said at least a second analog feedback signal by providing a first combined analog signal;a third portion of said analog signal filtering and combining circuitry comprises a second analog signal filter circuit coupled to said first analog signal combining circuit and responsive to said first combined analog signal by providing a second filtered analog signal;a fourth portion of said analog signal filtering and combining circuitry comprises forward signal scaling circuitry coupled to said first analog signal combining circuit and responsive to said first combined analog signal by providing a forward scaled signal; anda fifth portion of said analog signal filtering and combining circuitry comprises a second analog signal combining circuit coupled to said second analog signal filter circuit and said forward signal scaling circuitry, and responsive to said second filtered analog signal and said forward scaled signal by providing a second combined analog signal as said feedforward signal.

17. The apparatus of claim 13, wherein: said at least a second analog feedback signal comprises a plurality of analog feedback signals;said feedback circuitry comprises said DAC circuitry, responsive to said digital output signal by providing said first analog feedback signal, andfeedback signal scaling circuitry coupled to said DAC circuitry and responsive to said first analog feedback signal by providing said plurality of analog feedback signals; andsaid analog signal filtering and combining circuitry comprises a plurality of analog signal filter circuits and a plurality of analog signal combining circuits mutually coupled in an alternating manner, and responsive to said resultant analog signal and said plurality of analog feedback signals by successively filtering upstream signals and combining respective ones of said filtered upstream signals with respective ones of said plurality of analog feedback signals to provide said feedforward signal.

18. The apparatus of claim 13, wherein: said at least a second analog feedback signal comprises second, third and fourth analog feedback signals;said feedback circuitry comprises said DAC circuitry, responsive to said digital output signal by providing an analog signal,feedback signal filtering circuitry coupled to said DAC circuitry and responsive to said analog signal by providing a filtered analog signal as said first analog feedback signal,first feedback signal scaling circuitry coupled to said DAC circuitry and responsive to said analog signal by providing said second analog feedback signal,second feedback signal scaling circuitry coupled to said feedback signal filtering circuitry and responsive to said first analog feedback signal by providing said third analog feedback signal, andthird feedback signal scaling circuitry coupled to said feedback signal filtering circuitry and responsive to said first analog feedback signal by providing said fourth analog feedback signal;a first portion of said analog signal filtering and combining circuitry comprises a first analog signal filter circuit responsive to said resultant analog signal by providing a first filtered analog signal;a second portion of said analog signal filtering and combining circuitry comprises a first analog signal combining circuit coupled to said first analog signal filter circuit and responsive to said first filtered analog signal and said second and third analog feedback signals by providing a first combined analog signal;a third portion of said analog signal filtering and combining circuitry comprises a second analog signal filter circuit coupled to said first analog signal combining circuit and responsive to said first combined analog signal by providing a second filtered analog signal; anda fourth portion of said analog signal filtering and combining circuitry comprises a second analog signal combining circuit coupled to said second analog signal filter circuit and responsive to said second filtered analog signal and said fourth analog feedback signal by providing a second combined analog signal as said feedforward signal.

19. An apparatus including a sigma-delta difference-of-squares RMS-to-DC converter, comprising: analog signal multiplier and combiner means for multiplying and combining an analog input signal and a first analog feedback signal to provide a resultant analog signal that includes at least one signal component corresponding to a difference between a square of said analog input signal and a square of said first analog feedback signal;analog signal filter and combiner means for filtering and combining said resultant analog signal and at least a second analog feedback signal to provide a feedforward signal;analog-to-digital converter (ADC) means for converting said feedforward signal to a related digital output signal; andfeedback means, including digital-to-analog converter (DAC) means, for converting said digital output signal to said first analog feedback signal and said at least a second analog feedback signal.

20. A method for performing a sigma-delta difference-of-squares RMS-to-DC conversion, comprising: multiplying and combining an analog input signal and a first analog feedback signal to provide a resultant analog signal that includes at least one signal component corresponding to a difference between a square of said analog input signal and a square of said first analog feedback signal;filtering and combining said resultant analog signal and at least a second analog feedback signal to provide a feedforward signal;converting said feedforward signal to a related digital output signal; andconverting said digital output signal to said first analog feedback signal and said at least a second analog feedback signal.