0.6-2.5 GBaud CMOS tracked 3X oversampling transceiver with dead zone phase detection for robust clock/data recovery

Abstract

For generation of the multiphase clocks for a serializer, a wide-range multiphase delay-locked loop (DLL) is used in the transmitter to avoid the detrimental characteristics of a phase-locked loop (PLL), such as jitter peaking and accumulated phase error. A tracked 3× oversampling technique with dead-zone phase detection is incorporated in the receiver for robust clock/data recovery in the presence of excessive jitter and inter-symbol interference (ISI). Due to the dead-zone phase detection, phase adjustment is performed only on the tail portions of the transition histogram in the received data eye, thereby exhibiting wide pumping-current range, large jitter tolerance, and small phase error. A voltage-controlled oscillator (VCO), based on a folded starved inverter, shows about 50% less jitter than one with replica bias. The transceiver, implemented in 0.25 μm CMOS technology, operates at 2.5 GBaud over a 10-m 150-Ω STP cable and at 1.25 GBaud over a 25-m cable with a bit error rate (BER) of less than 10−13.

Description

FIELD OF THE INVENTION

[0002] The present invention relates to the field of data communications. In particular the present invention discloses methods and circuits for robust data recovery on a high-speed serial data link.

BACKGROUND OF THE INVENTION

[0003] Considerable research effort has focused on implementing the physical layers of Gigabit Ethernet, Fibre Channel, IEEE1394, network switch, etc. The major goal is to give the physical layer a high bandwidth transmission for digital data over a long cable with a low bit error rate (BER). As more transceivers operate at higher frequencies and over longer cables, the signal frequencies tend to come close to the channel bandwidth. Bandwidth limitation in the channel causes signal degradation, in the form of inter-symbol interference (ISI), as shown in FIG. 1. Signal degradation shows up in the eye diagram as eye-closure: the center of the eye is smaller in both time and signal amplitude. Eye-closure causes higher BER since it restricts successful data-detection to a smaller time interval.

[0004] According to IEEE std 802.3z, Gigabit Ethernet standard, the receiver shall operate if the total jitter of data transition is less than 71% of the bit time, where deterministic jitter takes up 45% and random jitter, 26%. Deterministic jitter is also referred to as systematic jitter and is caused mostly by ISI and duty-cycle distortion. Random jitter is also referred to as nonsystematic jitter and is generated by a number of noise sources such as thermal noise, power supply noise, substrate noise, etc. Random jitter is Gaussian in nature, while deterministic jitter is due to non-Gaussian events as shown in FIG. 1(b).

[0005] Random jitter is generated in both the transmitter and receiver. A transmitter clock is generated by a transmitter-side PLL or DLL. Since this clock switches the serializer, the outgoing data stream inherits the jitter component of the PLL- or DLL-generated clock. The receiver clock samples the data with its own jitter component. Thus, the equivalent jitter is the sum of both jitter components. As the transceiver operates at higher frequencies and the bit time becomes shorter, the random jitter will occupy a greater portion of the bit time and then the eye opening will narrow. Therefore, for a lower BER, jitter should be reduced in both the transmitter and receiver as the frequency increases.

[0006] In general, a clock recovery circuit takes a sequence of times at which a transition edge of a pulse crosses some threshold voltage and averages the times to extract the real input pulse timing. This averaging process makes the clock recovery circuit tolerant to input jitter. Jitter tolerance is a very critical requirement for clock recovery circuits. With the same circuit and process the jitter tolerance will be dependent on the transceiver architecture.

[0007] Currently, many transceivers are designed to be a macro-cell of an ASIC standard cell library as well as a stand-alone component. Thus, both small area and low power consumption become essential in the transceiver design. In order to measure the BER of a transceiver in an operating frequency, a test board with a small number of field programmable gate array (FPGA) chips is required. The FPGA in the transmitter side generates an appropriate bit sequence, and that in the receiver monitors the sequence and measures the BER. If built-in self-test (BIST) capability is included on chip, this will take the place of the FPGAs. The BIST can lower the test cost and cover the entire frequency range of the transceiver. As mentioned above, when designing a high-speed transceiver with a low BER, jitter reduction and jitter tolerance of the architecture are the most important design issues. Low power consumption, small chip area, and testability are also design concerns.

SUMMARY OF THE INVENTION

[0008] An apparatus, in accordance with an embodiment of the present invention, includes means for generating a data sampling clock signal and means for using the data sampling clock signal to sample a data signal into sampled data representing a first zone, a second zone, and a third zone of the data signal. Means are used for determining which zone of the sampled data has a transition of the data signal. Means are also used for indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition.

[0009] A folded starved inverter differential output apparatus for use in a voltage controlled oscillator, in accordance with another embodiment of the present invention, includes a first polarity of two transistors cross-coupled and a second polarity of four transistors. Also included are two inverter gates and a supply regulator.

[0010] A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit, in accordance with a final embodiment of the present invention, includes a reference loop circuit; wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than 1000 parts per million. Also included is a data loop circuit; wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than 200 parts per million.

[0011] These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following detailed descriptions and a study of the various figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIGS. 1A and 1B are prior art eye diagrams of serial data before and after transmission over a cable link.

[0013] FIG. 2 is a schematic diagram of a transmitter architecture, in accordance with the prior art.

[0014] FIG. 3A is a block diagram of a prior art wide-range multiphase delay locked loop.

[0015] FIG. 3B is a block diagram of a wide-range multiphase delay locked loop, in accordance with the present invention.

[0016] FIG. 4A is a block diagram of a coarse phase detector, in accordance with the present invention.

[0017] FIG. 4B is a block diagram of a skewed current phase detector, in accordance with the present invention.

[0018] FIG. 4C is a timing diagram of the skewed current phase detector, in accordance with the present invention.

[0019] FIG. 5 is a block diagram of a wide range multiphase DLL, in accordance with the present invention.

[0020] FIG. 6 is a block diagram of a receiver architecture, in accordance with the present invention.

[0021] FIG. 7A is an eye diagram of a prior art tracked 2× oversampling receiver.

[0022] FIG. 7B is an eye diagram of a tracked 3× oversampling receiver, in accordance with the present invention.

[0023] FIGS. 8A and 8B are an analysis of bit error rate for three different phase detection types.

[0024] FIGS. 9A and 9B are a comparison pumping current range between 2× and 3× oversampling receivers.

[0025] FIG. 10A is a prior art asymmetric jitter histogram of a 2× oversampling receiver.

[0026] FIG. 10B is an asymmetric jitter histogram of a 3× oversampling receiver, in accordance with the present invention.

[0027] FIG. 11A is a prior art timing diagram of a 2× oversampling receiver in an ISI environment.

[0028] FIG. 11B is a timing diagram of a 3× oversampling receiver in an ISI environment, in accordance with the present invention.

[0029] FIG. 12A is a graph of accumulated phase errors for a 3× oversampling receiver with 20 microamperes of pumping current, in accordance with the present invention.

[0030] FIG. 12B is a prior art graph of accumulated phase errors for a 2× oversampling receiver with 20 microamperes of pumping current.

[0031] FIG. 12C is a graph of accumulated phase errors for a 3× oversampling receiver with 60 microamperes of pumping current, in accordance with the present invention.

[0032] FIG. 13 is a block diagram if a frequency comparator with hysteresis, in accordance with the present invention.

[0033] FIG. 14 is a block diagram of a voltage controlled oscillator, in accordance with the persent invention.

[0034] FIG. 15 is an example layout of various aspects of the present invention.

[0035] FIG. 16A is a jitter histogram of a DLL clock, in accordance with the present invention.

[0036] FIG. 16B is a jitter histogram of a PLL clock, in accordance with the present invention.

[0037] FIG. 17A is an eye diagram of serial data before a 25-meter cable link.

[0038] FIG. 17B is an eye diagram of serial data after a 25-meter cable link, utilizing the present invention.

[0039] FIG. 17C is a jitter histogram of recovered clock data, in accordance with the present invention.

[0040] FIG. 18A is an eye diagram of serial data before a 10-meter cable link.

[0041] FIG. 18B is an eye diagram of serial data after a 10-meter cable link, utilizing the present invention.

[0042] FIG. 18C is a jitter histogram of recovered clock data, in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

Transmitter Architecture

[0043] The proposed transmitter incorporates a voltage-mode driver, a serializer, an analog multiphase delay-locked loop (DLL), and a pseudo-random binary sequence (PRBS) generator for BIST as shown in FIG. 2. Unlike a conventional current-mode driver, where only pull-down current is provided, the voltage-mode driver offers both active pull-up and pull-down, which makes it possible to maintain its high speed in the presence of parasitic capacitance associated with bonding pads and ESD protection diodes, regardless of cable impedance. Furthermore, the driver can be AC-coupled to a cable without additional load resistors. When the BIST is enabled, the PRBS generator provides DC-balanced 10-bit data at every reference clock cycle with a maximum run length of 6. A special character is periodically inserted for the synchronization with a remote receiver.

[0044] In the transmitter section, multiphase clocks are required to drive the serializer. In conventional transceivers where two PLLs are used, one in each of the transmitter and receiver, if both PLL bandwidths were identical, jitter peaking at the bandwidth would grow, rather than be suppressed. Since the transmitter requires only multiphase clock generation, but neither clock recovery nor frequency synthesis, a DLL can be used rather than a PLL. A DLL has a flat jitter transfer function and the aforementioned jitter peaking problem can be avoided. In addition, a DLL is typically smaller and requires less power than the equivalent PLL.

[0045] A. Wide-Range Multiphase Delay-Locked Loop

[0046] Since a conventional DLL adjusts only phase, not frequency, the operating frequency range is severely limited and the DLL is prone to stick or lock to an undesired delay time, which is called as stuck and harmonic lock problems and analyzed in in detail. Thus, when designing a wide-range multiphase DLL, careful consideration is required to avoid these problems. While other wide-range DLLs use phase mixers or phase selections to generate a single clock output, the DLL in uses a multistage voltage-controlled delay line (VCDL) similar to those used by conventional DLLs. Therefore, the DLL can generate multiphase clocks without using an excessive amount of hardware. In, delay cells are controlled by two lines as shown in FIG. 3(a). A replica delay line generates a control voltage, Vcr, to prevent false locking to harmonics and sets the delay range of the delay cells. However, since the delay range is limited by a bias voltage, bias, the DLL exhibits only a 4× operating range. A new DLL architecture is proposed to increase the operating range.

[0047] A VCDL, consisting of ten delay cells, generates ten clock outputs, as shown in FIG. 3(b). It uses one merged control voltage, Vc. In general, the initial delay time of a VCDL could be out of lock range. Therefore, at first, a coarse phase detector forces the delay time towards the lock range. The coarse phase detector takes a reference clock (Ref-CLK), CLK0, and CLK1 as the inputs, but not CLK9. After the delay time is placed within the lock range, the control is transferred from the coarse phase detector to a fine phase detector. At this time, the signal glock activates the fine phase detector. Then, the fine phase detector removes the residual phase error between Ref-CLK and CLK9.

[0048] For the fine phase detector not to fall prey to the stuck problem, the delay time of the VCDL, TVCDL should satisfy the following inequality:

0.5×TCLK<TVCDL<1.5×TCLK,  (1)

[0049] where TCLK is the period of the reference clock. However, the range of TVCDL, is generally wider than this constraint and the initial value of TVCDL is not known at start-up. To place the initial TVCDL within this range (1), the coarse phase detector, consisting of two skewed-current phase detectors (SCPDs), is used as shown in FIG. 4(a). The SCPD is an exclusive-OR gate with high precision. However, since the upper to lower current ratio is tuned to 3:1 as shown in FIG. 4(b), its output Q has a high-to-low duration ratio of 3:1 as shown in FIG. 4(c), where θg, denotes the delay, or phase difference, between the two inputs of the SCPD, and a phase difference of 2π corresponds to TCLK. If the Ref-CLK-to-CLK0 delay, that is the delay time (TDC) of one delay cell, is between ⅛×TCLK and ⅞×TCLK, the SCPD0 output Q0, will be high, thereby activating the gup signal and disabling the gdown and glock signals. Then, gup increases Vc until TDC is reduced to less than ⅛×TCLK. Conversely, if the Ref-CLK-to-CLK1 delay time, 2×TDC, is less than ⅛×TCLK, the SCPD1 output Q1 will be low, thereby activating the gdown signal. Then, Vc decreases until 2×TDC is larger than ⅛×TCLK. Once coarsely phase-locked, Ref-CLK, CLK0, and CLK1 maintain the delay relationship shown in FIG. 4(c). This can be summarized by the following inequality:

T DC <⅛×TCLK, 2×TDC>⅛×TCLK  (2)

[0050] or equivalently in terms of TVCDL:

⅝×TCLK<TVCDL<{fraction (5/4)}×TCLK, (for TDC={fraction (1/10)}×TVCDL).  (3)

[0051] In this locked state, Q1 is ‘0’ and Q2 is ‘1’. Therefore, gup and gdown are ‘0’ and glock is ‘1’. Then, CP0 is disabled and the (fine) PD is activated. Since TVCDL is the Ref-CLK-to-CLK9 delay time, the inequality (3) implies that the phase of CLK9 could vary as indicated by the shading in FIG. 4(c). However, since the inequality (3) satisfies the inequality (1) with some margin, the control hand-over is smooth without losing the lock. The PD later removes the residual phase error between Ref-CLK and CLK9.

[0052] As long as the following inequality (4) is satisfied, the coarse phase detector works correctly as explained above.

T DC.max (={fraction (1/10)}×TVCDL.max)<⅞×TCLK.  (4)

[0053] Inequality (4) determines the lower bound of the DLL operating range as follows:

{fraction (4/35)}×TVCDL.max<TCLK≦TVCDL.max.  (5)

[0054] Hence, the DLL has a theoretical operating range of 8.75:1. Experimental results show that the prototype DLL works from 30 to 250 MHZ, an 8.3:1 operating range.

[0055] In high-speed operations, the clock output with a short cycle time can be severely distorted as the clock passes through many delay cells. Even if the duty cycle of Ref-CLK is 50% at the entrance, that of CLK9 may deviate significantly from 50%. This causes multiphase clock outputs to have a phase error, which could be fatal in high-speed operations. A cell-level duty cycle correction scheme has been adopted in this design as shown in FIG. 5. On the control hand-over, another phase detector, PD2, is also activated and performs cell-level duty cycle correction. The PD2 takes the inverted Ref-CLK and inverted CLK9 as the inputs, adjusting a control voltage, Vduty. Before the control hand-over, Vduty maintains such a bias voltage that it may generate the identical cell currents in the up and down paths of a delay cell element (DCE), as shown in FIG. 5. After the control hand-over, Vduty fine-tunes the current ratio of the DCE and thus aligns the falling edges of Ref-CLK and CLK9. A duty-cycle correction circuit (DCC) used right at the input of Ref-CLK corrects the duty cycle of Ref-CLK only. With cell-level duty cycle correction, all intermediate clock outputs as well as CLK9 maintain a 50% duty cycle. In this way, multiphase clocks are made equally spaced with a 50% duty cycle.

Receiver Architecture

[0056] The proposed receiver is composed of an on-chip terminator [3], data samplers, a multiphase PLL and a tracked 3× oversampling circuit with dead-zone phase detection for timing recovery, a frequency comparator as a frequency acquisition aid, and a comma detection circuit, as shown in FIG. 6. The reference frequency is provided externally from a crystal and is expected to show a 100 ppm tolerance from its nominal value. Thus, the maximum frequency difference between the reference clock and the recovered clock is less than 200 ppm. The VCO frequency is driven toward the reference frequency with the aid of a phase frequency detector (PFD) in the PLL until reaching the lock range of the PLL. The frequency comparator activates a phase tracking operation only after the frequency lock is obtained when the external reference and VCO frequencies are within 200 ppm. In general, the capture range of a PLL is greater than the lock range. Hence, the frequency comparator is designed to have hysteresis that closely matches the capture and lock range of the PLL, whereas the frequency comparator in does not have hysteresis. The comma detection circuit monitors the incoming data stream to search for the K28.5 pattern in IBM 8B/10B coding for byte alignment. A built-in self-test (BIST) with PBRS generation, verification, and an error counting logic is integrated in the chip to simplify testing at full speed.

[0057] A. Tracked Oversampling Receiver

[0058] In clock and data recovery (CDR) systems with a tracked oversampling technique, multiple samples per bit are used to determine whether the phase of the recovered clock leads or lags the phase of the incoming data. The oversampling effectively behaves as the phase detector. If the VCO phase leads the incoming data, a DOWN pulse is set to HIGH. If the VCO phase lags, an UP pulse goes to HIGH. Each DOWN or UP pulse drives its dedicated charge pump, thereby discharging or charging a loop filter. Digital PLL-based oversampling receivers inherently have a static sampling phase error and suffer from an abrupt phase jump due to phase quantization, thereby sometimes showing an unacceptably high BER at higher data-rates. Alternately, in tracked oversampling receivers, the continual charge pumping removes the phase error gradually without an abrupt phase jump, thereby reducing the BER and, since CDR and data retiming are performed simultaneously, an additional data rotator or data selector is not required, Unlike a conventional non-oversampling CDR, the operating frequency of both the VCO and digital circuits are reduced to {fraction (1/10)} the data rate and thus the design is relatively simple and robust.

[0059] After the signal is sent over a long cable, the received data eye is severely degraded as shown in FIG. 7. Sampled bits are examined to determine whether to move the sampling clock phases earlier (UP) or later (DOWN). Sampling clock location is settled in steady state, where the number of UP pulses is equal to the number of DOWN pulses as shown in FIG. 7. In the tracked 2× oversampling technique, an UP or DOWN signal always pulses at every transition as shown in FIG. 7(a). Therefore, the average error current (id) over a bit time is

i d =I p α·sgnθ e ,  (6)

[0060] where Ip is the actual pumping current of a charge pump, α is transition density, and sgnθe is the sign of the phase error. However in this tracked 3× oversampling technique, only the tall portions of the histogram activate the phase adjustment, and the transition edges located in a dead-zone—the middle portion of one-third of the bit time—are ignored for phase comparison as shown in FIG. 7(b). Because of the existence of this dead-zone, the phase detection of the tracked 3× oversampling technique is referred to as dead-zone phase detection.

[0061] The jitter histogram of the data stream in FIG. 7 is based on a receiver specification. If the equivalent jitter histogram with a uniform probability density function (pdf) is used for the simplicity of calculation, the average error current of the dead-zone phase detection can be calculated as follows: 1$\begin{array}{cc}{i}_d=I_p·\alpha ·\frac{T_j-1/3}{T_j}·\mathrm{sgn}{\theta }_e,& \left(7\right)\end{array}$

[0062] where TJ is the equivalent total jitter amount and ‘TJ−⅓’ is the amount of jitter activating the phase adjustment. Equation (7) indicates the average error current is related to TJ. If TJ is 50% of the bit time, i.e., 0.5× unit interval (UI), the average error current becomes 2$\begin{array}{cc}{i}_d=I_p·\alpha ·\frac{1}{3}·\mathrm{sgn}{\theta }_e,& \left(8\right)\end{array}$

[0063] The dead-zone phase detection has one-third the average error current of the 2× oversampling technique. In other words, for the same average error current, the dead-zone phase detection can use a pumping current that is three times larger than the 2× oversampling.

[0064] B. Wide Pumping Current Range of Dead-Zone Phase Detection

[0065] To guarantee the stability of a PLL, the following stability limit should be kept:

K v ,·I p ′·R<f ref ,  (9)

[0066] where Kv is the VCO gain, Ip′ is the effective charge pump current, R is the loop filter resistor, and fref is the input reference frequency. At the low supply voltages used in current sub-micron technologies, Kv must be large enough to guarantee lock in varying process and temperature conditions, and R must be sufficiently large to avoid jitter peaking. Therefore, from (9), Ip′ has its upper limit, and to guarantee the phase margin of a PLL, Ip′ cannot be reduced indefinitely, thus giving its lower limit. Therefore, IP′ should be controlled so that it is within the range between its upper and lower limits.

[0067] Although the effective pumping current (IP′) is proportional to the actual pumping current (IP), the former is also related to the jitter histogram, jitter amount, phase detection type, etc. Thus, to select the optimal phase detection type that allows a wider actual pumping-current range, simulation was performed to find the relationship of the actual pumping current versus the BER as shown in FIG. 8. The wide pumping-current range means easier PLL design in terms of loop stability. The jitter amount in this simulation is a little larger than a receiver specification and it is assumed that fref is 100 MHz, Kv is 200 MHz/V, R is 1 kΩ, and the loop filter capacitance C is 350 pF. 2×, equally spaced 3×, and unequal 3× oversampling are chosen for the comparison. The 2× oversampling has a narrow pumping-current range. On the other hand, the 3× oversampling has a wider pumping-current range without BER degradation, since the dead zone between the boundary sampling clocks avoids excessive phase adjustment. A dead-zone of one-half the bit time was chosen in the unequal 3× oversampling scheme. However, this scheme does not show an improvement over the equally spaced 3×oversampling in spite of the extra complexity. Furthermore, the BER increases at low pumping current since the boundary clocks cannot prevent jitter from destroying the middle samples due to the insufficient phase margin and narrow boundary-to-middle clock spacing.

[0068] The simulation shows that the pumping-current range increases with the operating frequency, as shown in FIG. 9. This agrees with (9). Considering a 2-ns phase lag between phase detection and adjustment, the actual pumping-current range will be narrower, as shown in FIG. 9(b). However, this simulation is performed under the following three assumptions:

[0069] 1) there are no process, voltage, and temperature (PVT) variations of the PLL components (except for the pumping current),

[0070] 2) Kv remains fixed at 200 MHz/V although the tuning range should increase with the operating frequency, and

[0071] 3) there are no parasitic currents due to coupling, charge sharing, etc., to damage the PLL's operation, especially when the pumping-current is low. Therefore, in most practical cases, the pumping-current range will be reduced much more than shown in FIG. 9(b).

[0072] Thus, when 2× oversampling is used, the pumping current must be adjusted towards the optimal value depending on the operating conditions and frequency. However, the receiver with dead-zone phase detection has approximately a three times wider pumping-current range compared with 2× oversampling in the whole operating frequency range. Therefore, it operates in a wide frequency range without resorting to such a tight pumping-current adjustment. The previous tracked 3× oversampling phase detector raises several design problems due to the long pumping pulses that persist for one full VCO cycle time. The proposed design reduces the pulse width to one bit time, thereby not only avoiding the use of an extremely small pumping current, but also preventing the enlargement of the phase lag. Furthermore, since the design has no frequency-acquisition aid, its operating range is severely limited.

[0073] C. Large Jitter Tolerance of Dead-Zone Phase Detection

[0074] Due to systematic variation of bit times and other factors, the jitter histogram is often found to be asymmetric with a longer tail in one direction, as shown in FIG. 10. In the tracked 2× oversampling receiver, since the boundary clock edge tends to be settled at the centroid of the jitter histogram, the middle clock edge could be off the optimum point as shown in FIG. 10(a). However, in the tracked 3× oversampling receiver, since the middle clock edge is driven toward the center of an eye using only the tail portions, the middle clock edge does not vary so much in spite of the centroid shifting as shown in FIG. 10(b). Therefore, when compared with a 2× oversampling scheme, its operation is more robust in the presence of excessive jitter and bit errors are less likely to occur. Although the width of the dead zone can be varied, simulation shows the dead-zone of one-third the bit time offers adequate performance as well as simpler implementation. Interestingly, when the incoming data signal is clean with an ideal eye diagram and there is neither deterministic nor random jitter, the recovered clock drifts by up to one-third of the bit time, i.e., between +⅙×UI and −⅙×UI, thereby having more accumulated jitter. However, both the cycle-to-cycle jitter (<{fraction (1/30)}×UI) and the BER (<10−13) are still very low.

[0075] In most practical cases, such as an ISI or a periodic jitter environment, some data have a large eye width and others have a small eye width, as shown in FIG. 11. When the dead-zone phase detection is used, there is only a small number of UP and DOWN pulses. However, in 2× oversampling, UP and DOWN signals pulse alternately with alternating big and small eyes. It induces a high-frequency ripple in the control voltage even in the locked state.

[0076] D. Small Phase Error of Dead-Zone Phase Detection

[0077] With small phase error, the middle clock edge comes close to the center of an eye, thereby lowering the BER. In 2× or (equally spaced) 3× oversampling CDR, the simulation results show that the phase error increases with the pumping current. Thus, at the lower limit of the pumping current, the receiver has the minimum phase error. The lower limit is primarily determined by parasitic currents rather than the lack of phase margin and it is around 10-20 μA. With a 10-μA pumping current, the 3× oversampling scheme exhibits 75% the phase error of the 2× scheme. With 20 μA, the former exhibits 60% the phase error of the latter as shown in FIG. 12(a) and (b). In the whole pumping-current range, if the same pumping current is used, the 3× oversampling scheme exhibits smaller phase error than the 2× scheme, and the 3× oversampling scheme with three times the pumping current induces a similar phase error to the 2× scheme as shown in FIG. 12(b) and (c).

[0078] E. Frequency Comparator

[0079] As described above, the frequency comparator has hysteresis between the lock and unlock conditions. A 16-bit binary counter is updated at every VCO-CLK cycle as shown in FIG. 13. A 14-bit divider divides the Ref-CLK. Latches, U2, sample the binary counter value at the divided Ref-CLK rising edges. However, the Ref-CLK and VCO-CLK domains are asynchronous with each other. Thus, there is the possibility that the latches fall in meta-stability when transmitted value changes on the sampling edge of the Ref-CLK. Since some bits have been already changed, but other bits have not been changed yet at the sampling time, the sampled value may be quite different from the original value. To prevent this meta-stability problem, a binary-to-gray code converter is inserted before the latching stage to allow only one bit to be inverted whenever the counter value is updated, and even if the meta-stability occurs, it does not create any problem since only a one-bit difference is induced.

[0080] After another 16,384 cycles, the latches sample the counter value once more and compare it with the previous sample for frequency comparison. If the Ref-CLK and VCO-CLK frequencies are within 200 ppm, DATA-LOOP is activated. Sometimes, a temporary frequency-mismatch may intermittently unlock the loop. Therefore, the comparator is designed to have a looser unlock condition of 1000 ppm. Since this frequency comparator does not use a reset signal, no extra cycle time for a reset procedure is required.

[0081] F. Voltage-Controlled Oscillator Based on a Folded Starved Inverter

[0082] For better jitter performance, the PLL should have a structure immune to supply noise and should also contain fewer noise sources. In conventional VCOs using a replica bias circuit, most jitter is produced by noise in the bias voltage from the replica circuit. Some analyses [19], [20] indicate that the output waveform of a delay cell should be symmetric, have a fast slew rate and a large voltage swing, so a folded starved inverter has been designed with such guidelines in mind, as shown in FIG. 14. A cross-coupled PMOS pair is included to sharpen the transition edges of the output waveform regardless of the delay time. The inverters, G1 and G2, give more linearity to the VCO gain, and its positive supply-sensitivity compensates for the negative supply-sensitivity of the starved inverters. To further reduce the effect of power supply fluctuation, a supply regulator is added with resistors and capacitors to filter out the high frequency components of the 3.3-V I/O supply and to provide a clean voltage to the gate of an NMOS source follower. Simulation results show that the proposed VCO has about a 10-fold smaller supply sensitivity (0.23 ps/mV) and substrate sensitivity (0.26 ps/mV) than a conventional VCO using a replica bias circuit. Since there are no replica bias circuits and no tall current, this VCO has less phase noise than the replica biased VCO. Phase noise of −85 dBc/Hz at 100-kHz offset is obtained from noise simulation, which is 15 dB less than that of the VCO with replica bias.

[0083] The prototype chip has been fabricated with a 0.25-μm 1-poly 4-metal logic CMOS process. The chip uses two supply voltages, 2.5V and 3.3V. The 3.3-V supply is used in the I/O circuits and the VCO in the PLL. For the other core circuits the 2.5-V supply is used. The DLL has one-quarter the size of the PLL. The designed chip is packaged with a 64-pin PQFP. FIG. 15 shows a microphotograph of the fabricated chip. The chip size is 2.3 min×2.14 min and thus is 4.9 mm2.

[0084] FIG. 16(a) and (b) show the measured jitter histograms of the DLL and PLL clocks, respectively, when they are locked to the reference clock at 187 MHz. The jitter performance at 187 MHz is 6-ps RMS and 40-ps peak-to-peak in the DLL, and 5.5 ps and 35 ps in the PLL. The jitter performance at 70 MHz is 3.5 ps and 21 ps in the DLL, and 3.6 ps and 25 ps in the PLL. The lower jitter at 70 MHz is due to reduced jitter of the clock source at this frequency in the measurement. Although the proposed DLL has a larger VCDL gain than the previous DLL in [6], it shows a comparable jitter performance due to pumping-current reduction and filter-capacitance enlargement. The jitter of the PLL is reduced to be half that of a replica biased PLL, which is previously designed, but not published.

[0085] In a board-level test of the transceiver operating at 1 GBaud over a 30-m 150-i shielded twisted pair (STP) cable, at 1.25 GBaud over 25 m, and at 2.5 GBaud over 10 m, no error was detected for more than three hours, and thus the BER is less than 10-13 (see FIG. 1, FIG. 17, and FIG. 18). FIG. 1(a), FIG. 17(a), and FIG. 18(a) show that the TX data eyes have good uniformity, with less than 2% timing error among the clock phases over the range of 30 to 250 MHz, which implies that the multiphase clocks of the DLL are acceptably equally spaced. The jitter of the TX data is about 20% larger than that of the DLL clock output. Due to the dead-zone phase detection, the recovered clock jitter is actually reduced in spite of the large jitter in the incoming data signals. In the extreme case when the signal jitter is 111-ps RMS at 1.25 GBaud as shown in FIG. 17(b), the recovered clock jitter is reduced to 28-ps RMS as shown in FIG. 17(c), and the peak-to-peak jitter of the recovered clock is less than one-fifth the bit time, i.e., 0.2×UI. This measured result agrees with the simulation result in FIG. 12(a). This peak-to-peak jitter is less than the static phase error of a digital PLL-based 3× oversampling receiver. Furthermore, it is less than the static phase error of a digital PLL-based 5× oversampling receiver. Conversely, when there is little jitter in the incoming data signal, relatively large jitter is observed in the recovered clock. If, for example, a 1.25-GBaud 10-m optic fiber link is set up, the RX data are almost clean. Then, the recovered clock jitter is about 0.3×UI. However, as mentioned above, the cycle-to-cycle jitter (<{fraction (1/30)}×UI) is still very low. Even in the optic fiber link, the transceiver operates with no error detected for more than three hours.

[0086] Table 1 summarizes the measured performance of the transceiver. The DLL frequency range is from 30 to 250 MHz. The data rate range of the link is from 0.6 to 2.5 GBaud. The power dissipation is proportional to the data rate., At 2.5 GBaud, the prototype chip consumes 269 mW.

[0087] A tracked 3× oversampling receiver with dead-zone phase detection offers wide pumping-current range, large jitter tolerance, and small phase error in the presence of excessive jitter and ISI. A wide-range multiphase DLL for a transmitter shows the maximum-to-minimum operating frequency ratio of 8.3, with a coarse phase detection to fine phase detection hand-over scheme. The multiphase clocks of the DLL are equally spaced, thereby enabling the TX data eyes to have good uniformity. A supply-regulated, folded starved inverter cell, which is designed for the low-jitter performance of the receiver VCO, offers full swing, sharp transition edge, linear gain, and low supply sensitivity. A frequency comparator with hysteresis is incorporated as a frequency acquisition aid for the receiver PLL. The transceiver, implemented in 0.25 μm CMOS technology, operates at 2.5 GBaud over a 10-m 150-Ω STP cable and at 1.25 GBaud over 25 in with a BER of less than 10−13.

[0088] In view of the foregoing, it will be appreciated that an apparatus includes means for generating a data sampling clock signal and means for using the data sampling clock signal to sample a data signal into sampled data representing a first zone, a second zone, and a third zone of the data signal. Means are used for determining which zone of the sampled data has a transition of the data signal. Means are also used for indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition.

[0089] It will also be appreciated that a folded starved inverter differential output apparatus for use in a voltage controlled oscillator includes a first polarity of two transistors cross-coupled and a second polarity of four transistors. Also included are two inverter gates and a supply regulator.

[0090] Furthermore, a frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit; wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than 1000 parts per million. Also included is a data loop circuit; wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than 200 parts per million.

[0091] In addition to the above mentioned examples, various other modifications and alterations of the invention may be made without departing from the invention. Accordingly, the above disclosure is not to be considered as limiting and the appended claims are to be interpreted as encompassing the true spirit and the entire scope of the invention.

Claims

1. An apparatus comprising means for generating a data sampling clock signal; means for using the data sampling clock signal to sample a data signal into sampled data representing a first zone, a second zone, and a third zone of the data signal; means for determining which zone of the sampled data has a transition of the data signal; and means for indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition.

2. A folded starved inverter differential output apparatus for use in a voltage controlled oscillator comprising: a first polarity of two transistors cross-coupled; a second polarity of four transistors; two inverter gates; and a supply regulator.

3. A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit comprising: a reference loop circuit; wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than 1000 parts per million; and a data loop circuit; wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than 200 parts per million.