The disclosed embodiments relate to integrated circuit memory devices and, in particular, to a 3 transistor non-volatile memory (NVM) cell without program disturb and with an N/P/N structure to accommodate very small area.
U.S. Pat. No. 7,164,606 B1, which issued on Jan. 16, 2007, to Poplevine et al., discloses an all PMOS 4-transistor non-volatile memory (NVM) cell that utilizes reverse Fowler-Nordheim tunneling for programming. U.S. Pat. No. 7,164,606 is hereby incorporated by reference herein in its entirety to provide background information regarding the present invention.
Referring to
During the above-described program sequence, the drain and source regions of the read transistor Pr and the program transistor Pw of the non-programmed NVM cells are set to a fixed inhibiting voltage VN, while the Ve electrode is set to voltage VN and the Vc electrode is ramped up from 0V to Vcmax. As a result, negative charge still gets trapped to the floating gate of non-programmed NVM cells, even though the amount is less than the negative charge that gets trapped to the floating gate of programmed NVM cells. This sets the voltage level of the floating gate of non-programmed cells to about VN above the voltage level of the floating gate of the programmed cells. This means that that the maximum possible voltage level difference between the floating gates of the programmed cells and the floating gates of the non-programmed cells is VN. The non-programmed cells with this condition are referred to as disturbed cells.
Thus, while the all-PMOS 4-transistor NVM cell programming technique disclosed in the '606 patent provides advantages of both low current consumption, allowing the ability to simultaneously program a large number of cells without the need for high current power sources, and a simple program sequence, it would be highly desirable to have available an NVM cell that maintains the benefits of low programming current, but also avoids the disturbed cell condition.
Embodiments provide a non-volatile memory (NVM) cell structure comprising: an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode connected to a data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode connected to the data storage node; and an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.
Other embodiments provide a method of programming a non-volatile memory (NVM) cell, the NVM cell including an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to a data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node, the NVM cell programming method comprising: ramping up the control voltage and erase voltage electrodes from 0V to a predefined maximum control voltage Vcmax and a predefined maximum erase voltage Vemax, respectively, while setting the source and drain voltages of the NMOS data transistor to 0V.
Other embodiments provide a method of programming a non-volatile memory (NVM) array that includes a plurality of rows of NVM cells, each NVM cell in the array including an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to a data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode connected to the data storage node; and an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node, the NVM cell array programming method comprising: for those NVM cells in the array to be programmed, ramping up the control voltage and erase voltage electrodes from 0V to Vcmax and Vemax, respectively, while setting the source and drain electrodes of the cell's NMOS data transistor to 0V.
The features and advantages of the various aspects of the present invention will be more fully understood and appreciated upon consideration of the following detailed description of the invention and the accompanying drawings, which set forth illustrative embodiments in which the concepts of the invention are utilized.
Thus, the
During the programming sequence, as discussed further below (see Program Sequence), the Ve electrode and the Vc electrode of the selected row to be programmed are ramped from 0V to a predefined maximum erase voltage Vemax and a predefined maximum control voltage Vcmax, respectively, while the B1 electrode or the B2 electrode or both are set to 0V. For the selected row not to be programmed (inhibit program), the Ve electrode and the Vc electrode are ramped up from 0V to the predefined maximum erase voltage Vemax and the predefined maximum control voltage Vcmax, respectively, while the B1 electrode or the B2 electrode or both are set to an inhibiting voltage VN. The Ve electrodes and Vc electrodes of non-selected rows remain at 0V. Thus, NVM cells in the non-selected rows will not be programmed or disturbed from the erase state, independent of the voltage value of the B1 electrode and the B2 electrode. This eliminates the need for passgate transistors on the B1 and B2 electrodes in the NVM array, thus keeping the size of the array small. The Vemax and Vemax voltage levels are chosen so that after an erase sequence (see Erase Condition below) and a programming sequence, the floating gate voltage of programmed cells is at VFG1, and the floating gate voltage of non-programmed cells is at VFG2, where VFG1 and VFG2 are lower than 0V, and VFG1 is smaller than VFG2 (for example, VFG1=−4V and VFG2=−1V).
During the read sequence, as discussed further below (see Read Condition), the Ve electrodes and Vc electrodes of non-selected rows are set to 0V, while the Ve electrode and Vc electrode of the selected row to be read are set to a predefined maximum read voltage Vrmax, such that Vrmax+VFG1 is lower than 0V and Vrmax+VFG2 is higher than 0V (for example, Vrmax=3V, so that Vrmax+VFG1==−1V and Vrmax+VFG2=+2V). Also, for all of the NVM cells in the array, the B1 electrodes are set to 0V and the B2 electrodes are set to a positive voltage such that the voltage difference between the B1 electrode and the B2 electrode is sufficient to be able to read while preventing disturb to programmed cells (for example, about 1V), or vice versa. Thus, in this read condition, all of the NVM cells from non-selected rows will give zero current output and non-programmed cells from the selected row to be read will give a non-zero current output.
The NVM cell and the NVM cell array retain the advantages of the Reverse Fowler-Nordheim Tunneling programming method described above with respect to U.S. Pat. No. 7,164,606.
Referring to
Program Sequence
1. All of the electrodes are set to 0V.
2. For the selected row to be programmed, set the B1 electrode to 0V and the B2 electrode to floating, or the B2 electrode to 0V and the B1 electrode to floating, or both electrodes to 0V, then ramp up the Vc electrode of the selected row from 0V to Vcmax, and the Ve electrode of the selected row from 0V to Vemax, and hold it for the duration of a predefined program time Tprog. (Compared with the programming sequence for the all-PMOS 4 transistor NVM cell disclosed in U.S. Pat. No. 7,164,606, the Ve electrode is now ramped up along with the Vc electrode in order to prevent forward biasing the PN diode that is formed between the isolated P-well and the N-well). Then ramp down the Vc electrode of the selected row from Vcmax to 0V, and the Ve electrode of the selected row from Vemax to 0V. The Vpw electrodes of the selected row are set to 0V.
3. For the selected row not to be programmed (inhibit program), set the B1 electrode to an inhibiting voltage VN and the B2 electrode to floating, or the B2 electrode to the inhibiting voltage and the B1 electrode to floating, or both electrodes to the inhibiting voltage VN, then ramp up the Vc electrode of the selected row from 0V to Vcmax and the Ve electrode of the selected row from 0V to Vemax and hold these voltages for the duration of the predefined program time Tprog (Compared with the programming sequence for the all-PMOS 4 transistor NVM cell disclosed in U.S. Pat. No. 7,164,606, the Ve electrode is now ramped up along with the Vc electrode in order to prevent forward biasing the PN diode that is formed between the isolated P-well and the N-well, see
4. For non-selected rows, keep the Vc and Ve electrodes of these rows at 0V, the B1 electrode to 0V or the inhibiting voltage VN, or the B2 electrode to 0V or the inhibiting voltage VN.
5. Return all of the electrodes with the voltage VN to 0V. After this, the programming sequence is completed, where programmed cells in the selected row will have been programmed and non-programmed cells in the selected row (inhibit program) will not have been programmed while non-programmed cells in non-selected rows will not have been programmed and in no-disturb condition.
Erase Condition
Ramp up the Ve electrode from 0V to the maximum erase voltage Vemax, hold it for the duration of a predefine erase time Terase, and ramp the Ve electrode back down from the maximum erase voltage Vemax to 0V. All other cell electrodes are set to 0V.
Read Condition
Set the B1 electrode to 0V and the B2 electrode to a voltage difference of about 1V (e.g., sufficient enough voltage to be able to read the cell current while preventing disturb to the programmed cells), or vise versa. Set the Vc electrode and the Ve electrode of the selected row to be read to the maximum read voltage Vrmax, and set the Vc electrodes and the Ve electrodes of the non-selected rows to 0V. All other electrodes are set to 0V.
Those skilled in the art will appreciate that the voltage levels utilized in the program, erase and read operations will depend upon the thickness of the gate oxide utilized in the NMOS and PMOS devices of the NVM cell 200. For example, for a gate oxide thickness of 60-80 Å, VN˜=3.3V, Vcmax=Vemax˜=10V, with Tprog=Terase˜=20-50 milliseconds. For gate oxide thickness of 120 Å, VN˜=5.0V, Vcmax=Vemax˜=16V, with Tprog=Terase˜=20-50 milliseconds.
It should be understood that the particular embodiments described above have been provided by way of example and that other modifications may occur to those skilled in the art without departing from the scope of the claimed subject matter as expressed in the appended claims and their equivalents.