Patent Application
20110157260
This application claims the benefit of Korean Patent Application No. 10-2009-0134638 filed on Dec. 30, 2009 and Korean Patent Application No. 10-2010-0030382 filed on Apr. 2, 2010, which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to an image display device, and more particularly to a 3-dimensional image (hereinafter referred to as “3D image”) display device which is capable of increasing the display quality by improving the response time of liquid crystals.
2. Discussion of the Related Art
A 3D image display device implements a 3D image using a stereoscopic technique or an autostereoscopic technique. The 3D image display device uses parallax images of the left and right eyes having a high 3D effect and comprises a stereoscopic technique and an autostereoscopic technique, both of which are being put to practical use. In the autostereoscopic technique, in general, an optical plate, such as a parallax barrier for separating the optical axes of the left and right parallax images, is placed in front or at the rear of a display screen. The stereoscopic technique is used to display the left and right parallax images with different polarization directions on a liquid crystal display panel and to implement a 3D image using polarizing glasses or liquid crystal shutter glasses.
The stereoscopic technique can be classified into a first polarization filter method using a pattern retarder film and polarizing glasses, a second polarization filter method using a switching liquid crystal layer and polarizing glasses, and a shutter glass method using liquid crystal shutter glasses.
The first polarization filter method is used to implement a 3D image by alternately displaying a left-eye image and a right-eye image in a liquid crystal panel for every horizontal line, switching polarization characteristics incident on the polarizing glasses via the pattern retarder film on the liquid crystal panel, and spatially splitting the left-eye image and the right-eye image. The second polarization filter method is used to implement a 3D image by alternately displaying a left-eye image and a right-eye image in a liquid crystal panel on a frame basis, switching polarization characteristics incident on the polarizing glasses via the switching liquid crystal layer on the liquid crystal panel, and temporally and spatially splitting the left-eye image and the right-eye image. In the first and second polarization filter methods, the pattern retarder film or the switching liquid crystal layer disposed on the liquid crystal panel as a polarization filter may adversely affect the transmittance of a 3D image.
The shutter glass method is used to implement a 3D image by alternately displaying a left-eye image and a right-eye image in a liquid crystal panel on a frame by frame basis and opening or shutting the left/right shutters of the liquid crystal shutter glasses in synchronism with the display timing. The liquid crystal shutter glasses, as shown in
To produce an excellent binocular parallax by turning on a backlight in the second period Tb of each frame as in the required specification of
Accordingly, the present invention is directed to 3D image display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An aspect of this invention is to provide a 3D image display device which is capable of increasing the display quality by improving the response time of the liquid crystals.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a 3-dimensional (3D) image display device includes a liquid crystal panel configured to alternately display a left-eye image and a right-eye image in a cycle of unit frame period, a data driving circuit configured to drive data lines of the liquid crystal panel, a gate driving circuit configured to drive gate lines of the liquid crystal panel, a timing controller configured to divide the unit frame period into N sub-frame periods for each of the left-eye image and the right-eye image, where N is an integer equal to or greater than 2, a plurality of light sources configured to generate light to be radiated to the liquid crystal panel, a light source control circuit configured to generate a backlight control signal to control a turn-on time of the plurality of light sources, and a light source driving circuit configured to turn off all the light sources during a first N-1 subframe periods and turn on all the light sources during a last subframe period.
In another aspect, a method of driving a 3-dimensional (3D) image display device having a liquid crystal display panel and a plurality of light sources includes alternately displaying a left-eye image and a right-eye image in a cycle of unit frame period, providing light to the liquid crystal display panel with the plurality of light sources, dividing the unit frame period into N sub-frame periods for each of the left-eye image and the right-eye image, generating a backlight control signal to control a turn-on time of the plurality of light sources, and turning off the plurality of light sources during a first N-1 sub-frame periods and turning on the plurality of light sources during the last sub-frame period.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
The liquid crystal panel 10 comprises two sheets (i.e., upper and lower) of glass substrates and a liquid crystal layer interposed between the glass substrates. A number of data lines DL and a number of gate lines GL intersect each other in the lower glass substrate of the liquid crystal panel 10. Liquid crystal cells Clc are arranged in a matrix form in the liquid crystal panel 10 by a crossing structure of the data lines DL and the gate lines GL. A thin film transistor (TFT), a storage capacitor Cst and the pixel electrode 1 of each liquid crystal cell Clc which are coupled to the TFT, and so on are further formed in the lower glass substrate of the liquid crystal panel 10.
Black matrices and color filters (not shown) are formed on the upper glass substrate of the liquid crystal panel 10. A common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method, such as a twisted nematic (TN) mode and a vertical alignment (VA) mode. On the other hand, the common electrode 2 is formed on the lower glass substrate along with the pixel electrode 1 in a horizontal electric field driving method, such as an in-plane switching (IPS) mode and a fringe field switching (FFS) mode. A polarization plate is attached to each of the upper and lower glass substrates of the liquid crystal panel 10. An orientation film for determining the pre-tilt angle of a liquid crystal is formed on an inner surface contacting the liquid crystal.
The timing controller 11 generates a data timing control signal DDC to control the operation timing of the data driving circuit 12 and a gate timing control signal GDC to control the operation timing of the gate driving circuit 13 in response to timing signals Vsync, Hsync, DE, and DCLK, which are received from an external system circuit. The timing controller 11 controls the operations of the data driving circuit 12 and the gate driving circuit 13 in the sub-frame frequency of (unit frame frequency×N) Hz, where N is a positive integer equal to or greater than 2, by multiplying the data timing control signal DDC and the gate timing control signal GDC. For example, the sub-frame frequency is 240 Hz when the unit frame frequency is 120 and N is 2.
The timing controller 11 performs time division on one frame period into N subframe periods. The timing controller 11 copies unit frame data 3D DATA of a 3D data format, received from the external system circuit, to a frame memory on a frame by frame basis. The timing controller 11 repeatedly supplies data displayed when the left shutter of the shutter glasses 18 is open (hereinafter referred to as “left-eye data”) to the data driving circuit 12 during the N subframe periods of an odd frame. The timing controller 11 repeatedly supplies data displayed when the right shutter of the shutter glasses 18 is open (hereinafter referred to as “right-eye data”) to the data driving circuit 12 during the N subframe periods of an even frame.
The data driving circuit 12 comprises a number of data drive integrated circuits (ICs). Each of the data drive ICs comprises a shift register, a register, a latch, a digital to analog (D/A) converter, a multiplexer, and an output buffer. The shift register samples a clock signal. The register temporarily stores digital data received from the timing controller 11. The latch stores data for every one line in response to a clock signal generated by the shift register and outputs the data of one line unit at a time. The D/A converter selects a gamma voltage of the positive or negative polarity with reference to a gamma reference voltage in response to the digital data value output from the latch. The multiplexer selects the data lines DL along which analog data converted in response to the positive polarity or negative polarity gamma voltage are supplied. The output buffer is coupled between the multiplexer and the data lines DL. The data driving circuit 12 converts the left eye/right-eye data of a 3D data format into an analog data voltage in response to the data timing control signal DDC of the sub-frame frequency (unit frame frequency×N) Hz and supplies the same data to the data lines DL N times within each frame.
The gate driving circuit 13 comprises a number of gate drive ICs. Each of the gate drive ICs comprises a shift register, a level shifter for converting the output signal of the shift register according to a swing width suitable to drive the TFTs of the liquid crystal cells, and an output buffer. The gate driving circuit 13 sequentially outputs scan pulses or gate pulses in response to the gate timing control signal GDC of the sub-frame frequency (unit frame frequency×N) Hz and supplies them to the gate lines GL twice within each frame.
The backlight unit 16 comprises a number of light sources and radiates light to the liquid crystal panel 10. The backlight unit 16 may be implemented using a direct type backlight unit or an edge type backlight unit. The direct type backlight unit 16 has a structure in which a number of optical sheets and a diffusion sheet are stacked under the liquid crystal panel 10 and a number of the light sources are disposed under the diffusion sheet. The edge type backlight unit 16 has a structure in which a number of optical sheets and a light guide plate are stacked under the liquid crystal panel 10 and one or more of the light sources are disposed on the side of the light guide plate. The light sources may be implemented as a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), dot light sources such as a light emitting diode (LED), or any other suitable lamp or light emitting device.
The light source control circuit 14 generates a light source control signal LCS under the control of the timing controller 11 and controls the light sources according to the backlight control signal, e.g., a pulse width modulation (PWM) signal, pulse amplitude modulation (PAM) signal, pulse frequency modulation (PFM) signal, so that the light sources are blinked at the same time in response to the light source control signal LCS. The light source control signal LCS includes a PWM signal for controlling the turn-on time of the light sources and a current control signal for controlling the driving current of the light sources. A maximum duty ratio of a PWM signal may be set to 50% or less in order to improve the performance of 3D cross-talk and a motion picture response time (MPRT). A level of the driving current of the light sources may be set, so that the level of the driving current is inversely proportional to the maximum duty ratio of the PWM signal by the current control signal. More specifically, as the maximum duty ratio of the PWM signal decreases, the level of the driving current increases. The inversely proportional relationship between the maximum duty ratio of the PWM signal and the level of the driving current is to compensate for a reduction in luminance of the screen resulting from an increase in turn-off time of the light sources in one frame period for improving the MPRT performance. A duty ratio of the PWM signal may vary depending on the input image within a range equal to or less than the previously set maximum duty ratio. In this case, the light source control circuit 14 analyzes the input image and adjusts the duty ratio of the PWM signal according to the analysis result of the input image. The light source control circuit 14 may be built in the timing controller 11.
The light source control signal LCS comprises turn-on/off timings of the light sources. The turn-on timing of the light sources may vary depending on the duty ratio of a PWM signal after the liquid crystals are saturated. The turn-off timing of the light sources may be fixed to a point of time at which the left/right-eye data of a next frame are written at the center of the liquid crystal panel 10. The light source driving circuit 15 blinks the light sources by turning off all the light sources during the first N-1 subframe period and turning on all the light sources during the last subframe period, in response to the light source control signal LCS.
The shutter control circuit 17 determines whether a current frame is an odd frame in which the left-eye data will be displayed or an even frame in which the right-eye data will be displayed based on the vertical sync signal Vsync received from the external system circuit. The shutter control circuit 17 generates a left shutter control signal STL to open the left shutter of the shutter glasses 18 during the odd frames and a right shutter control signal STR to open the right shutter of the shutter glasses 18 during the even frames.
The shutter glasses 18 is an apparatus to be worn by a viewer who wants to see left/right-eye images in three-dimensions, displayed in the liquid crystal panel 10 on a frame by frame basis. The shutter glasses 18 alternately open and shut the left and right shutters on a frame by frame basis in response to the shutter control signals STL and STR generated by the shutter control circuit 17. As the left/right-eye images are alternately shut off, different images are formed in the left and right eyes of the shutter glasses 18. Accordingly, a viewer can have a feeling of viewing a 3D image.
The data modulation circuit 20 is configured to modulate the unit frame frequency to prevent flickering. In particular, the data modulation circuit 20 inserts interpolation frames into the input frame data provided from the video source to generate a unit frame data. For example, the data modulation circuit 20 can modulate the input frame data with a frequency of 60 Hz into a unit frame data with a unit frame frequency of 120 Hz by inserting one interpolation frame for each input frame data. Alternatively, the data modulation circuit 20 can modulate the input frame data with a frequency of 60 Hz into a unit frame data with a unit frame frequency of 80 Hz by inserting one interpolation frame for every three input frame data. The data modulation circuit 20 then provides the unit frame data to the timing controller 11. The data modulation circuit 20 can be formed within an external system circuit (not shown).
As shown in
During the first and second subframes SF1 and SF2 of an odd frame, left-eye data DATA (L) for one frame are redundantly displayed in the liquid crystal panel 10. Further, during the first and second subframes SF1 and SF2 of an even frame, right-eye data DATA (R) for one frame are redundantly displayed in the liquid crystal panel 10. The response time of a liquid crystal LC is inversely proportional to the capacitor components existing in the liquid crystal panel. The capacitance of the capacitor components is inversely proportional to the frame frequency. Accordingly, when the unit frame frequency is multiplied by two as compared with the input frame frequency, the response time of the liquid crystal LC can become faster correspondingly. Accordingly, in the odd frame, before a lapse of time corresponding to the first subframe SF1 immediately after the left-eye data DATA (L) are written at the center of the liquid crystal panel 10, the liquid crystal LC at the center of the liquid crystal panel 10 is saturated and maintained at the saturation state throughout the second subframe SF2 of the odd frame. In the odd frame, all the light sources BL are simultaneously turned on at the maximum duty ratio of 50% or less during the second subframe SF2 in which the central liquid crystal LC is maintained at the saturation state. Further, the left shutter of the shutter glasses 18 is open during the odd frame period.
Meanwhile, in the even frame, before a lapse of time corresponding to the first subframe SF1 immediately after the right-eye data DATA (R) is written at the center of the liquid crystal panel 10, a liquid crystal LC at the center of the liquid crystal panel 10 is saturated and maintained at the saturation state throughout the second subframe SF2 of the even frame. In the even frame, all the light sources BL are simultaneously turned on at the maximum duty ratio of 50% or less during the second subframe SF2 in which the central liquid crystal LC is maintained at the saturation state. Further, the right shutter of the shutter glasses 18 is open during the even frame period.
The turn-on timing of the light sources BL, as shown in
3D cross-talk can be reduced by improving the response time of the liquid crystal display panel using the first embodiment shown in
As shown in
During the first, second, and third subframe periods (SF1, SF2, and SF3) of an odd frame, left-eye data DATA (L) for one frame is redundantly displayed in the liquid crystal panel 10. Further, during the first, second, and third subframe periods (SF1, SF2, and SF3) of an even frame, right-eye data DATA (R) for one frame is redundantly displayed in the liquid crystal panel 10. The response time of a liquid crystal LC is inversely proportional to the capacitor components existing in the liquid crystal panel. The capacitance of the capacitor components is inversely proportional to the frame frequency. Accordingly, when the unit frame frequency is multiplied by three as compared with the input frame frequency, the response time of the liquid crystal LC can become faster correspondingly. Accordingly, in the odd frame, before a lapse of time corresponding to the first subframe SF1 immediately after the left-eye data DATA (L) is written at the center of the liquid crystal panel 10, the liquid crystal LC at the center of the liquid crystal panel 10 is saturated and maintained at the saturation state throughout the second and third subframes SF2 and SF3 of the odd frame. Further, the left shutter of the shutter glasses 18 is open during the odd frame period.
Meanwhile, in the even frame, before a lapse of time corresponding to the first subframe SF1 immediately after the right-eye data DATA (R) is written at the center of the liquid crystal panel 10, a liquid crystal LC at the center of the liquid crystal panel 10 is saturated and maintained at the saturation state throughout the second and third subframes SF2 and SF3 of the even frame. Further, the right shutter of the shutter glasses 18 is open during the even frame period.
The turn-on timing of the light sources BL, as shown in
3D cross-talk can be reduced by improving the response time of the liquid crystal display panel using the second embodiment shown in
As described above, the 3D image display device according to this invention controls the operations of the driving circuits at a frequency faster than an input frame frequency, divides one frame into N subframes, and repeatedly displays the same, so that all the liquid crystals are saturated. Further, all the light sources are turned off during the first N-1 subframes, all the light sources are turned on during the last subframe period, and the left and right shutters are alternately opened or shut on a unit frame by unit frame basis. Further, raising a light source driving current can compensate for potential deterioration of the brightness of a display surface resulting from blinking driving. Further, the 3D image display device of this invention can prevent 3D crosstalk by increasing the response time of liquid crystals and improve the performance of an MPRT without causing deterioration of the brightness of motion pictures, thereby significantly improving the display quality.
It will be apparent to those skilled in the art that various modifications and variations can be made in the 3D image display device of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2009-0134638 | Dec 2009 | KR | national |
| 10-2010-0030382 | Apr 2010 | KR | national |
