Patent Application
20250202510
The present disclosure relates to a waveguide link and, more particularly, to a 50 GB/S PAM4 bi-directional plastic waveguide link having carrier synchronization using a PI-based Costas loop.
A demand for a greater input/output (I/O) bandwidth in data sensors is ever increasing due to the explosive growth of network traffic. However, the conventional high-speed interconnects are struggling with the challenges in the functional and the economical aspects. Copper-based electrical links show their critical bandwidth limitation that is caused by a skin loss. Optical links require significant equipment costs for electrical/optical (E/O) and O/E conversion devices and a chip-to-fiber assembly in short-reach high-capacity links.
As an alternative for solving the problems of the conventional high-speed interconnects, recent researches present that plastic waveguide links showing the inherent low loss and wideband channel characteristic can be a promising solution for providing power-/cost-efficient high-speed interconnects. However, the conventional technologies show only a single waveguide transmission due to low confinement of a waveguide and a limited carrier synchronization requiring external local oscillator (LO) phase tuning.
The present disclosure for solving such a problem have an object to provide a 50 GB/S PAM4 bi-directional plastic waveguide link having carrier synchronization using a PI-based Costas loop.
According to an embodiment of the present disclosure, an RF receiver is suggested. The RF receiver may include a phase detector configured to detect the phase of a down-converted received signal using a clock signal, and a phase synchronization device configured to adjust the phase of the clock signal based on the detected phase.
Furthermore, the phase synchronization device may include a loop filter configured to determine a phase control value based on an output signal of the phase detector, and a phase adjuster configured to adjust the phase of the clock signal based on the determined phase control value.
Furthermore, the loop filter may be a digital loop filter (DLF). The phase synchronization device may include a sampler configured to sample the output signal of the phase detector based on a predetermined voltage reference value. The digital loop filter may be configured to determine the phase control value by accumulating sampling values output by the sampler.
Furthermore, the digital loop filter may be a secondary order digital loop filter, and may be configured to determine the phase control value by accumulating the sum of a current sampling value and a previous sampling value.
Furthermore, the loop filter may be an analog loop filter. The phase adjuster may be configured to adjust the phase of the clock signal in an analog domain.
Furthermore, the phase synchronization device may further include a multi-phase filter. The multi-phase filter may be configured to generate an in-phase (I) clock signal and a quadrature phase (Q) clock signal from a signal of a clock source and to provide the in-phase (I) clock signal and the quadrature phase (Q) clock signal to the phase adjuster.
Furthermore, the RF receiver may further include an in-phase (I) down converter mixer, a quadrature phase (Q) down converter mixer, and a multiplier. The in-phase (I) down converter mixer is configured to down-convert the received signal using the in-phase (I) clock signal which is phase-adjusted by the phase adjuster and converted into a carrier frequency by the multiplier. The quadrature phase (Q) down converter mixer is configured to down-convert the received signal using the quadrature phase (Q) clock signal which is phase-adjusted by the phase adjuster and converted into a carrier frequency by the multiplier.
Furthermore, the phase detector may be configured to generate an output signal that is proportional to a sinusoidal wave of two times (2θ) a phase offset θ between the received signal and the in-phase (I) clock signal, based on the down-converted received signal from the in-phase (I) down converter mixer and the down-converted received signal from the quadrature phase (Q) down converter mixer.
Furthermore, the multiplier may be disposed between the in-phase (I) down converter mixer and the quadrature phase (Q) down converter mixer, and the phase synchronization device, or may be disposed between the clock source and the phase synchronization device.
According to an embodiment of the present disclosure, an RF communication system is suggested. The RF communication system may include an RF transmitter configured to up-convert a transmission signal to a carrier frequency and transmit the transmission signal, an RF receiver configured to down-convert a received signal received on the carrier frequency and receive the received signal, a bi-directional plastic waveguide device configured to provide a channel for transmission of the transmission signal and a channel for reception of the received signal, and a microstrip-to-waveguide transition (MWT) configured to transfer a signal between the RF transmitter or the RF receiver and the bi-directional plastic waveguide device. The RF receiver may include a phase detector configured to detect the phase of the down-converted received signal using a clock signal, and a phase synchronization device configured to adjust the phase of the clock signal based on the detected phase.
Furthermore, the bi-directional plastic waveguide device may further include a first plastic waveguide unit and a second plastic waveguide unit each including a plastic waveguide and metal cladding that surrounds the plastic waveguide.
Furthermore, the MWT may include a first MWT unit for transferring the transmission signal from the RF transmitter to the first plastic waveguide unit and a second MWT unit for transferring the received signal from the second plastic waveguide unit to the RF receiver.
Furthermore, the bi-directional plastic waveguide device may include a metal shield disposed between the first and second plastic waveguide units.
According to the present disclosure, compared to a conventional technology, in light of a throughput distance and energy efficiency, it is possible to provide a 50 GB/S PAM4 bi-directional plastic waveguide link having carrier synchronization using a PI-based Costas loop, which has very excellent performance.
Furthermore, according to the present disclosure, technical effects in that power consumption is small and the design of a receiver can be facilitated by performing phase synchronization in the receiver without using a module, such as an ADC or a DSP, can be achieved.
Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same components have the same reference numerals as much as possible even if they are displayed in different drawings. Furthermore, in describing the present disclosure, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present disclosure, the detailed description thereof will be omitted.
Various aspects of the present disclosure are described below. Disclosures proposed herein may be implemented in wide and various forms, and it is to be understood that an arbitrary and specific structure, function, or both of them that are proposed herein are only exemplary. A person having ordinary knowledge in the art to which the present disclosure belongs will understand that one aspect proposed herein may be implemented independently of arbitrary other aspects proposed herein based on the disclosures proposed herein and two or more such aspects may be combined in various ways. For example, a device may be implemented or a method may be implemented by using an arbitrary number of aspects described herein. Furthermore, such a device may be implemented or such a method may be implemented in addition to one or more aspect described herein or by using another structure, a function, or a structure and a function other than these aspects.
According to the present disclosure, a 50 GB/S PAM4 bi-directional plastic waveguide link having carrier synchronization using a PI-based Costas loop is proposed. In an implementation example, such a link may be implemented as a 50 GB/S PAM4 bi-directional plastic waveguide link having carrier synchronization by using 70 GHz transmitter (Tx) and receiver (Rx) ICs in fan-out wafer level packaging (FOWLP) that is manufactured by a 28 nm CMOS process. Such a link may achieve a figure of merit (FoM) of 2.8 pJ/b/m that shows the latest performance in light of a throughput distance and energy efficiency.
As illustrated in
The RF chip 100 and the MWTs 140 and 141 may be implemented on a printed circuit board (PCB) 180. The RF chip 100 may include an RF transmitter 110, an RF receiver 120, and a phase locked-loop (PLL) 130. The RF transmitter (Tx) 110 may be configured to up-convert a transmission signal to a carrier frequency and transmit the transmission signal. The RF receiver (Rx) 120 may be configured to down-convert a received signal received on a carrier frequency and receive the received signal. The E-TUBE device 150 may provide a channel for transmission of a transmission signal and a channel for reception of a received signal. To this end, the E-TUBE device 150 may include a first plastic waveguide unit 151 for transmission and a second plastic waveguide unit 152 for reception. The MWT may be configured to transfer signals between the RF transmitter 110 or the RF receiver 120 and the E-TUBE device 150. To this end, the MWT may include a first MWT unit 140 for transferring a transmission signal from the RF transmitter 110 to the first E-TUBE unit 151 and a second MWT unit 141 for transferring a received signal from the second E-TUBE unit 152 to the RF receiver 120. Furthermore, although not indicated by a separate reference numeral, the RF chip 100-2 may include corresponding components for transmission to and reception with the RF chip 100 through the E-TUBE device 150 as illustrated in
In an implementation example, the carrier frequency may be a 70 GHz frequency band. An input signal may be transmitted and received (160) in a bandwidth of ˜25 GHz on the basis of 70 GHz through the E-TUBE device 150. The PLL 130 may provide the RF transmitter 110 and the RF receiver 120 with a clock signal from a clock source. In such an implementation example, the PLL 130 may provide an external clock signal of 17.5 GHZ. The RF transmitter 110 and the RF receiver 120 may include multipliers 113 and 123, respectively, each of which may convert a clock signal provided thereto into a carrier frequency. In such an implementation example, the multipliers 113 and 123 may each be implemented as a frequency quadrupler (×4) in order to generate a 70 GHz local oscillation (LO) signal from the clock signal of 17.5 GHz. A phase synchronization device 124 in the RF receiver 120 may track the phase offsets of carrier signals that are generated from independent clock sources, which will be described later.
Performance of the waveguide channel and the transceivers (Tx and Rx) may be determined by a link budget for satisfying a target bit-error rate (BER). An exemplary link budget of the bi-directional plastic waveguide link according to the present disclosure has been illustrated in
As described above, the MWTs 140 and 141 may efficiently transfer energy to a transmission line from a waveguide and from the waveguide to the transmission line. To this end, as illustrated in
As illustrated in
In an implementation example, the E-TUBE units 151 and 152 may each be a rectangle dielectric waveguide on which a metal film has been laminated (i.e., surrounded by the metal cladding 154), and may show a frequency-independent insertion loss of 5 dB/m and group delay of 4 ns/m. The metal cladding 154 may confine a radio wave and prevent electromagnetic leakage. As illustrated in
Meanwhile, in order to maximize an output signal-to-noise ratio (SNR), coherent demodulation requires carrier synchronization. However, the phase offsets of carrier signals are generated from the generation of independent LOs of the Tx/Rx, and phase delay through the E-TUBE channel causes a reduction of the SNR. In a conventional technology, a DSP-based baseband circuit has been used to overcome such a reduction, but great power consumption of such a circuit at a high speed limits a common use.
Accordingly, according to the present disclosure, a low power synchronization method based on a Costas loop is suggested.
The Costas loop may be implemented within the RF receiver 120. As illustrated in
Specifically, the multiplier 123 may convert the phase-adjusted in-phase (I) clock signal and the phase-adjusted quadrature phase (Q) clock signal output from the phase synchronization device 124 to a carrier frequency ω0 and transfer them to the in-phase (I) down converter mixer 210 and the quadrature phase (Q) down converter mixer 211, respectively. Or, the multiplier 123 may convert a clock signal from the clock source to the carrier frequency ω0 and transfer it to the phase synchronization device 124. The phase synchronization device 124 may perform phase adjustment on the clock signal converted into the carrier frequency. In other words, according to an implementation example, the multiplier 123 may be disposed between the in-phase (I) down converter mixer 210 and the quadrature phase (Q) down converter mixer 211, and the phase synchronization device 124, or may be disposed between the clock source and the phase synchronization device 124.
The in-phase (I) down converter mixer 210 may generate a demodulation output that is proportional to cos(θ) by down-converting an input signal Din using an in-phase (I) clock signal LOI. The quadrature phase (Q) down converter mixer 211 may generate a demodulation output that is proportional to sine(θ) by down-converting the input signal Din using a quadrature phase (Q) clock signal LOQ. In this case, θ is a phase offset between an RF received signal and the in-phase (I) clock signal LOI. The phase detector 220 may be configured to generate an output signal VPD that is proportional to a sinusoidal wave of two times (2θ) (i.e., sin (20)) the phase offset θ between the RF received signal and the in-phase (I) clock signal in a voltage domain, based on a down-converted received signal (i.e., the demodulation output) from the in-phase (I) down converter mixer 210 and a down-converted received signal (i.e., the demodulation output) from the quadrature phase (Q) down converter mixer 211. A corresponding transfer function of the phase detector 220 has been exemplified in
The loop filter 250 may determine a phase control value based on the output signal VPD of the phase detector 220. The phase adjuster (PI) 260 may adjust the phases of clock signals (i.e., the in-phase (I) clock signal and the quadrature phase (Q) clock signal) based on the determined phase control value.
In an implementation example, the loop filter 250 may be a digital loop filter (DLF). In such a case, the phase synchronization device 124 may include the sampler 240. The sampler 240 may be configured to sample the output signal VPD of the phase detector 220 based on a predetermined voltage reference value Vref. In an implementation example, the sampler 240 may be a 1-bit sampler, and may output a sampling value having a 1-bit size, that is, 0 or 1, by sampling the output of the phase detector 220 based on the voltage reference value Vref using an asynchronous low frequency clock (Async clk). The digital loop filter (DLF) 250 may be configured to determine a phase control value by accumulating the sampling values that are output by the sampler 240. In an implementation example, the digital loop filter 250 may be a secondary order digital loop filter (DLF). The secondary order DLF has been exemplified in
In another implementation example, the loop filter 250 may be an analog loop filter. In such a case, the phase synchronization device 124 does not include the sampler 240. The phase adjuster 260 may be configured to adjust the phase of a clock signal in an analog domain based on a phase control value that has been determined by the analog loop filter 250. In other words, in such an implementation example, the phase synchronization device 124 may be implemented to perform phase regulation in the analog domain.
As described above, the phase adjuster (PI) 260 may be configured to adjust the phase of a clock signal (in such an example, a 17.5 GHz clock signal) based on a phase control value that has been determined by the loop filter 250. The PI-based Costas loop according to the present disclosure may obtain a low jitter LO signal, compared to a VCO-based Costas loop. This does not cause an additional jitter that occurs from VCO couplings of multi-channel communication. The 17.5 GHz clock signal having the phase adjusted by the phase adjuster 260 may be multiplied by a frequency (in such an example, as much as 4 times by the frequency quadrupler (×4)) by the multiplier 123 in order to generate a clock signal (in such an example, a 70 GHz LO signal) converted into a carrier frequency, or the phase adjuster 260 may perform phase adjustment on the clock signal (i.e., the 70 GHz LO signal) converted into a carrier frequency by the multiplier 123.
The multi-phase filter (PPF) 270 may generate multi-phase signals having several phases from a received signal. In an implementation example, the multi-phase filter 270 may be configured to generate an in-phase (I) clock signal and a quadrature phase (Q) clock signal having two different phases (in such an example, an in-phase (I) and a quadrature-phase (Q)) from a clock signal (in such an example, 17.5 GHz clock signal) from the clock source and to provide the phase adjuster 260 with the in-phase (I) clock signal and the quadrature phase (Q) clock signal. In such a case, the phase adjuster 260 may generate the phase-adjusted in-phase (I) clock signal and the phase-adjusted quadrature phase (Q) clock signal. These signals may be converted into a carrier frequency through the multiplier 123, and may be input to the in-phase (I) down converter mixer 210 and the quadrature phase (Q) down converter mixer 211 again, respectively.
Or, as described above, in another implementation example, the multiplier 123 (i.e., the frequency quadrupler) may be disposed between the PLL 130 and the phase synchronization device 124. In such a case, a clock signal (in such an example, the 17.5 GHz clock signal) from the PLL 130 may be converted into a carrier frequency (in such an example, 70 GHz) by the multiplier 123, and may be provided to the multi-phase filter 270 of the phase synchronization device 124. Furthermore, in such a case, the multi-phase filter 270 may be configured to generate an in-phase (I) clock signal and a quadrature phase (Q) clock signal from the clock signal converted into the carrier frequency and to provide the in-phase (I) clock signal and the quadrature phase (Q) clock signal to the phase adjuster 260. Accordingly, the phase synchronization device 124 may adjust the phase of the clock signal in a carrier frequency band. The phase-adjusted clock signal may be directly transferred to the down-converting mixer 122.
As illustrated in
The 70 GHz transceiver (Rx and Tx) may adopt architecture for a direct conversion in order to use the wideband characteristics of the E-TUBE channel.
As illustrated in
As illustrated in
In an implementation example, the frequency quadruplers 113 and 123 may be implemented as two frequency doubler (2×) chains. The two stages of push-push frequency doubler chains may generate 70 GHz clock signals, and buffers thereof can suppress an unwanted harmonic frequency by using LC filters. Thereafter, finally, an LO output may be distributed to the mixers 111, 210, and 211 of the Tx and Rx. A quadrature phase shift of the LO may be implemented by using physical delay of a distribution line, and is insensitive to a PVT change.
As illustrated in
Comparisons between performance of a conventional technology and performance of an E-TUBE link according to the present disclosure are listed in the following table.
As illustrated in Table 1, the E-TUBE link according to the present disclosure may achieve the FoM of 2.8 pJ/b/m that shows performance having an unprecedented level in light of the results of a throughput distance and energy efficiency, compared to the conventional technology. Additionally, in order to replace the existing interconnects in high throughput links including 400/800 GB/S communications, the E-TUBE link may present a high-speed I/O interface that complies with observes 50GBASE-CR and a 50 GB/S standard over twisted pair.
The description of the proposed embodiments is provided so that a person having ordinary knowledge in an arbitrary technical field of the present disclosure can use or implement the present disclosure. Various modifications of such embodiments will be evident to a person having ordinary knowledge in the art of the present disclosure. Common principles defined herein may be applied to other embodiments without departing from the scope of the present disclosure. Accordingly, the present disclosure should not be limited to the proposed embodiments, but should be interpreted in the widest range that is consistent with the proposed principles and new characteristics.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2021-0124453 | Sep 2021 | KR | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/KR2022/013990 | 9/19/2022 | WO |
