NSF Award
9360144
9360144 Kaplan Superconductive circuits are proving effective in processing very high speed data streams. For example, HYPRES has demonstrated an 8-bit analog-to-digital converter (ADC) with 4.4 effective bits at 4 GHz, and 2 effective bits at 7 GHz. We project an ADC performance of 6 effective bit at 10 GHz. However, the ability of superconductive circuits to work at such high data rates renders it difficult to communicate with room-temperature circuitry. We address this problem in this proposal. We propose to design, fabricate and test a demultiplexer circuit to divert high-speed data into several lower-speed channels. Each channel will be clocked at a rate low enough for conventional circuits. The demultiplexer will be compatible with our ADC, and will be general enough to be used in other applications where the data rate is too high for conventional circuits. During Phase I, proof of principle will be demonstrated with a 1:4 demultiplexer. The design will be modular so that extension to a circuit with a larger demultiplexer ratio is be straightforward. In Phase II, the operation of the demultiplexer will be demonstrated as part of a high-speed monolithic ADC chip. ***
