A FOUR-QUADRANT MODULATION TECHNIQUE TO EXTEND MODULATION INDEX RANGE FOR MULTILEVEL SELECTIVE HARMONIC ELIMINATION / COMPENSATION

Abstract

Four quadrant modulation techniques that can synthesize a full range solution or a full modulation index range are provided. Such techniques can be applied to a DC/AC inverter, an AC to DC rectifier, and AC/DC/ AC topology. The techniques can also be applied to a neutral point clamped (NPC) topology, flying capacitor (FLC) topology, cascaded H-bridge (CHB) topology, modular multilevel topology, modular multilevel converters, and multimodule converters.

Description

BACKGROUND OF THE INVENTION

Multilevel converters/inverters, including neutral point clamped (NPC), flying capacitor (FLC), cascaded H-bridge (CHB) and modular multilevel converters/inverters, have drawn attention in recent years, especially in medium and high voltage/power applications, such as motor drive systems, traction, PV inverters and battery charging stations. Their advantages include high reliability, low voltage stress, low electromagnetic interference (EMI) and low common-mode voltages. Pulse width modulation (PWM) modulation techniques, including selective harmonic elimination (SHE) and selective harmonic compensation (SHC), have been applied in multilevel converters/inverters to achieve high performance with low switching frequencies in various applications such as static synchronous compensators and active power filters (APF). In these techniques, the transcendental equations to be solved are developed based on voltage/current references, total harmonic distortion (THD) requirements and other objectives with the help of Fourier transformation.

Techniques including iterative numerical algorithms, online calculations and the complete solution have been proposed to solve the transcendental equations. However, the effective modulation index range of these techniques has been shown to be very narrow and their applications limited. Other techniques have been used to extend modulation ranges, but have been shown to have increased switching frequency and switching power loss, and have difficulty meeting harmonic requirements.

BRIEF SUMMARY

Embodiments of the present invention seek to solve or mitigate one or more problems of the prior art. Embodiments of the present invention include a four quadrant modulation technique that can synthesize a full range solution or a full modulation index range.

A four-quadrant modulation method according to an embodiment of the present invention can include determining switching angles θ_r and θ_f without any limitations, wherein θ_r is a rising switching angle and θ_f is a falling switching angle; detecting switching angles θ_r and θ_f with undesired states and transforming them into practical states and leaving remaining switching angles θ_r and θ_f unchanged; and inputting the switching angles θ_r and θ_f and the phase information into a logic circuit to generate driving signals.

Embodiments of the present invention can be applied to a DC/AC inverter, an AC to DC rectifier, AC/DC/AC topology, voltage source inverters, current source inverters, rectifiers, STATCOM, and APF. Embodiments of the present invention can be applied to any topology with multilevel voltage or current output without voltage limitations. Embodiments of the present invention can be applied to a neutral point clamped (NPC) topology, flying capacitor (FLC) topology, cascaded H-bridge (CHB) topology, modular multilevel topology, modular multilevel converters, and multimodule converters. Embodiments of the present invention can be applied to multilevel selective harmonic elimination (SHE), multilevel selective harmonic elimination and compensation (SHC), selective harmonic mitigation (SHM), and selective harmonic optimization (SHO). Determining the phase of the grid can be accomplished using a phase locked loop. The switching angles θ_r and θ_f with undesired states can be transformed to practical states by assigning new switching angles θ_r′ and θ_f′, wherein θ_r′=−π+θ_f and θ_f′=π+θ_r′. In addition, the switching angles θ_r and θ_f with undesired states can be transformed to practical states by assigning new switching angles θ_r′ and θ_f′, wherein θ_r′=π+θ_f and θ_f′=−π+θ_r′.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the typical topology and waveforms of a 3-cell CHB system.

FIG. 2(a) shows the range of fundamental voltage V^P_{HB_1} in a voltage phasor diagram (per unit) of one HB with θ_r ∈ [0, π/2] and θ_f∈ [π/2, π].

FIG. 2(b) shows the range of 3^rd voltage V^P_{HB_3} in a voltage phasor diagram (per unit) of one HB with θ_r ∈ [0, π/2] and θ_f∈ [π/2, π].

FIG. 2(c) shows the range of 5^th voltage V^P_{HB_5} in a voltage phasor diagram (per unit) of one HB with θ_r ∈ [0, π/2] and θ_f∈ [π/2, π].

FIG. 3 shows the fundamental voltage phasor diagram (per unit) of one HB with θr ∈ [−π, π] and θf ∈ [−π, π].

FIG. 4(a) shows solution trajectories of a 7-level cascaded inverter with a four-quadrant modulation method according to an embodiment of the present invention.

FIG. 4(b) shows the difference between the reference and the actual output voltage resulting from solution obtained by a four-quadrant modulation method according to an embodiment of the present invention

FIG. 5 is a graph of modulation index range versus number of cells with different modulation techniques.

FIG. 6(a) shows all possible switching states of a four-quadrant modulation method according to an embodiment of the present invention.

FIG. 6(b) shows undesired switching states of a four-quadrant modulation method according to an embodiment of the present invention

FIG. 7 shows the digital implementation of a four-quadrant switching angle modulation technique for each half-bridge according to an embodiment of the present invention.

FIG. 8 is a flow chart to determine the inductance range where a grid current after compensation can meet the constraints on fundamental compensation, harmonic compensation and undesired harmonic injection.

FIG. 9(a) is a graph showing an example of a design procedure for inductance with a nonlinear load harmonic current envelope and harmonic standard.

FIG. 9(b) is a graph showing an example of a design procedure for inductance with derived constraints and a CHB harmonic envelope.

FIG. 10 shows the topology of a simulation experiment according to an embodiment of the present invention.

FIG. 11 shows a proof of concept test plan for the present invention.

FIGS. 12(a) to 12(d) show experimental and simulation results of a first test after applying a four-quadrant switching angle modulation technique according to the present invention.

FIGS. 13(a) to 13(d) show experimental and simulation results of a first test after applying a conventional modulation technique.

FIGS. 14(a) to 14(d) show experimental and simulation results of a second test after applying a four-quadrant switching angle modulation technique according to the present invention.

FIGS. 16(a) to 16(d) show experimental and simulation results of a third test after applying a four-quadrant switching angle modulation technique according to the present invention.

FIGS. 15(a) to 15(d) show experimental and simulation results of a third test after applying a four-quadrant switching angle modulation technique according to the present invention.

FIG. 17 is a graph showing derived constraints and CHB harmonic envelope of test 1.

FIG. 18 is a graph showing derived constraints and CHB harmonic envelope of test 2.

FIGS. 19(a) is a graph showing a nonlinear load harmonic current envelope and harmonic standard of the inductor design procedure in test 3.

FIGS. 19(b) is a graph showing derived constraints and CHB harmonic envelope standard of the inductor design procedure in test 3.

FIGS. 20 (a) is a graph showing a nonlinear load harmonic current envelope and harmonic standard of the inductor design procedure in test 4.

FIGS. 20(b) is a graph showing derived constraints and CHB harmonic envelope standard of the inductor design procedure in test 4.

DETAILED DESCRIPTION

Embodiments of the present invention include a four quadrant modulation technique that can synthesize a full range solution or a full modulation index range. In an embodiment, a four-quadrant modulation method can include determining the phase of a grid; determining switching angles θ_r and θ_f without any limitations, wherein θ_r is a rising switching angle and θ_f is a falling switching angle; detecting switching angles θ_r and θ_f with undesired states and transforming them into practical states and leaving remaining switching angles θ_r and θ_f unchanged; and inputting the switching angles θ_r and θ_f and the phase information into a logic circuit to generate driving signals.

FIG. 1 shows the typical topology and waveforms of a 3-cell CHB system. Referring to FIG. 1, a 3-cell cascaded H-bridge (CHB) is tied to a grid, which has nonlinear loads. The load current is i_NL; the grid current is i_g and the current injected to the grid from the CHB is i_CHB. The output voltage of the CHB is v_CHB. The coupling inductor between the CHB and the grid has an inductance of L_m. It is well known that, with different modulation techniques, the inductor design is also different. This application will discuss inductor design between sinusoidal pulse width modulation (SPWM) and SHE/SHC. Based on SHE/SHC applications, the effects of inductance on both compensation capacity and the attenuation of undesired harmonics will be analyzed. Guidelines for the inductor design in multilevel SHE/SHC applications will be proposed to ensure that there is compliance with harmonic standards.

In FIG. 1, half-wave symmetry modulation is used to compensate the odd harmonics in a CHB topology. For one HB, the output voltage v_HB(t) can be expressed as,

$\begin{array}{cc}{v}_{\mathrm{HB}}\left(t\right)=\{\begin{array}{cc}E,& 2n\pi +{\theta }_r<{\omega }_gt<2\mathrm{n\pi }+{\theta }_f\\ -E,& \left(2n+1\right)\pi +\theta \text{?}<{\omega }_gt<\left(2n+1\right)+\theta \text{?}\\ 0,& \mathrm{otherwise}\end{array}\text{?}\text{indicates text missing or illegible when filed}& \left(1\right)\end{array}$

Where, E is the DC bus voltage of a HB; ω_g is the fundamental angular frequency, which is 2π(60) rad/s; θr and θ_f are the switching angles at rising and falling transitions of a HB. The Fourier series for v_HB(t) can be expressed as:

$\begin{array}{cc}{v}_{\mathrm{HB}}\left(t\right)=\sum _{\text{?}}^{\infty }\left(a_{\mathrm{HB}\_h}\cos \left(h\omega t\right)+b_{\mathrm{HB}\_h}\sin \left(h\omega t\right)\right)& \left(2\right)\\ \{\begin{array}{c}{a}_{\mathrm{HB}\_b}=-\frac{2E}{\pi h}\left(\sin \left(h{\theta }_r\right)-\sin \left(h{\theta }_f\right)\right)\\ a_{\mathrm{HB}\_b}=-\frac{2E}{\pi h}\left(\cos \left(h{\theta }_r\right)-\cos \left(h{\theta }_f\right)\right)\end{array}\text{?}\text{indicates text missing or illegible when filed}& \left(3\right)\end{array}$

where h is the harmonic order, and h=1, 3, 5, . . .

The complex HB output voltage V_{HB_h} of the h order harmonic is defined as: V_{HB_h}=a_{HB_h}+jb_{HB_h}, then the magnitude of each order harmonic is |V_{HB_h}| and the initial phase is ∠V_{HB_h}. The expression of V_{HB_h} can be rewritten as:

$\begin{array}{cc}{V}_{\mathrm{HB}\_h}=\frac{2E}{\pi h}\left(\left(-\sin \left(h{\theta }_r\right)+j\cos \left(h{\theta }_r\right)\right)-\left(-\sin \left(h{\theta }_f\right)+j\cos \left(h{\theta }_f\right)\right)\right)& \left(4\right)\end{array}$

Based on Euler equation, −sin(hθ)+jcos(hθ)=ej(hθ+π/2), (4) can be rewritten as:

$\begin{array}{cc}{V}_{\mathrm{HB}\_h}=\frac{2E}{\pi h}\left(e^{j\left({\mathrm{hd}}_r+\frac{\pi }{2}\right)}-e^{j\left({\mathrm{hd}}_f+\frac{\pi }{2}\right)}\right)& \left(5\right)\end{array}$

If the base voltage for the h^th order harmonic is E/h, (5) can be rewritten in per unit:

$\begin{array}{cc}{V}_{\mathrm{HB}\_h}^p=\frac{2}{\pi }\left(e^{j\left(h{\theta }_r+\frac{\pi }{2}\right)}-e^{j\left(h{\theta }_f+\frac{\pi }{2}\right)}\right)& \left(6\right)\end{array}$

The voltage phasor diagrams can be developed based on (6). The voltage phasor, V^P_{HB_h}, is determined by two vectors,

$\frac{2}{\pi }e^{j\left(h\theta r+\frac{\pi }{2}\right)}\mathrm{and}\frac{2}{\pi }e^{j\left(h\theta f+\frac{\pi }{2}\right)}.$

As shown in FIG. 2, if θ_r ∈ [0, π/2] and θ_f∈[π/2, π] [1],[19], the ranges of phasors of

$e^{j\left(h\theta r+\frac{\pi }{2}\right)}$

are shown by the arcs in FIG. 2 (a), (b), and (c) for h=1, 3, 5. The shaded region represents the range of phasor V_HB-h, and it is derived by the ranges of the phasors

$\frac{2}{\pi }e^{j\left(h\theta r+\frac{\pi }{2}\right)}\mathrm{and}\frac{2}{\pi }e^{j\left(h\theta f+\frac{\pi }{2}\right)}.$

In FIG. 5(c), for the 5^th order harmonic, because both the ranges of 5θ_r and 5θ_f exceed 360 , the range of V_{hb_5} covers the whole area inside the range circle with actual radius 4E/5π. Similarly, when h>5, all voltage phasors cover the whole range circles with actual radius 4E/hπ (not shown in FIG. 2). The actual amplitudes of the voltage phasors in FIG. 2 should be multiplied by E/h. As shown in FIG. 2 (a), because switching angles θ_r and θ_f have the limited ranges [0, π/2] and [π/2,π], the range of the synthesized fundamental voltage phasor V_{HB_1} is limited, so it cannot cover the full modulation index range. The same rule can also be applied to the analysis of the synthesized 3^rd order voltage harmonic V_{HB_3}. Extending the range of θ_{r and} θ_f can therefore increase the ranges of the synthesized phasors and the modulation index range. FIG. 3 shows the range of the fundamental voltage phasor with θ_r and θ_f extended to [−π, π]. Because both the trajectories

$\frac{2}{\pi }e^{j\left(h\theta r+\frac{\pi }{2}\right)}\mathrm{and}\frac{2}{\pi }e^{j\left(h\theta f+\frac{\pi }{2}\right)}$

cover the full angle range, the synthesized voltage phasor V_{HB_1} covers the whole range circle with actual radius 4E/π. Because all voltage harmonic phasors fully cover the range circles, they are not shown.

FIG. 2 (c) and FIG. 3 shows that if there is no limitation on range of θ_{r and} θ_f, then two phasors

$\frac{2}{\pi }e^{j\left(h\theta r+\frac{\pi }{2}\right)}\mathrm{and}\frac{2}{\pi }e^{j\left(h\theta f+\frac{\pi }{2}\right)}$

can synthesize any phasor within the circle with a radius of 4/π. This conclusion can be proved by algebraic method. Define V_{REF_h} as

$V_{\mathrm{REF}\_h}=\frac{4}{\pi }R_{\mathrm{REF}}e^j{\theta }_{\mathrm{REQ}},$

where R_REF<1 is a non-negative real number related to the magnitude of V_{REF_h}, θ_REF ∈ [0, 2π] is the phase of V_{REF_h.} and V_{REF_h} can represent any phasor inside the circuit with a radius of 4/π. If the value of hθ_r and hθ_f is as below:

$\{\begin{array}{c}{\theta }_M=\arccos \left(R_{\mathrm{REF}}\right)\\ h{\theta }_r=\left({\theta }_{\mathrm{REF}}-{\theta }_M\right)-\frac{\pi }{2}\\ h{\theta }_f=\left(-\pi +{\theta }_{\mathrm{REF}}+{\theta }_M\right)-\frac{\pi }{2}\end{array},$

Then the synthesized phasor

$\left(\frac{2}{\pi }e^{j\left(h{\theta }_r+\frac{\pi }{\text{?}}\right)}-\frac{2}{\pi }e^{j\left(h{\theta }_f+\frac{\pi }{2}\right)}\right)$ $\text{?}\text{indicates text missing or illegible when filed}$

equals to V_{REF_h} as proved below:

$\begin{array}{cc}\begin{array}{c}\frac{2}{N\pi }e^{j\left(h{\theta }_r+\frac{\pi }{2}\right)}-\frac{2}{N\pi }e^{j\left(h{\theta }_f+\frac{\pi }{2}\right)}=\frac{2}{N\pi }\left(e^{j\hspace{1em}\left({\theta }_{\text{?}}-{\theta }_M\right)}-e^{j\left(-\pi +{\theta }_{\text{?}}+{\theta }_M\right)}\right)\\ =\frac{2}{N\pi }\left(e^{j\left({\theta }_{\text{?}}-{\theta }_M\right)}-e^{-j\pi }e^{j\left({\theta }_{\text{?}}+{\theta }_M\right)}\right)\\ =\frac{2}{N\pi }\left(e^{j\left({\theta }_{\text{?}}-{\theta }_M\right)}+e^{j\left({\theta }_{\text{?}}+{\theta }_M\right)}\right)\\ =\frac{2}{N\pi }\left(\begin{array}{c}\cos \left({\theta }_{\mathrm{REF}}-{\theta }_M\right)+j\sin \left({\theta }_{\mathrm{REF}}-{\theta }_M\right)+\\ \cos \left({\theta }_{\mathrm{REF}}+{\theta }_M\right)+j\sin \left({\theta }_{\mathrm{REF}}+{\theta }_M\right)\end{array}\right)\\ =\frac{2}{N\pi }\left(\begin{array}{c}2\cos \left({\theta }_{\mathrm{REF}}\right)\cos \left({\theta }_M\right)+\\ j2\sin \left({\theta }_{\mathrm{REF}}\right)\cos \left({\theta }_M\right)\end{array}\right)\\ =\frac{4}{N\pi }\cos \left({\theta }_M\right)\left(\cos \left({\theta }_{\mathrm{REF}}\right)+j\sin \left({\theta }_{\mathrm{REF}}\right)\right)\end{array}& \\ \text{?}\text{indicates text missing or illegible when filed}& \end{array}$

After θ_r and θ_f are extended to [−π, π], compared with conventional single quadrant switching angles within [0, π/2] and [π/2, π], the switching angles are four quadrants. The four quadrants switching angles can synthesize a full modulation index while the single quadrant switching angles cannot.

To verify the four quadrants switching angle modulation technique according to an embodiment of the present invention, the modulation technique is applied to the 3-cell, 7-level cascaded multilevel inverter of FIG. 1 with selective harmonic elimination (SHE). The references of the 3rd and 5th harmonics are set to zero, and the reference of the fundamental voltage changes from 0 to 3E with phase equal to zero degree. Optimized toolbox with generic algorithm (GA) in MATLAB is used to find the switching angle solutions. The objective function (OF) is set as OF=|E₁|+|E₃|+|E₅|, where E_h is the difference between the voltage reference and the actual CHB voltage resulting from the obtained solutions. For the fundamental voltage, the per unit differences of the real and imaginary parts of the fundamental voltage are defined as E_{a_1}=Re(V_{CHB_1}−V_{Ref_1})/(NE), and E_{b_1}=IM(V_{CHB_1}−V_{Ref_1})/(NE), where V_{CHB_1} is the actual fundamental output voltage of the CHB, V_{Ref_1} is the fundamental reference voltage and N=3 is the number of cells. Because the harmonic voltage reference is zero, the per unit differences of harmonic voltages are defined as E_a-h=RE(V_{CHB_h})(NE/h), and E_{b_h}=Im(V_{CHB_h})(NE/h), where V_{CHB_h} is the actual harmonic output voltage of the CHB. From the FIG. 4(a), a four-quadrant modulation according to the present invention can find the solutions within the whole voltage range [0, 3E] and the per-unit error is less than 5%. On the other hand, with conventional single quadrant switching angle modulation technique, the modulation is only valid for [2.10E, 2.67E] (the shaded area). For this 3-cell, 7-level cascaded multilevel inverter, the four-quadrant switching angle modulation technique according to an embodiment of the present invention can therefore expand the modulation index range by more than five times compared with conventional techniques.

A comparison between the four quadrants switching angle modulation according to the present invention and other conventional modulation techniques is shown in FIG. 5. FIG. 5 shows the relationship of the modulation index range in percentages, which is defined as (Actual Modulation index range)/(Full Modulation index range), versus the number of HB cells of the CHB with different modulation techniques. Here, the Full Modulation index range is from 0 to NE. In FIG. 5, all the modulation techniques aim to eliminate the low order harmonics and control the amplitude of the fundamental component. For the variable DC modulation technique, DC-link voltage of each HB can vary from 0.5E to E. FIG. 5 shows that four-quadrant switching angle modulation techniques according to the present invention can always achieve a full modulation index range; while for other modulation techniques, increasing the number of HB cells reduces the modulation index range.

In a HB, depending on the relationship of θ_r, θ_f and the 0° , the number of the switching states is equal to P₃³=6. All possible switching states are shown in FIG. 6 (a). In the implementation, a microcontroller (MCU) is used to differentiate each switching state and generate the correspondent driving signals.

|θ_r−θ_f|>π is not realizable with a HB, but theoretically it could happen with four-quadrant switching angle modulation techniques according to the present invention as shown by state 3s and state 4s in FIG. 6 (b).

Since they cannot be realized using a HB, they are undesired states. To avoid these undesired switching states, |θ_r−θ_f|<π can be used as a constraint in switching angle calculations, but this would complicate the calculations. This problem can be avoided by reassigning new switching angles θ_r′ and θ_f′ as in (7) for state 3s and (8) for state 4s.

$\begin{array}{cc}\{\begin{array}{c}{\theta }_r^{\prime }=-\pi +{\theta }_j\\ {\theta }_f^{\prime }=\pi +{\theta }_r\end{array}& \left(7\right)\\ \{\begin{array}{c}{\theta }_r^{\prime }=\pi +{\theta }_f\\ {\theta }_f^{\prime }=-\pi +{\theta }_r\end{array}& \left(8\right)\end{array}$

In (7) for state 3s, the ranges of new switching angles are: θ_r′∈[−π, 0] and θ_f′∈[0, π]. Because θ_f′−θ_r′=(θ_r−θ_f)+2π∈[0, π], the new switching state will belong to state 3.

The new synthesized voltage phasor V_{HB_h}′ with the reassigned switching angles is identical to the original V_{HB_h}. This can be proved in (9) because harmonic order h is odd and e^−jhπ=e^jhπ=−1:

$\begin{array}{cc}\begin{array}{c}{V}_{\mathrm{HB}\_h}^{\prime }=\frac{2E}{\pi h}\left(e^{j\left(\text{?}+\frac{\pi }{2}\right)}-e^{j\left(\text{?}+\frac{\pi }{2}\right)}\right)\\ =\frac{2E}{\pi h}\left(e^{j\left(h\left(\text{?}+{\theta }_f\right)+\frac{\text{?}}{2}\right)}-e^{j\left(h\left(\text{?}\right)+\frac{\pi }{2}\right)}\right)\\ =\frac{2E}{\pi h}\left(e^{-\text{?}}e^{j\left({\text{?}}_f+\frac{\pi }{2}\right)}-e^{j\text{?}}e^{j\left(\text{?}+\frac{\text{?}}{2}\right)}\right)\\ =\frac{2E}{\pi h}\left(e^{j\left(\text{?}+\frac{\pi }{2}\right)}-e^{j\left(\text{?}+\frac{\text{?}}{2}\right)}\right)\\ =V_{\mathrm{HB}}\left(h\right)\end{array}& \left(9\right)\\ \text{?}\text{indicates text missing or illegible when filed}& \end{array}$

A similar analysis can be applied to state 4s. The ranges of new switching angles are θ_{r′ ∈ [}0, π] and θ_f′ ∈ [−π, 0]. Because (θ_r′−θ_f)=(θ_f−θ_r)+2π∈[0, π], the new switching state will belong to state 4.

The new synthesized phasor V_{HB_h}′ is identical to the original V_{HB_h}, as proved in (10):

$\begin{array}{cc}{V}_{\mathrm{HB}\_h}^{\prime }=\frac{2E}{\pi h}\left(e^{j\left(\text{?}+\frac{\text{?}}{2}\right)}-e^{j\left(\text{?}+\frac{\pi }{2}\right)}\right)=\frac{2E}{\pi h}\left(e^{j\left(\text{?}+\frac{\pi }{2}\right)}-e^{j\left(\text{?}+\frac{\pi }{2}\right)}\right)=V_{\mathrm{HB}\_h}\text{?}\text{indicates text missing or illegible when filed}& \left(10\right)\end{array}$

The implementation of a four-quadrant switching angle modulation technique according to an embodiment of the present invention is shown in FIG. 7 for each HB. There are three inputs: grid voltage v_g(t), θ_r and θ_f, and the four driving signals: g1, g2, g3 and g4. Block 1 is the PLL block that obtains the phase information of v_g(t); Block 2 detects state 3s and state 4s and converts them to state 3 and state 4 using (7) and (8), respectively; and Block 3 uses the phase information and switching angles to generate driving signals.

It should be noted that, in FIG. 6 (a), different switching states may generate identical waveforms. For example, state 1 and state 6, or state 2 and state 5 can generate identical waveforms. This indicates that duplicated solutions can exist in four-quadrant switching angle modulation techniques according to the present invention. Because this does not have any negative impacts to the implementation or calculations, it will not be discussed in detail.

Four-quadrant switching angle modulation techniques of the present invention can be applied to different grid applications such as harmonic elimination, harmonic mitigation and harmonic compensation, etc.

In FIG. 1, inductor L_m's design is critical because it has significant impact on power density, compensation capacity and current quality of the system. With the SPWM technique, high inductances can reduce undesired switching harmonics from being injected into the power grid, but high inductances also decrease compensation current capacity.

Therefore, the upper and lower bounds of the inductance are calculated based on compensation capacity and attenuation requirements for switching harmonics, respectively. In multilevel SHE/SHC, the inductor design process is similar, but the values of the bounds are different from the SPWM technique.

In the following paragraphs, inductor design constraints based on fundamental component compensation will be discussed. Next, the relationship between inductance L_m and the injected CHB current harmonic spectrum envelope is analyzed. Third, based on the injected CHB current harmonic spectrum envelope, inductor design constraints for both controllable harmonics (which are related to compensation capacity) and uncontrollable harmonics (which are related to the attenuation of undesired harmonics) are discussed, respectively. Finally, an inductor design procedure is proposed based on all of these constraints.

This application will only discuss grid-tied SHC. The generalized solution can be applied to all grid-tied applications, such as SHE and all offline applications.

The output voltage of the CHB is the sum of all HB voltages, so the time domain waveform and frequency domain spectrum can be expressed as,

$\begin{array}{cc}v_{\mathrm{CHB}}\left(t\right)=\sum _{\text{?}}^N\left(v_{\mathrm{HB}\_\text{?}}\left(t\right)\right)& \left(11\right)\\ V_{\mathrm{CHB}\_h}=\sum _{i=1}^N\left(V_{\mathrm{HB}\_i\_h}\right)=\frac{2\mathrm{NE}}{\pi h}\sum _{i=1}^N\left(e^{j\left(\text{?}+\frac{\pi }{2}\right)}-e^{j\left(\text{?}+\frac{\pi }{2}\right)}\right),h=1,3,\dots \text{?}\text{indicates text missing or illegible when filed}& \left(12\right)\end{array}$

where h is the order of the specific HB, i is the sequence number of HBs, and θ_ir and θ_if are the switching angles at rising and falling transitions of the i^th HB;

With a four-quadrant switching angle modulation technique according to the present invention, the generated V_{CHB_h} can cover the full range circle with a radius equal to 4NE/πh:

|V_{CHB_h}|≤4NE/(πh)   (13)

The output current of the CHB is:

$\begin{array}{cc}I_{\mathrm{CHB}\_h}=\{\begin{array}{cc}\frac{V_{\mathrm{CHB}\_h}-V_{\text{?}}}{j\text{?}L},& h=1\\ \frac{V_{\mathrm{CHB}\_h}}{\mathrm{jh}{\omega }_gL},,& h=3,5,\dots \end{array}\text{?}\text{indicates text missing or illegible when filed}& \begin{array}{c}\left(14\right)\\ \\ \left(15\right)\end{array}\end{array}$

From (14) and (15), the spectrum envelope |I_{CHB_h}|_ENV for harmonics (h>1) is:

$\begin{array}{cc}{I_{\mathrm{CHB}\_h}}_{\mathrm{ENV}}=\frac{{V_{\mathrm{CHB}\_h}}_{\mathrm{ma}x}}{h{\omega }_gL}=\frac{4\mathrm{NE}}{h^2\pi {\omega }_gL},h=3,5,\dots & \left(16\right)\end{array}$

where |V_{CHB_h}|max is the maximum magnitude of all possible h^th order harmonics.

For fundamental compensation, the following condition should be met:

V_{CHB_1}=jω_gL*I_{REF_1}+V_g   (17)

where I_{REF_1} is the reference fundamental current for the CHB. I_{REF_1} can be either active (for generator or battery charging function), reactive (for STATCOM function), or zero (for harmonic compensation function). From (13) and (17), for the fundamental component, the following constraint for I_{REF_1} should be met:

If V_{CHB_1}|max can meet the in-equality defined by above, then the in-equality can always be satisfied with any I_{REF_1}. To reach maximum |V_{CHB_1}|,the fundamental reference current is

I _{REF_1} =|I _{REF_1}|_max∠(arg(V_g)−90°), then |V_{CHB_1}|=|V_{CHB_1}|_max=ω_gL|I_{REF_1}|_max+|V_g|≤4NE/π.

then the constraint for L is:

$\begin{array}{cc}V_{\mathrm{CHB}\_I}=j{\omega }_gL^{*}I_{\mathrm{REF}\_1}+V_g\le 4\mathrm{NE}/\pi \{\begin{array}{c}{L}_{\text{?}}=\frac{4\mathrm{NE}/\pi -V_g}{{\omega }_g{I_{\mathrm{REF}\_1}}_{\mathrm{ma}x}}\\ L\le L_{\text{?}}\end{array}\text{?}\text{indicates text missing or illegible when filed}& \left(18\right)\end{array}$

For convenience, harmonics of a multilevel SHC are divided into controllable harmonics and uncontrollable harmonics. If the magnitude and phase of a harmonic can be controlled with a four-quadrant switching angle modulation technique according to the present invention, it is a controllable harmonic. Otherwise, it is an uncontrollable harmonic. Embodiments of the present invention can control the low order harmonics. If H is the highest order of all controllable harmonics, for h<H, I_{CHB_h} can be controlled.

As shown in FIG. 1, if I_{NL_h} is the harmonic current generated from non-linear load on the grid, for both the controllable and uncontrollable harmonics, the grid current I_{g_h} after compensation is given by (19), and its magnitude should meet harmonic standards I_{STD_h} in (20):

I _{g_h} =I _{NL_h} −I _{CHB_h,} h=1,3,5 . . .   (19)

|I_{g_h}|<|I_{STD_h|,} h=3,5 . . .   (20)

For the controllable harmonics, to ensure that the grid current harmonics are as small as possible, the current references can be designed according (21).

$\begin{array}{cc}\{\begin{array}{cc}{I}_{\mathrm{REF}\_h}=I_{\mathrm{NL}\_h},& \mathrm{if}{I_{\mathrm{CHB}\_k}}_{\mathrm{ENV}}\ge I_{\mathrm{NL}\_h}\\ I_{\mathrm{REF}\_h}={I_{\mathrm{CHB}\_h}}_{\mathrm{ENV}}\angle I_{\mathrm{NL}\_h},& \mathrm{if}{I_{\mathrm{CH}B\_h}}_{\mathrm{ENV}}<I_{\mathrm{NL}\_h}\end{array}& \left(21\right)\end{array}$

In (21), if _{ICHB_h} is higher than I_{NL_h}, the current reference for the h^th order harmonic will be equal to I_{NL_h}; then a full compensation is achieved. If I_{CHB_h} cannot be higher than I_{NL_h}, the current reference would have the maximum magnitude (the envelop magnitude) and the same phase as I_{NL_h}. Then |I_{g_h}|=|I_{NL_h}−I_{CHB_h}|=|I_{NL_h}|−|I_{CHB_h}|_ENV. The L_m design should guarantee |I_{NL_h}|−|I_{CHB_h}|ENV≤I_{STD_h} or |I_{CHB_h|ENV}≥|I_{NL_h|}−|I_{STD_h}|.

Therefore, the constraint for harmonic compensation capacity is:

$\begin{array}{cc}\{\begin{array}{c}{I}_{\mathrm{cap}\_h}=I_{\mathrm{NL}\_h}-I_{\mathrm{STD}\_h}\\ {I_{\mathrm{CHB}\_h}}_{\mathrm{ENV}}\ge I_{\mathrm{cap}\_h}\end{array},\mathrm{for}h=3,5,\dots H& \left(22\right)\end{array}$

For undesired uncontrollable harmonics above order H, the worst case should be considered.

From (19) and (20), the constraint can be described as,

$\begin{array}{cc}{I_{\text{?}}}_{\mathrm{ma}x}={\text{?}\text{?}I_{\text{?}}}_{\mathrm{ma}x}={I_{\text{?}}}_{m\mathrm{ax}}+{I_{\text{?}}}_{\mathrm{ma}x}\le I_{\text{?}}\mathrm{or},\{\begin{array}{c}{I}_{\text{?}}=I_{\mathrm{NL}\_h}-I_{\mathrm{STD}\_h}\\ {I_{\mathrm{CHB}\_h}}_{\mathrm{ENV}}\le \text{?}\end{array},\mathrm{for}h>H\text{?}\text{indicates text missing or illegible when filed}& \left(23\right)\end{array}$

The constraint above for |I_{CHB_h}|_max holds when |_{STD_h}| is larger than |I_{NL_h}|, otherwise, the |I_{CHB_h}|_max should be as small as possible when other constraints are met.

Based on the identified constraints above, the recommended inductor design procedure is:

• • Step 1: Derive the Limitation on L_fun based on fundamental requirement (18);
  • Step 2: Measure/calculate I_{NL_h} envelope, and harmonic current requirement I_{STD_h} in the standard;
  • Step 3: Use (22) to derive the constraints on compensation capacity, I_{cap_h} and use (23) to derive the constraints on undesired harmonic injection, I_{und_h};
  • Step 4: Decrease the inductance from L_fun, and find the range[L_min, L_max] where (15), (22) and (23) can be met at the same time. FIG. 8 shows a flow chart describing the process in detail. Finally an inductance inside the range is chosen.

FIG. 9 shows an example of the proposed inductor design procedure. In step 1, the fundamental requirement L_fun is calculated; then, in step 2 the current envelope of nonlinear load, I_{NL_h}, is calculated/measured and the harmonic requirement, I_{STD_h}, is obtained from the standard as shown in FIG. 9(a). In step 3, the current constraints on compensation capacity, I_{cap_h}, is derived from (22) and plotted in FIG. 9(b); the current constraints on undesired harmonic, I_{und_h}, is derived from (23) and plotted as well. In step 4, inductance L is determined and |I_{CHB_h}|ENV is derived based on (16) and plotted. As shown in FIG. 9(b), because the dotted line is between the constraints (i.e. I_{CHB_h}|ENV>I_{cap_h} and |I_{CHB_h}|ENV<I_{cap_h}), the constraints on both the compensation capacity and undesired harmonic can be met.

The methods and processes described herein can be embodied as code and/or data. The software code and data described herein can be stored on one or more computer-readable media, which may include any device or medium that can store code and/or data for use by a computer system. When a computer system reads and executes the code and/or data stored on a computer-readable medium, the computer system performs the methods and processes embodied as data structures and code stored within the computer-readable storage medium.

It should be appreciated by those skilled in the art that computer-readable media include removable and non-removable structures/devices that can be used for storage of information, such as computer-readable instructions, data structures, program modules, and other data used by a computing system/environment. A computer-readable medium includes, but is not limited to, volatile memory such as random access memories (RAM, DRAM, SRAM); and non-volatile memory such as flash memory, various read-only-memories (ROM, PROM, EPROM, EEPROM), magnetic and ferromagnetic/ferroelectric memories (MRAM, FeRAM), and magnetic and optical storage devices (hard drives, magnetic tape, CDs, DVDs); network devices; or other media now known or later developed that is capable of storing computer-readable information/data. Computer-readable media should not be construed or interpreted to include any propagating signals. A computer-readable medium of the subject invention can be, for example, a compact disc (CD), digital video disc (DVD), flash memory device, volatile memory, or a hard disk drive (HDD), such as an external HDD or the HDD of a computing device, though embodiments are not limited thereto. A computing device can be, for example, a laptop computer, desktop computer, server, cell phone, or tablet, though embodiments are not limited thereto.

The subject invention includes, but is not limited to, the following exemplified embodiments.

Embodiment 1. A four-quadrant modulation method, comprising:

determining the phase of a grid;

determining switching angles θ_r and θ_f, wherein θ_r is a rising switching angle and θ_f is a falling switching angle;

detecting switching angles θ_r and θ_f with undesired states and transforming them into practical states and leaving remaining switching angles θ_r and θ_f unchanged; and

inputting the switching angles θ_r and θ_f and the phase information into a logic circuit to generate driving signals.

Embodiment 2. The four-quadrant modulation method according to embodiment 1, wherein determining switching angles θ_r and θ_f comprises determining switching angles θ_r and θ_f without any limitations on a range of θ_r.

Embodiment 3. The four-quadrant modulation method according to any of embodiments 1-2, wherein determining switching angles θ_r and θ_f comprises determining switching angles θ_r and θ_f without any limitations on a range of θ_f.

Embodiment 4. The four-quadrant modulation method according to any of embodiments 1-3, wherein the method is applied to a DC/AC inverter, an AC to DC rectifier, or a device with an AC/DC/AC topology.

Embodiment 5. The four-quadrant modulation method according to any of embodiments 1-4, wherein the method is applied to a neutral point clamped (NPC) topology, a flying capacitor (FLC) topology, a cascaded H-bridge (CHB) topology, a modular multilevel topology, a modular multilevel converters, or a multi-module converter.

Embodiment 6. The four-quadrant modulation method according to any of embodiments 1-5, wherein the method is applied to a multilevel selective harmonic elimination (SHE), a multilevel selective harmonic elimination and compensation (SHC), a selective harmonic mitigation (SHM), or a selective harmonic optimization (SHO).

Embodiment 7. The four-quadrant modulation method according to any of embodiments 1-6, wherein determining the phase of the grid comprising using a phase locked loop to determine the phase of the grid.

Embodiment 8. The four-quadrant modulation method according to any of embodiments 1-7, wherein the switching angles θ_r and θ_f with undesired states are transformed to practical states by assigning new switching angles θ_r′ and θ_f′, wherein θ_r′=−π+θ_f and θ_f′=π+θ_r′.

Embodiment 101. A four-quadrant modulation method, comprising:

providing an inverter;

determining a phase of a grid of the inverter;

determining switching angles θ_r and θ_f, wherein θ_r is a rising switching angle and θ_f is a falling switching angle;

detecting switching angles θ_r and θ_f with undesired states and transforming them into practical states and leaving remaining switching angles θ_r and θ_f unchanged; and inputting the switching angles θ_r and θ_f and the phase information into a logic circuit to generate driving signals.

Embodiment 102. The four-quadrant modulation method according to embodiment 101, wherein the inverter is a multilevel inverter.

Embodiment 103. The four-quadrant modulation method according to any of embodiments 101-102, wherein the inverter is a 3-cell, 7-level cascaded inverter.

Embodiment 104. The four-quadrant modulation method according to any of embodiments 101-103, wherein determining switching angles θ_r and θ_f comprises determining switching angles θ_r and θ_f without any limitations on a range of θ_r.

Embodiment 105. The four-quadrant modulation method according to any of embodiments 101-104, wherein determining switching angles θ_r and θ_f comprises determining switching angles θ_r and θ_f without any limitations on a range of θ_r.

Embodiment 106. The four-quadrant modulation method according to according to any of embodiments 101-105, wherein the method is applied to a DC/AC inverter, an AC to DC rectifier, or a device with an AC/DC/AC topology.

Embodiment 107. The four-quadrant modulation method according to according to any of embodiments 101-106, wherein the method is applied to a neutral point clamped (NPC) topology, a flying capacitor (FLC) topology, a cascaded H-bridge (CHB) topology, a modular multilevel topology, a modular multilevel converters, or a multi-module converter.

Embodiment 108. The four-quadrant modulation method according to according to any of embodiments 101-107, wherein the method is applied to a multilevel selective harmonic elimination (SHE), a multilevel selective harmonic elimination and compensation (SHC), a selective harmonic mitigation (SHM), or a selective harmonic optimization (SHO).

Embodiment 109. The four-quadrant modulation method according to according to any of embodiments 101-108, wherein determining the phase of the grid comprising using a phase locked loop to determine the phase of the grid.

Embodiment 110. The four-quadrant modulation method according to according to any of embodiments 101-109, wherein the switching angles θ_r and θ_f with undesired states are transformed to practical states by assigning new switching angles θ_r′ and θ_f′, wherein θ_r′=−π+θ_f and θ_f′=πn+θ_r′.

Embodiment 111. The four-quadrant modulation method according to according to any of embodiments 101-110, wherein the inverter comprises six switching states, and wherein state 1 through state 6 are defined as follows:

Embodiment 201. A system for four-quadrant modulation, the system comprising:

a processor; and

a (non-transitory) machine-readable medium (e.g., a (non-transitory) computer-readable medium) in operable communication with the processor and having machine-executable instructions (e.g., computer-executable instructions) stored thereon that, when executed by the processor, perform the method according to any of embodiments 1-8 or 101-111.

Embodiment 202. The system according to embodiment 201, further comprising an inverter.

Embodiment 203. The system according toc embodiment 202, wherein the inverter is a multilevel inverter.

Embodiment 204. The system according to any of embodiments 202-203, wherein the inverter is a 3-cell, 7-level cascaded inverter.

Embodiment 205. The system according to any of embodiments 201-204, further comprising a DC/AC inverter.

Embodiment 206. The system according to any of embodiments 201-205, further comprising an AC to DC rectifier

Embodiment 207. The system according to any of embodiments 201-206, further comprising a device with an AC/DC/AC topology.

A greater understanding of the present invention and of its many advantages may be had from the following example, given by way of illustration. The following example is illustrative of some of the methods, applications, embodiments and variants of the present invention. It is, of course, not to be considered as limiting the invention. Numerous changes and modifications can be made with respect to the invention.

Example 1

A simulation and proof of concept experiment was conducted for a 3-cell, 7 level 1 kVA prototype to validate a four-quadrant switching angle modulation technique according to an embodiment of the present invention. The circuit topology, test plan and parameters are shown in FIG. 10, FIG. 11, Table I, and Table II, respectively. Simulations were conducted on MATLAB SIMULINK, and the experimental waveforms were recorded with a RIGOL MS04054 digital oscilloscope. The spectrums from simulations and experiments were calculated using MATLAB FFT tool. The harmonic mitigation technique was implemented, and up to 15 harmonics could be controlled. Detailed inductor design based on the inductor design procedure is below. Harmonic standard IEEE 519 was used as the harmonic limitation. The calculated four-quadrant switching angles are shown in TABLE III.

FIG. 12 shows the experimental and simulation results for test 1 after applying a four-quadrant switching angle modulation technique according to an embodiment of the present invention in the non-grid tied system with RL load in FIG. 9(a). With the four-quadrant switching angle modulation technique, the V_CHB is five-level, instead of seven-level, while the switching frequency is still 60 Hz in each HB. The current spectrum shows that the fundamental component, harmonics and total demand distortion (TDD) meet the requirements.

TABLE I
CONFIGURATION OF THE SIMULATION
AND EXPERIMENT
	Topology	Fundamental Parameters
	Test 1	(a)	P = 640 W, Q = 483VAR
	Test 2	(b)	P = 990 W, Q = 0
	Test 3	(c), KCAP OFF	P = −480 W, Q = 480 VAR
	Test 4	(c), KCAP ON	P = −390 W, Q = −480 VAR

TABLE II
PARAMETERS OF SIMULAITON & EXPERIMENT
	Grid Voltage, Vg	110 V/60 Hz
	DC bus voltage, E	50	V
	Number of cells, N	3
	Inductance LL	10	mH
	Resistance RL	5	ohm
	Inductance LL1	5	mH
	Inductance LL2	2.5	mH
	Capacitance CL1	1000	uF
	Capacitance CL2	400	uF
	Inductance Lm	5	mH
	Resistance RL1	7.5 ohm (Test 3)
		15 ohm (Test 4)

TABLE III
THE CALCULATED FOUR-QURDRANT
SWITCHING ANGLES
	θr (deg)	θf (deg)	switching state
	Test 1	112.4	106.8	State 2
		52.35	132.3	State 1
		12.16	166.8	State 1
	Test 1*	0	180	State 1
		55.76	90.93	State 1
		89.90	124.2	State 1
	Test 2	−62.51	−143.0	State 6
		−22.96	177.5	State 3s
		−42.11	78.01	State 3
	Test 3	31.10	162.8	State 1
		53.70	146.4	State 1
		88.67	105.5	State 1
	Test 4	80.30	−174.9	State 4s
		−20.10	140.8	State 3
		42.31	30.25	State 2

If a conventional modulation technique is adopted, the switching angle solutions cannot be found. One practical solution is to sacrifice high order harmonics and only control fundamental and 3^rd harmonics. The waveforms and the current spectrums with a conventional single quadrant switching angle modulation technique are as shown in FIG. 13 for test 1*. In the FIG. 14, the waveform is 7-level, but its current harmonic cannot meet the harmonic requirement. The comparison of FIGS. 12 and 13 shows the advantages of embodiments of the present invention.

FIG. 14 shows the results of test 2 after a four quadrant modulation technique according to the present invention is applied to a grid-tied CHB system. The results of test 3 in FIG. 15 and the results of test 4 in FIG. 16 show that a four quadrant modulation according to the present invention can be used to simultaneously draw active power from the grid to charge batteries, compensate the harmonics of non-linear loads, and compensate the reactive power on the grid. Both the harmonic spectra before compensation and after compensations are shown in both FIGS. 15 and 16. The solid bars are the spectrum before the compensation and the empty bars are the spectrum after the compensation. Both simulation and experimental results show that the active power is well controlled as designed to charge batteries (i.e., PF was controlled to be unity), high order harmonics are below the standard, and TDD is below 5%.

Conventional single-quadrant switching angle modulation techniques cannot find solutions for test 1, 2 and 4, while four quadrant modulation according to the present invention can find solutions for all 4 tests. This proves that four quadrant modulation techniques according to the present invention can significantly extend modulation index ranges.

The detailed process for the inductor design in the above simulation and experiment will now be discussed.

Test 1 is an offline application. Therefore, Vg=0, Z=j_hωgL+R. Hence (16) is transformed to

$\begin{array}{cc}{I_{\mathrm{CHB}\_h}}_{\mathrm{ENV}}=\frac{4E}{hZ}=\frac{4E}{h\sqrt{{\left({\omega }_gL\right)}^2+R^2}},h=3,5,7;& \left(18\right)\end{array}$

is transformed to

$Z_{\text{?}}=\frac{4\mathrm{NE}}{\pi {{}_{I_{\mathrm{REF}\_1}}}_{\mathrm{ma}x}}\mathrm{and}L_{\text{?}}=\sqrt{Z_{\text{?}}^2-R^2}/{\omega }_R.\text{?}\text{indicates text missing or illegible when filed}$

In step 1, L_fun equals to 21.6 mH; in step 2, I_{NL_h}=0 because no compensation is required in the system, and the current harmonic requirement, I_{STD_h}, is regulated by Std. 519 with its strictest limitation; in step 3, from (22), I_{cap_h}=−I_{STD_h}<0 indicating that no compensation requirement is required and from (23) I_{und_h}=I_{STD_h}; in step 4, L_min=7.8 mH and L_max=21.6 mH. Therefore, a 10 mH inductor is used in the system. The relationship between the constraints and |I_{CHB_h|ENV} is as shown in FIG. 17.

Test 2 is a grid-tied system with an elimination purpose. Similar to test 1, I_NL=0 because there is no compensation requirement. The grid voltage is provided by a strong grid with an auto-transformer, STACO 2513-3. In step 1, L_fun=10.74 mH; in step 2, I_{NL_h}=0 and the current harmonic, I_{STD_h}, is regulated by Std. 519; from (22), I_{cap_h}=−I_{STD_h}<0 indicating that no compensation requirement is required and from (23) I_{und_h}=I_{STD_h}; in step 4, L_min=4.6 mH and L_max=10.74 mH. A 10 mH inductor is used in the system. The relationship between the constraints and |I_{CHB_h}|_ENV is as shown in FIG. 18.

It should be noted that I_{STD_h} in Std. 519 is related to |I_SC/I_rated|, where I_SC is short current. Because Z_g is ignorable with strong grid, and Z_T=0.32+j0.078, which is measured using an impedance analyzer, KEYSIGHT E4990A at 60 Hz, the short current is I_SC=V_g/(Z_g+Z_T)=(459−j112) A, and |I/_SC/I_rated|23.6. The I_{STD_h} with grid-tied application is different from test 1 as compared in FIGS. 17 and 18.

Test 3 and test 4 are grid-tied systems having the same working conditions as shown above. No equations need extra transformation. For test 3, in step 1, L_fun=10.74 mH; in step 2, the I_{NL_h} and I_{STD_h} is as shown in FIG. 19(a); in step 3, I_{cap_h} and I_{und_h} is as shown in FIG. 19(b) , in step 4, L_max=6.8 mH, and L_min=4.9 mH. L_m=5 mH is used in the system, and |_{CHB_h}|_ENV is as shown in FIG. 19(b).

For test 4, L_fun=10.74 mH, L_max=5.9 mH, L_min=4.9 mH, and L_m=5 mH is used in the system. The I_{NL_h} and I_{STD_h} is as shown in FIG. 19 (a); I_{cap_h}, I_{und_h} and |I_{CHB_h}|_ENV is as shown in FIG. 19(b).

It is important to note that the undesired current attenuation constraint is calculated based on a worst case scenario, which is rare in real-world applications. As a result, there is a large margin between the undesired harmonics and the standard requirement. As shown in FIGS. 14, 15 and 16, although inductor design only considers I_{STD_h} with |I_SC/I_rated| ∈ [20, 50], the actual current can meet the strictest requirement in Std. 519.

It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application.

All patents, patent applications, provisional applications, and publications referred to or cited herein (including those in the “References” section) are incorporated by reference in their entirety, including all figures and tables, to the extent they are not inconsistent with the explicit teachings of this specification.

REFERENCES

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2. A. Marzoughi, R. Burgos, D. Boroyevich, and Y. Xue, “Investigation and comparison of cascaded H-bridge and modular multilevel converter topologies for medium-voltage drive application,” in IECON 2014-40th Annual Conference of the IEEE Industrial Electronics Society, 2014, pp. 1562-1568.

3. Y. Zhou and H. Li, “Analysis and Suppression of Leakage Current in Cascaded-Multilevel-Inverter-Based PV Systems,” IEEE Transactions on Power Electronics, vol. 29, pp. 5265-5277, 2014.

4. Y. Chu, S. Wang, and R. Crosier, “Grid active power filters using cascaded multilevel inverters with direct asymmetric switching angle control for grid support functions,” in Applied Power Electronics Conference and Exposition (APEC), 2013 Twenty-Eighth Annual IEEE, 2013, pp. 1332-1338.

5. H. Zhao and S. Wang, “A real-time selective harmonic compensation (SHC) based on asymmetric switching angle modulation and current feedback control for cascaded modular multilevel inverters,” presented at the 2015 IEEE Applied Power Electronics Conference and Exposition (APEC), 2015.

6. H. Zhao, T. Jin, S. Wang, and L. Sun, “A Real-Time Selective Harmonic Elimination Based on a Transient-Free Inner Closed-Loop Control for Cascaded Multilevel Inverters,” IEEE Transactions on Power Electronics, vol. 31, pp. 1000- 1014, 2016.

7. Z. Hua, L. Yun Wei, N. R. Zargari, C. Zhongyaun, N. Ruoshui, and Z. Ye, “Selective Harmonic Compensation (SHC) PWM for Grid-Interfacing High-Power Converters,” Power Electronics, IEEE Transactions on, vol. 29, pp. 1118-1127, 2014.

8. A. Moeini, H. Zhao, and S. Wang, “High efficiency, hybrid Selective Harmonic Elimination phase-shift PWM technique for Cascaded H-Bridge inverters to improve dynamic response and operate in complete normal modulation indices,” in 2016 IEEE Applied Power Electronics Conference and Exposition (APEC), 2016, pp. 2019-2026.

9. L. Yu, H. Hoon, and A. Q. Huang, “Real-Time Calculation of Switching Angles Minimizing THD for Multilevel Inverters With Step Modulation,” Industrial Electronics, IEEE Transactions on, vol. 56, pp. 285-293, 2009.

10. B. Ozpineci, L. M. Tolbert, and J. N. Chiasson, “Harmonic optimization of multilevel converters using genetic algorithms,” Power Electronics Letters, IEEE, vol. 3, pp. 92-95, 2005.

11. W. Jin and D. Ahmadi, “A Precise and Practical Harmonic Elimination Method for Multilevel Inverters,” Industry Applications, IEEE Transactions on, vol. 46, pp. 857-865, 2010.

12. J. N. Chiasson, L. M. Tolbert, K. J. McKenzie, and D. Zhong, “A complete solution to the harmonic elimination problem,” Power Electronics, IEEE Transactions on, vol. 19, pp. 491-499, 2004.

13. L. M. Tolbert, J. N. Chiasson, D. Zhong, and K. J. McKenzie, “Elimination of harmonics in a multilevel converter with nonequal DC sources,” Industry Applications, IEEE Transactions on, vol. 41, pp. 75-82, 2005.

14. Y. Liu, H. Hong, and A. Q. Huang, “Real-Time Algorithm for Minimizing THD in Multilevel Inverters With Unequal or Varying Voltage Steps Under Staircase Modulation,” IEEE Transactions on Industrial Electronics, vol. 56, pp. 2249- 2258, 2009.

15. M. S. A. Dahidah, G. Konstantinou, N. Flourentzou, and V. G. Agelidis, “On comparing the symmetrical and non-symmetrical selective harmonic elimination pulse-width modulation technique for two-level three-phase voltage source converters,” Power Electronics, IET, vol. 3, pp. 829-842, 2010.

16. M. S. A. Dahidah and V. G. Agelidis, “Non-symmetrical SHE-PWM technique for five-level cascaded converter with non-equal DC sources,” in Power and Energy Conference, 2008. PECon 2008. IEEE 2nd International, 2008, pp. 775- 780.

17. A. Moeini, H. Iman-Eini, and A. Marzoughi, “DC link voltage balancing approach for cascaded H-bridge active rectifier based on selective harmonic elimination-pulse width modulation,” IET Power Electronics, vol. 8, pp. 583-590, 2015.

18. M. Najjar, A. Moeini, M. K. Bakhshizadeh, F. Blaabjerg, and S. Farhangi, “Optimal Selective Harmonic Mitigation Technique on Variable DC Link Cascaded H-Bridge Converter to Meet Power Quality Standards,” IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. PP, pp. 1-1, 2016.

19. D. Hong, S. Bai, and S. M. Lukic, “Closed-Form Expressions for Minimizing Total Harmonic Distortion in Three-Phase Multilevel Converters,” Power Electronics, IEEE Transactions on, vol. 29, pp. 5229-5241, 2014.

20. U.S. Pat. No. 4,344,123. Multilevel PWM inverter

21. U.S. Pat. No. 5,642,275. Multilevel cascade voltage source inverter with separate DC sources [2] U.S. Pat. No. 6,075,350. Power line conditioner using cascade multilevel inverters for voltage regulation, reactive power correction, and harmonic filtering.

22. Same topology and objective. But the modulation method to generate the waveform is not the same.

23. EP0336019. Multilevel pulse width modulation method, and modulator using this method.

24. M. S. A. Dahidah, G. Konstantinou, and V. G. Agelidis, “A Review of Multilevel Selective Harmonic Elimination PWM: Formulations, Solving Algorithms, Implementation and Applications,” Power Electronics, IEEE Transactions on, vol. 30, pp. 4091-4106, 2015.

25. A. Marzoughi, R. Burgos, D. Boroyevich, and Y. Xue, “Investigation and comparison of cascaded H-bridge and modular multilevel converter topologies for medium-voltage drive application,” in IECON 2014-40th Annual Conference of the IEEE Industrial Electronics Society, 2014, pp. 1562- 1568.

26. Y. Zhou and H. Li, “Analysis and Suppression of Leakage Current in Cascaded-Multilevel-Inverter-Based PV Systems,” IEEE Transactions on Power Electronics, vol. 29, pp. 5265-5277, 2014.

27. Y. Chu, S. Wang, and R. Crosier, “Grid active power filters using cascaded multilevel inverters with direct asymmetric switching angle control for grid support functions,” in Applied Power Electronics Conference and Exposition (APEC), 2013 Twenty-Eighth Annual IEEE, 2013, pp. 1332-1338.

28. H. Zhao and S. Wang, “A real-time selective harmonic compensation (SHC) based on asymmetric switching angle modulation and current feedback control for cascaded modular multilevel inverters,” presented at the 2015 IEEE Applied Power Electronics Conference and Exposition (APEC), 2015.

29. H. Zhao, T. Jin, S. Wang, and L. Sun, “A Real-Time Selective Harmonic Elimination Based on a Transient-Free Inner Closed-Loop Control for Cascaded Multilevel Inverters,” IEEE Transactions on Power Electronics, vol. 31, pp. 1000-1014, 2016.

30. Z. Hua, L. Yun Wei, N. R. Zargari, C. Zhongyaun, N. Ruoshui, and Z. Ye, “Selective Harmonic Compensation (SHC) PWM for Grid-Interfacing High- Power Converters,” Power Electronics, IEEE Transactions on, vol. 29, pp. 1118-1127, 2014.

31. A. Moeini, H. Zhao, and S. Wang, “High efficiency, hybrid Selective Harmonic Elimination phase-shift PWM technique for Cascaded H-Bridge inverters to improve dynamic response and operate in complete normal modulation indices,” in 2016 IEEE Applied Power Electronics Conference and Exposition (APEC), 2016, pp. 2019-2026.

32. L. Yu, H. Hoon, and A. Q. Huang, “Real-Time Calculation of Switching Angles Minimizing THD for Multilevel Inverters With Step Modulation,” Industrial Electronics, IEEE Transactions on, vol. 56, pp. 285-293, 2009.

33. B. Ozpineci, L. M. Tolbert, and J. N. Chiasson, “Harmonic optimization of multilevel converters using genetic algorithms,” Power Electronics Letters, IEEE, vol. 3, pp. 92-95, 2005.

34. W. Jin and D. Ahmadi, “A Precise and Practical Harmonic Elimination Method for Multilevel Inverters,” Industry Applications, IEEE Transactions on, vol. 46, pp. 857-865, 2010.

35. J. N. Chiasson, L. M. Tolbert, K. J. McKenzie, and D. Zhong, “A complete solution to the harmonic elimination problem,” Power Electronics, IEEE Transactions on, vol. 19, pp. 491-499, 2004.

36. L. M. Tolbert, J. N. Chiasson, D. Zhong, and K. J. McKenzie, “Elimination of harmonics in a multilevel converter with nonequal DC sources,” Industry Applications, IEEE Transactions on, vol. 41, pp. 75-82, 2005.

37. Y. Liu, H. Hong, and A. Q. Huang, “Real-Time Algorithm for Minimizing THD in Multilevel Inverters With Unequal or Varying Voltage Steps Under Staircase Modulation,” IEEE Transactions on Industrial Electronics, vol. 56, pp. 2249-2258, 2009.

38. M. S. A. Dahidah, G. Konstantinou, N. Flourentzou, and V. G. Agelidis, “On comparing the symmetrical and non-symmetrical selective harmonic elimination pulse-width modulation technique for two-level three-phase voltage source converters,” Power Electronics, IET, vol. 3, pp. 829-842, 2010.

39. M. S. A. Dahidah and V. G. Agelidis, “Non-symmetrical SHE-PWM technique for five-level cascaded converter with non-equal DC sources,” in Power and Energy Conference, 2008. PECon 2008. IEEE 2nd International, 2008, pp. 775-780.

40. A. Moeini, H. Iman-Eini, and A. Marzoughi, “DC link voltage balancing approach for cascaded H-bridge active rectifier based on selective harmonic elimination-pulse width modulation,” IET Power Electronics, vol. 8, pp. 583-590, 2015.

41. M. Najjar, A. Moeini, M. K. Bakhshizadeh, F. Blaabjerg, and S. Farhangi, “Optimal Selective Harmonic Mitigation Technique on Variable DC Link Cascaded H-Bridge Converter to Meet Power Quality Standards,” IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. PP, pp. 1-1, 2016.

42. D. Hong, S. Bai, and S. M. Lukic, “Closed-Form Expressions for Minimizing Total Harmonic Distortion in Three-Phase Multilevel Converters,” Power Electronics, IEEE Transactions on, vol. 29, pp. 5229-5241, 2014.

Claims

1. A four-quadrant modulation method, comprising: determining the phase of a grid;determining switching angles θr and θf, wherein θr is a rising switching angle and θf is a falling switching angle;detecting switching angles θr and θf with undesired states and transforming them into practical states and leaving remaining switching angles θr and θf unchanged; andinputting the switching angles θr and θf and the phase information into a logic circuit to generate driving signals.

2. The four-quadrant modulation method according to claim 1, wherein determining switching angles θr and θf comprises determining switching angles θr and θf without any limitations on a range of θr.

3. The four-quadrant modulation method according to claim 2, wherein determining switching angles θr and θf comprises determining switching angles θr and θf without any limitations on a range of θf.

4. The four-quadrant modulation method according to claim 3, wherein the switching angles θr and θf with undesired states are transformed to practical states by assigning new switching angles θr′ and θf′, wherein θr′=−π+θf and θf′=π+θr′.

5. The four-quadrant modulation method according to claim 1, wherein the method is applied to a DC/AC inverter, an AC to DC rectifier, or a device with an AC/DC/AC topology.

6. The four-quadrant modulation method according to claim 5, wherein the switching angles θr and θf with undesired states are transformed to practical states by assigning new switching angles θr′ and θf′, wherein θr′=π+θf and θf′=−π+θr′.

7. The four-quadrant modulation method according to claim 1, wherein the method is applied to a neutral point clamped (NPC) topology, a flying capacitor (FLC) topology, a cascaded H-bridge (CHB) topology, a modular multilevel topology, a modular multilevel converters, or a multi-module converter.

8. The four-quadrant modulation method according to claim 7, wherein the switching angles θr and θf with undesired states are transformed to practical states by assigning new switching angles θr′ and θf′, wherein θr′=−π+θf and θf′=−π+θr′.

9. The four-quadrant modulation method according to claim 1, wherein the method is applied to a multilevel selective harmonic elimination (SHE), a multilevel selective harmonic elimination and compensation (SHC), a selective harmonic mitigation (SHM), or a selective harmonic optimization (SHO).

10. The four-quadrant modulation method according to claim 9, wherein the switching angles θr and θf with undesired states are transformed to practical states by assigning new switching angles θr′ and θf′, wherein θr′=π+θf and θf′=−π+θr′.

11. The four-quadrant modulation method according to claim 1, wherein determining the phase of the grid comprising using a phase locked loop to determine the phase of the grid.

12. The four-quadrant modulation method according to claim 1, wherein the switching angles θr and θf with undesired states are transformed to practical states by assigning new switching angles θr′ and θf′, wherein θr′=−π+θf and θf′=π+θr′.

13. A four-quadrant modulation method, comprising: providing a 3-cell 7-level cascaded multilevel inverter;determining a phase of a grid of the inverter;determining switching angles θr and θf, wherein θr is a rising switching angle and θf is a falling switching angle;detecting switching angles θr and θf with undesired states and transforming them into practical states and leaving remaining switching angles θr and θf unchanged; andinputting the switching angles θr and θf and the phase information into a logic circuit to generate driving signals.

14. The four-quadrant modulation method according to claim 13, wherein determining switching angles θr and θf comprises determining switching angles θr and θf without any limitations on a range of θr and without any limitations on a range of θf.

15. The four-quadrant modulation method according to claim 13, wherein the method is applied to a DC/AC inverter, an AC to DC rectifier, or a device with an AC/DC/AC topology.

16. The four-quadrant modulation method according to claim 13, wherein the method is applied to a neutral point clamped (NPC) topology, a flying capacitor (FLC) topology, a cascaded H-bridge (CHB) topology, a modular multilevel topology, a modular multilevel converters, or a multi-module converter.

17. The four-quadrant modulation method according to claim 13, wherein the method is applied to a multilevel selective harmonic elimination (SHE), a multilevel selective harmonic elimination and compensation (SHC), a selective harmonic mitigation (SHM), or a selective harmonic optimization (SHO).

18. The four-quadrant modulation method according to claim 13, wherein determining the phase of the grid comprising using a phase locked loop to determine the phase of the grid.

19. The four-quadrant modulation method according to claim 13, wherein the switching angles θr and θf with undesired states are transformed to practical states by assigning new switching angles θr′ and θf′, wherein θr′=−π+θf and θf′=π+θr′.

20. The four-quadrant modulation method according to claims 13, wherein the inverter comprises six switching states, and wherein state 1 through state 6 are defined as follows: