This invention relates broadly to Current Conveyors (CCs) and more specifically to Second Generation Current Conveyors (CCIIs) including feedback networks.
In broad terms, Current Conveyors (CCs) and Second Generation Current Conveyors (CCIIs) are known in the electronic arts (https://en.wikipedia.org/wiki/Current_conveyor, accessed 5 Jun. 2017). Since the introduction of the CCII in the 1970s [1], it has proven to be a versatile building block in analogue electronic design. Systems employing the CCII include active filters [2], impedance converters such as negative impedance converters (NICs), active inductance circuits [1], operational amplifiers, gyrators, mode converters, oscillators [1], [3], controlled voltage and current sources [1], analogue computation elements such as integrators and differentiators [4], current-mode digital-to-analogue (DAC) converters and variable-state filters [5].
A CCII is a three-port network defined by the hybrid matrix:
where β and α represent the voltage and current transfer ratios respectively, YY the admittance at port Y, ZX the impedance at port X and YZ the admittance at port Z [3]. It is desirable in many applications to minimise the deviation of β and α from unity (here referred to as the transfer error), minimise RX and maximise RZ and RY (the resistive components of ZX, YZ and YY respectively) for some desired bandwidth.
The first implementations of CCIIs used operational amplifiers as functional blocks due to a lack of high-quality pnp devices in bipolar technology nodes at the time [4]. Research efforts were subsequently focused at finding equivalent CMOS realisations [5], [9], [10]. An example CCII [5] has formed the baseline of many subsequent designs, presenting an RX of less than 50Ω and a transfer error of below 1%. Another example CCII [10] proposed improves on this transfer precision by employing a double feedback mechanism as well as a high-swing cascode current mirror. The added complexity, however, reduces the achievable bandwidth to ˜1 MHz in 0.6 μm CMOS. Furthermore, the efficacy of this approach is only demonstrated in simulation, and not in measurement. On the other hand [9], the CCII from can be simplified by incorporating the common drain feedback amplifier into the differential voltage follower stage. This has the effect of improving the bandwidth (20 MHz in 1.2 μm CMOS) and reducing RX to 0.3Ω. An RC compensation network is also used, for the first time, to reduce peaking.
In an effort to improve bandwidth, an implementation based on a source follower and cascode current mirror stage [11] achieves a bandwidth of 700 MHz in a 1.2 μm CMOS node (for suitable load terminations). However, the resulting RX is large (˜50Ω), illustrating the trade-off between bandwidth and RX. A new high-precision (β and α transfer errors of 30×10-6 and 10-6 respectively) and ultra-low RX (less than 0.1Ω) CCII has been proposed [12]. The design, however, only achieves a bandwidth of 15 MHz in 0.5 um CMOS, demonstrating the trade-off that also exists between bandwidth and transfer precision. Other implementations of CCIIs not based on the aforementioned topologies have also been proposed, such as translinear-loop based CCII [13] with large bandwidths (2-3 GHz in 0.35 μm CMOS) and a low RX below 20Ω. This improvement comes at the price of a larger transfer error of 4%. Other recent CCII implementations based on a flipped voltage follower [14] and floating current source [15], [16] have also been proposed. In [14], low-power operation is achieved (less than 100 μW) and low THD (Total Harmonic Distortion) of less than 0.21% with a transfer error of less than 0.01% at the cost of bandwidth reduction (less than 60 MHz in 0.35 μm CMOS). In [15] a large bandwidth of ˜600 MHz (1 μm CMOS) with RX<15Ω is presented.
An analysis of the state-of-the-art in published literature therefore indicates that open-loop designs achieve higher bandwidths than designs with closed-loop feedback, but at the expense of poorer transfer precision and higher RX values. On the other hand, closed-loop designs boast excellent precision and low RX values but at the expense of lower bandwidths.
Besides having narrower operating bands, closed-loop CCIIs are also susceptible to instability, especially at higher frequencies. Despite this risk, stability analysis in CCIIs has received minimal attention in the literature. Even though a general approach [17] to the feedback analysis of low output impedance circuits (such as CCIIs), often an analytical approach at high frequencies is too complex to attempt. Furthermore, analytical methods typically fail to account for multiple loops which, if not explicitly created in the CCII circuit design, may exist through parasitic elements. Besides possible instability, feedback loops often also cause gain peaking at the upper frequency band-edge, with the only work [9] in addressing this problem through peaking reduction. The stability problem is often compounded by changing load impedance and environmental conditions during operation, as well as process variation. The Applicant believes that this problem requires post-production tunable phase margin and peaking control, which has never been addressed in literature.
Another shortcoming in the body of literature on CMOS CCIIs is a lack of published measurement data. In many publications [5], [9]-[16], all results are based on simulations. Furthermore, few papers consider practicalities of device manufacturing such as non-ideal effects, process corners and random variation, device parasitics, and stability considerations. To the Applicant's knowledge, no disclosure describing a physical implementation (with measurement results) of a high bandwidth, high precision CMOS CCII has ever been published. This may have contributed to manufacturers' aversion to commercial adoption of CCIIs [4].
Accordingly, the Applicant desires, and it may be an object of the invention to provide, one or more of the following:
Accordingly, the invention provides a Second Generation Current Conveyor (CCII) having a three-port network with ports designated as X, Y, and Z, wherein the CCII includes:
The tunable feedback network may be provided between at least two of the ports. The tunable feedback network may be provided between ports Z and Y.
The tunable feedback network may be post-production tunable. The tunable feedback network may be used to compensate for process tolerances.
The tunable feedback network may be implemented to reduce passband ripple.
The tunable feedback network may yield a CCII with both a large bandwidth and high precision.
The tunable feedback network may comprise a tunable RC network. The tunable RC network may be in the form of a tunable RC Miller network. The RC Miller network may comprise a capacitive element and a resistive element. The resistive element may include at least one solid-state element. The resistive element may be a MOS (Metal-Oxide Semiconductor) device or a MOS resistor. A resistance offered by the resistive element may be voltage-controlled or voltage-variable. The capacitive element may include at least one solid-state element. The capacitive element may be a varactor. A capacitance offered by the capacitive element may be voltage-controlled or voltage-variable. Accordingly, feedback characteristics, or other characteristics, of the tunable feedback network may be adjusted by adjusting a voltage applied to the resistive element and/or the capacitive element.
The tunable feedback network may be tunable to adjust one or more of the following characteristics:
The tunable feedback network may include a plurality of transistors. One or more of the transistors in the tunable feedback network may form part of one or more of the following:
The CCII may be implemented in CMOS (Complementary Metal-Oxide Semiconductor). The CCII may be implemented in 0.35 μm CMOS. The CCII may have an operating bandwidth exceeding 500 MHz. The CCII may have RX lower than 5Ω. The CCII may have a transfer error lower than 1%.
The CCII may be analysed using a multi-loop feedback analysis methodology based on the true return ratio approach [18], as well as multi-loop feedback theory [19], to design the tunable feedback network. Stability analysis proposed in [10] may be applied to the CCII to verify the efficacy of the approach, using two feedback loops.
The invention will now be further described, by way of example, with reference to the accompanying diagrammatic drawings.
In the drawings:
The following description of the invention is provided as an enabling teaching of the invention. Those skilled in the relevant art will recognise that many changes can be made to the embodiment described, while still attaining the beneficial results of the present invention. It will also be apparent that some of the desired benefits of the present invention can be attained by selecting some of the features of the present invention without utilising other features. Accordingly, those skilled in the art will recognise that modifications and adaptations to the present invention are possible and can even be desirable in certain circumstances, and are a part of the present invention. Thus, the following description is provided as illustrative of the principles of the present invention and not a limitation thereof.
First, the Applicant provides an explanation of techniques used to design and analyse a CCII in accordance with the invention.
Single-loop feedback theory is based on Bode's definition of the return ratio
where ve and ie represent the injected and vf and if the returned signals, as shown in
Bode's original theory requires replacing an existing dependent source (that models the active device—typically current or voltage gain) with an independent test source, which is not always possible, especially if black-box models are used. This limitation is overcome by Middlebrook's and Tian's subsequent extensions to single-loop feedback theory [18]. Using Middlebrook's approach, the feedback loop can be “cut” at any point that breaks all possible feedback loops, and a test source is inserted in the loop at the break, as shown in
The return ratio, can be derived from (2) and
Next, using Mason's multi-loop feedback theory [19], the single-loop cut approach is extended to multi-loop systems. As an example, the CCII+ in [10] can be represented by the signal flow graph in
All feedback loops, as well as the source and sink, are indicated. Mason has shown that the denominator of the transfer gain (denoted by Δ) is given by [19]
Δ=1−ΣmPm1+ΣmPm2−ΣmPm3+ . . . , (5)
where Pmr is the gain product of the mth possible combination of r non-touching loops where r>0. For example, in
T
1
=ed, T
2
=fg, T
3
=jk, T
4
=hi, T
5
=gec, T
6
=kic, T
7
=dfb, T
8
=hjb, T
9
=fkid, T
10
=jgeh. (6)
From (5),
Δ=1−Σi=110Ti+(T1T2+T3T4), (7)
which can be re-written in the factorised form [19]
Δ=Πn1−Tn′, (8)
where Tn′ is the loop gain of the nth loop with all lower-numbered loops split.
To illustrate the practical implication of (8), node 2 in
Δ=(1−T1′)(1−T2′)=1−T1′−T2′+T1′T2′, (9)
which has the same form as (7), as expected. In general, Tn′≠Tn.
Equation (8) is therefore compatible with the aforementioned double-injection cut technique and Δ can be obtained with relative ease, even for complicated cases (in the above example only two cuts were sufficient to isolate 10 loops). It is also compatible with existing numerical approaches, where parts of the signal flow graph might be black box models where the feedback structure is unknown (such as device parasitics of transistor models). Moreover, if a loop or part of a loop is considered twice (which is particularly likely in the black-box scenario) then the computed gain is simply 0 and from (8) results in multiplication of Δ by 1.
Finally, the stability of the network can be determined by solving for the poles of Δ. Alternatively, the effective open-loop gain can be found and a Nyquist plot constructed by:
Δ=1+A(s)F(s), A(s)F(s)=Δ−1, (10)
where A and F are the effective forward and feedback loop gains.
The approach for analysing multi-loop feedback stability therefore consists of the following steps:
Having formulated a multi-loop feedback analysis technique compatible with the envisaged numerical circuit design practices, the design and analysis of CCII in accordance with the invention may be disclosed and discussed.
An input of the circuit 100 is a differential voltage follower stage (M3-M7) which mirrors the voltage from port Y to X. A simple current mirror then conveys the current from port X to Z. Transistor M8 ensures that M5 operates in saturation and together with M9 ensures the same DC VDS across M5 and M6 (thereby reducing the voltage following error). M13 ensures that VDS across M8 is similar to that of M9, further reducing any voltage difference between the two legs of the differential voltage mirror. A high gain (and, subsequently, narrow band) AC feedback path is formed by the common source pair M8 and M13.
The remaining transistors act as biasing current sources. As a novel extension on [12], the tunable feedback network 102 is rendered tunable by adding a post-production tunable RC Miller network, with rfb and cfb selected to reduce this feedback gain and increase the bandwidth, at the expense of degrading precision and RX. Finally, a load impedance RL of 50Ω terminates both ports X and Z, to represent either external test equipment or a subsequent SoC (Silicon on-Chip) stage. The present design is, however, compatible with an arbitrary value of load impedance. A driving source is assumed to have negligible output impedance, as is common in CCII design.
To increase the bandwidth further and control the resulting tradeoffs, a numerical optimization-based design methodology is implemented. Design equations (11)-(15) are derived to serve as a basis for finding initial design values as well as to guide the numerical optimizations. These equations do not consider parasitic effects, which will only be accounted for in later simulation (using accurate device models supplied by the foundry) during the optimization stage. In the circuit 100, the following are chosen: RL=50Ω, gm,vm=gm,5=gm,6, gm,m=gm,14=gm,15=gm,16, gm,fb=gm,13, gm,b2=gm,17=gm,18, go,b2=go,17=go,18, go,b1=go,7, go,vm=go,5=go,6, go,m=go,14=go,15=go,16, go,fb=go,13. gm and go represent the transconductances and output conductances of the transistors, respectively. It then follows that:
Based on these design equations, the following parametric choices may be important:
Initial design values are chosen with these considerations in mind, as shown in Table 1.
Initial values for rfb and cfb are set to 1 kΩ and 100 fF, respectively. The resulting transfer curves for RL=50Ω and initial design values are shown in
Next, a robust global optimization is run until the design goals as shown in Table 2 are met.
Goal 1 sets an overvoltage requirement of at least 300 mV for each transistor to enforce linear transfer, which is the highest priority. Goal 2 requires transistors that form part of the RF path to be biased for optimal fT, which corresponds to approximately 100 μA per μm gate width. Goals 3-5 and 6-8 aim to reduce transfer errors and increase bandwidth. The −3 dB bandwidth is determined relative to the values of α and β at f=0 Hz.
After running the optimization, the resulting transfer curves are shown in
Optimized design values are shown in Table 3, with optimal values for rfb and cfb found as 1.2 kΩ and 360 fF, respectively.
Resulting impedance magnitudes at the various ports are further shown in
Next, the stability of the optimised CCII 100 is investigated and suitable values for rfb, cfb, which may be used by the post-production tuning mechanism, are determined.
Applying the stability analysis procedure presented above, a single feedback path can be found that breaks all loops, as indicated by the dotted line in
Finally, it is also important to consider the effects of process tolerances on stability, as shown in
The CCII 100 may be manufactured using the AMS AG 0.35 μm CMOS process. A micrograph of the top-view is shown in
A PCB is designed to house the IC and supply the necessary bias voltages and RF test signals, as shown in
Measured results are shown in
To illustrate further the importance of performing a stability analysis when designing high-precision CCIIs, the simulated CCII proposed in [10] is implemented in 0.35 μm CMOS and manufactured without stability analysis, as shown in
Next, the multi-loop analysis described above is performed on the circuit. Two feedback loops are identified as shown in
The oscillation frequency is measured as 480 MHz, which corresponds well to the theoretical prediction of ˜500 MHz. This result further supports the validity of the presented multi-loop analysis methodology.
The Applicant believes that the invention as described in the example embodiment discloses a high-precision, high bandwidth CMOS CCII with a post-production tunable phase margin and peaking compensation network. A transfer error of roughly 1.15% is achieved with a bandwidth of 500 MHz and RX<5Ω in 0.35 μm CMOS. A practical numerical optimisation based design methodology has been presented using accurate device models as well as layout parasitics, allowing good agreement with measured results to be obtained. It has been shown that process tolerances can result in more than 100% bandwidth variation, with layout parasitics contributing up to 20% in bandwidth reduction. This illustrates the need for detailed corner and layout parasitic simulations during design stages. Additionally, a rigorous multi-loop feedback analysis methodology has been applied to the design and analysis of CCIIs for the first time. It is shown, using an example of a high-precision CCII from literature and measured results, that failure to perform a multi-loop analysis can lead to an unstable design.
The Applicant believes that a field of application of the CCII as described in an example embodiment is in high-speed microelectronic design, particularly used in telecommunications systems and devices. With the continuously increasing speed requirements of modern telecommunication and data processing systems and the bandwidth, power and cost advantages of analogue solutions over their digital counterparts, CCIIs could play an important role in future high-speed microelectronic design.
Filing Document | Filing Date | Country | Kind |
---|---|---|---|
PCT/IB2018/058805 | 11/9/2018 | WO | 00 |