1. Field of the Invention
The present invention relates to superconducting devices and more particularly to a method for forming a vertical resistor on an integrated circuit, for example, a superconducting integrated circuit, using Al/AlOx/Al, which not only reduces the chip area of the resistor but provides across wafer uniformity as a function of the self-limiting oxidation of the aluminum and is not a strong function of the deposition uniformity since the spreading resistance effects occur in a relatively low resistance portion of the resistor structure and thus has a negligible effect on the overall resistance.
2. Description of the Prior Art
Integrated circuits formed with superconducting junctions are generally known in the art. An example of such an integrated circuit is disclosed in commonly owned U.S. Pat. No. 5,892,243, hereby incorporated by reference. Such superconducting junctions are known as Josephson junctions. Various types of Josephson junctions are known, such as disclosed in U.S. Pat. Nos. 4,785,426; 4,985,117; 5,278,140; 5,411,937 and 5,560,936.
In general, Josephson junctions are formed on a substrate, such as Si or thermally oxidized Si. A superconducting material is deposited on a substrate forming two contiguous superconducting regions. Such superconducting materials are known to be selected from materials, such as, Nb, NbN, NbCN, NbTiN, Pb. Nb and NbN are known to be preferred superconducting materials.
Such superconducting integrated circuits are known to be used to form logic circuits. Examples of such logic circuits are disclosed in U.S. Pat. Nos. 4,092,553; 4,371,796; 4,501,975; 4,785,426 and 5,051,627 all hereby incorporated by reference. Such superconducting logic circuits are adapted to be used in a relatively wide range of applications, such as digital signal processing systems and high-performance network switching. Such applications utilize Josephson junctions as well as superconductive quantum interference devices (SQUID) in which two or more Josephson junctions are connected together in a superconducting loop. Examples of such SQUID devices are disclosed in U.S. Pat. Nos. 4,785,426; 5,135,908 and 5,278,140, hereby incorporated by reference.
One type of logic circuits is known as a single flux quantum (SFQ) type circuit. Examples of such SFQ circuits are disclosed in U.S. Pat. Nos. 5,942,997 and 5,552,735. In such SFQ circuits, each logic operation corresponds to a single flux quantum transition of a Josephson junction or SQUID. Essentially data is stored as a magnetic flux quanta in the conductor of the SQUID. Data is transmitted between gates by a current pulse resulting from SFQ transitions of logic operations.
New applications have been developed, for example, satellite applications, in which the integrated circuit dimensions need to be reduced. For example, high speed SFQ circuitry requires relatively high circuit density to allow increased functions per chip and increased speed of operation. Such circuitry requires shunting resistors, known to be laid out such that the current flows parallel to the substrate. In such a configuration, the shunting resistor consumes much of the chip area and adds to the parasitic inductance of the circuit. In order to solve this problem, attempts have been made to form vertical resistors. With such vertical resistors, the current flows normal to the substrate and takes up relatively less chip area than known resistors and have relatively less parasitic inductance. However, there are problems associated with such vertical resistors in these applications. In particular, such shunt resistors are normally in contact with a superconducting film which forms a superconducting interconnect material, such a niobium (Nb) or nitrogen doped niobium (NbN). As such, the resistor material needs to be cleaned prior to deposition of the Nb or NbN. As is known in the art, the cleaning process significantly reduces the quantity and value of the resistor. As such, the uniformity of the resistance across the chip and wafer becomes dependent upon the cross wafer uniformity of the thickness of the resistor material. Thus, there is a need for a method for forming vertical resistors on an integrated circuits that is less affected by processes, such as cleaning, prior to the deposition of the superconducting interconnect material.
The present invention relates to a structure and a method for forming a vertical resistor on a superconducting integrated circuit. The resistance structure is formed from a Al/AlOx/Al material system. In particular, the resistance structure includes a layer of aluminum, in-situ oxidation of the aluminum surface and further deposition of aluminum. The resistance of the Al/AlOx/Al structure primarily comes from the aluminum oxide layer rather than the aluminum. As such, any aluminum removed during the interconnect pre-cleaning process will have a negligible impact on the overall resistance of the structure. The value of resistance of the vertical resistors fabricated in this fashion can be varied by varying the oxygen pressure during oxidation. Varying the oxidation pressure from 1 to 80 mT oxygen can create resistors with resistances from 3 to 0.03 ohms for a given junction size.
These and other advantages of the present invention can be readily understood with reference to the following specification and attached drawings wherein:
a-3e illustrate exemplary step-by-step process diagrams illustrating the various process steps involved in forming a resistance structure in accordance with the present invention.
The present invention relates to a vertical resistance structure for use with integrated circuits which include superconducting junctions or films. An example of such an integrated circuit structure is disclosed in commonly owned U.S. Pat. No. 5,892,243, hereby incorporated by reference. Such circuits have been known to employ shunting resistors formed as vertical resistance structures. An example of a known superconducting circuit utilizing vertical shunting resistors is disclosed in: P. Wolf, “Use of Paramagnetic or Other Impurities in Josephson Technology”, IBM Technical Disclosure Bulletin, Vol. 18, No. 8, January 1976, page 2645. As discussed above, the resistance structure is normally cleaned prior to the deposition of the interconnect material which results in a resistance that is a function of the uniformity of the thickness of the material across the wafer. The present invention solves this problem by utilizing a material system in which the cleaning process has a negligible effect on the resistance. In particular, as will be illustrated in three exemplary configurations, illustrated in
The value of resistance of the vertical resistors fabricated in this fashion can be varied by varying the oxygen pressure during oxidation. Varying the oxidation pressure from 1 to 80 mT can create resistors with resistances from 3 to 0.03 ohms for a given junction size.
The process is amenable to be formed with a planar configuration as illustrated in
Referring to
As shown in
As mentioned above, the aluminum layer 36 is normally cleaned by conventional techniques, such as, ion-beam etching or RF plasma etching, prior to deposition of the Nb interconnect material. Such cleaning processes are known to remove a portion of the resistance material systems. As such, a portion of the aluminum layer 36 is removed by the cleaning process prior to deposition of Nb interconnect layer 30. Since the resistance of a material is known to be proportional to the quantity or volume of the material, such removal of a portion of the aluminum layer 36 normally results in lowering of the overall resistance. However, by choosing a Al/AlOx/Al material system for the resistance structure, such removal will have a negligible effect on the overall resistance since the major or dominant portion of the resistance is from the AlOx layer 34. As such, the process lends itself to a cross wafer uniformity as a function of the aluminum self-limiting oxidation and is not a strong function of the deposition uniformity or the amount removed during the cleaning process.
Another exemplary embodiment of the invention is illustrated in
In this embodiment, an aluminum layer 48 is deposited on the surface of the substrate 38, the step 44 and a portion of the dielectric layer 42 are defined by lithograpic techniques. The surface of the aluminum layer 48 is allowed to oxidize forming an aluminum AlOx layer 50. Another aluminum layer 52 is then deposited on top of the AlOx layer 50. As shown in this embodiment, the aluminum layer 52 may have a relatively greater thickness than the aluminum layer 48 to account for the material lost during the cleaning process.
a-3e illustrate exemplary step-by-step process diagrams for forming a resistance structure in accordance with the present invention. Initially, a niobium layer 60 may be deposited on a substrate 62, for example, 200 nm (nanometers) thick. An aluminum layer 64, is then deposited on top of the niobium layer 60 by conventional techniques. In-situ oxidation of the surface of the aluminum layer 64 is allowed until approximately 1 nm layer AlOx is formed, forming a AlOx layer 66. Another aluminum layer 68, for example, 8 nm, is formed on top of the AlOx layer 66. Another niobium Nb layer 70 may be deposited on top of the aluminum layer 68 to form a pentalayer structure 72 illustrated in
Referring to
A dielectric, such as SiO2, 150 nm, is deposited by sputter deposition on top of the structure illustrated in
In all of the embodiments, the aluminum is fabricated in such fashion so as not to allow the proximity effect to extend to the aluminum oxide layer. This can be accomplished by 1) sufficiently thickening the layers of aluminum; 2) decreasing the mean free path within the aluminum by a lattice disorder; 3) or intentionally depositing a low mean free path material to reduce the coherence length within the resistor. Titanium layers may be used to reduce the proximity effect within the resistor without adding significantly to the overall resistance.
In order to prevent the proximity effect from extending into the aluminum oxide layer, it is important that the layer overlying the AlOx barrier be thick enough or “dirty” enough to prevent superconducting tunneling through the barrier. As such, the layer of aluminum overlying the AlOx barrier must be greater than 30 nm. In accordance with the second approach discussed above, this thickness can be reduced by making “dirty” aluminum. As is known in the art, “dirtying” can be accomplished by doping the aluminum with paramagnetic impurities or with small amounts of oxygen O or nitrogen N, for example, as generally discussed in “Use of Paramagnetic or Other Impurities in Josephson Technology”, by P. Wolf, IBM Technical Disclosure Bulletin, Vol. 18, No. 8, January 1978, pgs. 26-45, hereby incorporated by reference. For example, the aluminum can be deposited relatively slowly in the presence of the partial pressure of oxygen or nitrogen. The aluminum should be at least greater than 10 nm thick. The third approach, discussed above, consists of depositing greater than 10 nm of any number of materials with intrinsically lower coherence length, such as, titanium, molybdenum or nitrogen poor niobium nitride on the AlOx.
Obviously, many modifications and variations of the present invention are possible in light of the above teachings. Thus, it is to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described above.