Patent Application
20240372458
The USB industry standard has been widely adopted for charging and powering mobile devices, such as cell phones, laptop computers, tablet computers, and similar. These devices often have different power requirements and adhere to various USB versions and connector types, such as USB Type-A, USB Type-B, and USB Type-C.
Most mobile devices are provided by their respective manufacturer with a dedicated charger. However, consumers may wish to have a multi-port charger that can supply a DC power output to more than one device at a time. For example, some consumers may desire a multi-port charger that is operable to charge their cell phone and wireless headphones simultaneously. As such, the demand for power supply solutions that are compact, efficient, and versatile has significantly increased.
Conventional solutions for providing power to multiple USB devices simultaneously have had several limitations, including restrictions on maximum voltages, inefficient power conversion, and large form factors.
In some aspects, the techniques described herein relate to a power converter including, an AC/DC converter configured to generate a first secondary side output voltage based on an AC input voltage, the first secondary side output voltage being a first DC voltage; and a multi-port DC output circuit configured to receive the first secondary side output voltage from a first output node of the AC/DC converter and to provide respective DC output voltages to a first DC output port and a second DC output port, the multi-port DC output circuit including a first intermediate rail voltage switch, a second intermediate rail voltage switch, and a plurality of bus switches, a body diode of the first intermediate rail voltage switch being forward biased with respect to the first secondary side output voltage, and a body diode of the second intermediate rail voltage switch being reverse biased with respect to the first secondary side output voltage; wherein: the plurality of bus switches are configured to control a routing of a first intermediate rail voltage and a second intermediate rail voltage of the multi-port DC output circuit to the first DC output port and the second DC output port in response to a plurality of gate control signals.
Conventional solutions for providing power to multiple USB devices simultaneously have had several limitations, including restrictions on maximum voltages, inefficient power conversion, and large form factors. This is because conventional power converters often utilize at least one inductor per DC output, which can lead to increased complexity, power dissipation, cost, and size. Furthermore, these conventional solutions typically do not account for the dynamic power requirements of different USB devices, leading to inefficient power management and potential damage to the connected devices.
To elaborate, AC/DC converters with multiple DC outputs conventionally have a separate DC/DC converter dedicated to each output. In some conventional solutions, each DC/DC converter includes a respective inductor or transformer winding, each of which adds to the material cost and design complexity of the AC/DC converter. Disclosed herein are AC/DC converters that distribute power from a single transformer to multiple voltage output ports without requiring separate inductors for each voltage output, thereby advantageously reducing the cost and size of the AC/DC converters as compared to conventional solutions. Additionally, several of the AC/DC converters disclosed herein advantageously reduce the number of high-power dissipation switches (i.e., switches with a high RDS (on) resistance) in the respective output power path as compared to conventional solutions.
As disclosed herein, reducing the number of switches that receive a high peak current is achieved, in part, by configuring the multi-port DC converters such that at least one DC output port is of a higher voltage than that of one or more other DC output ports. By reducing the number of switches in the high peak current path while still maintaining the ability for the DC output ports to each provide a wide range of voltages, lower power dissipation is achieved with relatively low-cost switches.
Additionally, by not requiring a separate DC/DC power converter to be used for each DC output port, the cost and size of the solution can be reduced. As disclosed herein, rather than using a separate DC/DC power converter for each DC output port, output power from a single AC/DC power converter is routed to multiple DC output ports. The peak current across each of the switches used for routing the output power from the AC/DC converter may be significantly higher than an average current, which conventionally results in a high power dissipation due to a high RDS (on) of the switches. However, several of the multi-port DC output circuits disclosed herein advantageously limit the peak current to just a small number of low RDS (on) switches, thereby reducing design cost and size as compared to conventional solutions which may require a greater number of low RDS (on) switches to limit power dissipation.
Attention is initially drawn to
A voltage source Vin′ is received at the power converter 100. The voltage source Vin′ can be provided either as an alternating current (AC) or direct current (DC). An input side of the power converter 100 generally includes an input voltage filter block 122, a rectifier block 116 (in the case of AC input), an input voltage buffer capacitor CB, an active clamp circuit that includes an active clamp capacitor CC and an active clamp switch M3 driven by a pulse-width-modulation (PWM) control signal PWMM3, a main switch M1 driven by a PWM control signal PWMM1, and a primary side controller circuit 118. The input voltage filter block 122, the rectifier block 116, and the input buffer capacitor CB provide a filtered, buffered, rectified, or otherwise conditioned input voltage Vin (i.e., a DC input voltage at a DC voltage input node) to a transformer 102.
The transformer 102 transfers power from the primary side of the power converter 100 to a secondary side of the power converter 100 and generally includes a primary winding 104 with a first terminal 108 and a second terminal 110. Also shown is an output node 128 of a secondary winding of the transformer 102.
The output side of the power converter 100 generally includes a secondary winding 106 of the transformer 102, a synchronous rectifier switch M2, a secondary side controller circuit 120, and is configurable to provide power to a multi-port DC output circuit 130, as disclosed herein. Alternative example embodiments of the multi-port DC output circuit 130 are described with reference to
As described in greater detail below, the secondary side controller circuit 120 includes a control logic circuit 120a, gate driver circuits 120b, and optional charge-pump circuits 120c. In some embodiments, the charge-pump circuits 120c are operable to receive a DC input voltage (e.g., Vin, or a voltage generated using an auxiliary winding of the transformer 102 (not shown)) and to generate a configurable gate drive voltage that is subsequently used by the gate driver circuits 120b to generate all or a portion of the plurality of gate control voltages. The secondary side controller circuit 120 is operable to provide a synchronous rectifier switch control signal PWMM2, via the gate driver circuits 120b, to a synchronous rectifier switch M2, as well as to provide gate control signals to the switches associated with the multi-port DC output circuit 130, as described below.
The first terminal 108 of the primary winding 104 receives the DC input voltage Vin. The second terminal 110 of the primary winding 104 is coupled to a drain node of the main switch M1 and the active clamp switch M3. The main switch M1 controls a magnetizing current im through the primary winding 104 to charge a magnetizing inductance LM 105 of the transformer 102 during a first portion of a switching cycle of the power converter 100. The synchronous rectifier switch M2 controls a secondary side current flow is through the secondary winding 106 to discharge a secondary side inductance LS 107 of the transformer 102 into the multi-port DC output circuit 130 during a subsequent portion of the switching cycle.
When the main switch M1 is enabled by the primary side controller circuit 118 during a first portion of a switching cycle of the power converter 100, current flows through the primary winding 104 to a voltage bias node such as ground. The current flow im through the primary winding 104 causes energy to be stored in the magnetizing inductance LM 105 and a leakage inductance LL (not shown) of the transformer 102. When the main switch M1 is disabled in a subsequent portion of the switching cycle, a secondary side output voltage Vsec+ and the secondary side current is are provided to the multi-port DC output circuit 130. When the main switch M1 is turned off, a reflected voltage (nVout, not shown) is developed at the primary winding 104. The contribution of the reflected voltage nVout to a drain-source voltage VdsM1 of the main switch M1 at the second terminal 110 is expressed as:
where n is a turns ratio of the transformer 102. Energy stored in the leakage inductance LL of the transformer 102 also contributes to the voltage VdsM1 developed at the second terminal 110 and charges the active clamp capacitor CC via a resonant clamp current iclamp. The active clamp circuit prevents the voltage VdsM1 from increasing to a level that damages the main switch M1.
A first DC output port 241 is labeled Port1, and a second DC output port 242 is labeled Port2. In some embodiments, the gate control signals Out1G1, Out2G1, Bus1G1-2, and Bus2G1-2 are produced by the secondary side controller circuit 120. In other embodiments, the gate control signals may be produced by one or more USB port manager modules (e.g., which may be implemented using the control logic circuits 120a). The multi-port DC output circuit 230 advantageously works with any configuration on the AC side of the power converter 100 and is not limited to the flyback configuration shown. For example, in some embodiments, the secondary side output voltage Vsec+ at the output node 128 could be provided by an LLC power converter, etc.
As disclosed herein, the multi-port DC output circuit 230 is configured such that the intermediate rail voltage Vout1 is always kept at a higher voltage than the intermediate rail voltage Vout2. As shown, a parasitic body diode of the intermediate rail voltage switch SV1 is forward biased with respect to the secondary side output voltage Vsec+, and a parasitic body diode of the intermediate rail voltage switch SV2 is reverse biased with respect to the secondary side output voltage Vsec+.
Because of the resultant voltage drop across the body diodes of the intermediate rail voltage switches SV1-2 discussed above, the secondary side output voltage Vsec+ will always stay at a voltage no more than a diode drop (e.g., about 0.7V) above the intermediate rail voltage Vout1 and no more than a diode drop below the intermediate rail voltage Vout2. This advantageously allows a single intermediate rail voltage switch (SV1) to be used between Vsec+ at the node 128 and the intermediate buffer capacitor C1, as well as for a single intermediate rail voltage switch (SV2) to be used between Vsec+ at the node 128 and the intermediate buffer capacitor C2. The voltage rating needed for SV1 and SV2 can thereby be limited to about 0.7V above the highest setting for the output voltage Vout1, plus a small amount of margin to allow for parasitic ringing when SV1 is turned ON.
The synchronous rectifier switch M2 shown in
Recent industry trends, particularly the usage of USB Type-C power delivery, have increased the need for system awareness and control of the voltage and power levels provided to multiple DC output ports from a single AC power supply. This is sometimes implemented by each DC output port having a port manager module that communicates with connected devices and to each other to share available AC/DC power and to reduce power levels if the temperature, as monitored inside or on the system packaging, rises above a specified level. An alternative implementation is to use a single port manager module that measures and collects voltage, current, and temperature information from inside the system packaging as well as requests and information from devices connected to the ports in order to set and communicate voltage, current, and power levels for each DC output port. In some embodiments, the secondary side controller circuit 120 may include one or more DC output port manager modules and is thereby operable to control any of the example embodiments of the multi-port DC output circuit 130 disclosed herein.
Since such port manager modules can be implemented with digital control and firmware using one-time programmable (OTP) or multiple-time programmable (MTP) memory, the firmware or other programmable memory of a single port manager module can be used to drive many different switch configurations (such as those of the additional embodiments of multi-port DC output circuits disclosed herein) and also to configure how those switches are turned on and off.
If a port manager module recognizes that only a single DC output port is connected to a load, each of the intermediate output voltages Vout1-2 can be directly provided to the particular DC output port that has a load connected to it. For example, with reference to
Operation of the power converter 100 when configured to use the multi-port DC output circuit 230 is illustrated in the simplified plots 300 shown in
In the example shown, the DC output voltage at Port1 and associated power levels are higher than those of Port2. In this case, the bus switches SB1, SB5, and SB6 are ON while the switches SB2, SB3, and SB4 are OFF in order to electrically connect Vout1 to Port1 241 and Vout2 to Port2 242.
If, alternatively, the voltage and power delivered by Port2 were requested to be higher than those of Port1, then the switches SB2, SB3, and SB4 would be turned ON and the switches SB1, SB5, and SB6 would be turned OFF in order to electrically connect the intermediate rail voltage Vout to Port2 242 and to electrically connect the intermediate rail voltage Vout2 to Port1 241.
At time t1, the primary side main switch M1 is enabled by the main switch control signal PWMM1 302 and the magnetizing current in 312 begins to flow through the primary winding 104 to charge the magnetizing inductance LM. The intermediate rail voltage switch SV1 is in an ON state based on an asserted level of the gate control signal Out1G1, and the intermediate rail voltage switch SV2 is in an OFF state based on a de-asserted level of the gate control signal Out2G1. Between the time t1 and t2, the magnetizing current im increases at a rate designated as Slope1, which is equal to
During this time period, the secondary side current is 314 is equal to 0. At time t2, the magnetizing current im 312 and the secondary side current is 314 are at respective maximum levels for the switching cycle. Also at time t2, the main switch M1 is disabled by the main switch control signal PWMM1 302 and the secondary side current is 314 begins to flow to a load connected at Port1 241 of the multi-port DC output circuit 230 since the intermediate rail voltage switch SV1 is ON and the intermediate rail voltage switch SV2 is OFF.
Between the time t2 and t3, the secondary side current is decreases at a rate designated as Slope2, which is equal to
At time t3, the intermediate rail voltage switch SV1 is disabled via the gate control signal Out1G1 306, and the intermediate rail voltage switch SV2 is enabled via the gate control signal Out2G2 308. As shown by the plot of the secondary side output voltage Vsec+ 310, the secondary side output voltage Vsec+ almost instantly (e.g., within a few nanoseconds) transitions from the intermediate rail voltage level Vout1 to the intermediate rail voltage level Vout2 upon state transition of the intermediate rail voltage switches SV1-2. As such, between time t3 and t4, power is delivered to a load connected at Port2 242. During this period, the secondary side current decreases at a rate designated as Slope3 which is equal to
At time t4, the intermediate rail voltage switch SV1 is re-enabled via the gate control signal Out1G1 306, and the intermediate rail voltage switch SV2 is disabled via the gate control signal Out2G1 308. Once again, as shown by the plot of the secondary side output voltage Vsec+ 310, the secondary side output voltage Vsec+ almost instantly (e.g., within a few nanoseconds) transitions from the voltage level Vout2 to the voltage level Vout1 upon state transition of the intermediate rail voltage switches SV1-2. As such, between time t4 and t5, power is once again delivered to the load connected at Port1 241. During this period, the secondary side current is 314 decreases at the rate designated as Slope2. At time t5, the main switch M1 is enabled, and a new switching cycle of the power converter 100 begins.
The simplified plots 300 shown in
In the example shown in the simplified plots 300, the secondary side transformer current is 314 is equal to the current through the synchronous rectifier switch M2 shown in
Thus, because the current through the bus switches SB1-6 is lower than a peak secondary side current, lower-cost bus switches having a much higher RDS (on) as compared to the intermediate rail voltage switches SV1-2 may be advantageously used in the multi-port DC output circuit 230 and still maintain acceptable power dissipation levels.
Additionally, as shown in
For an active clamp flyback converter, one DC output port can also be chosen to receive current during the period that the active clamp switch M3 is turned on to discharge the active clamp capacitor CC, thereby increasing the output current delivered during that time. Additionally, if the lower output power is delivered at a lower voltage, the secondary side current is waveform 314 is more trapezoidal in shape, so the current peak is not as high as for a triangle waveform (e.g., as illustrated in
Alternatively, when loads connected to the DC output ports of the multi-port DC output circuits are balanced, energy savings can be achieved by always having the secondary side output voltage Vsec+ connected to the higher of the intermediate rail voltages at the beginning and the end of the main switch M1 off-time, and only turning on the active clamp switch M3 at the end of the main switch M1 off-time. Since the beginning and the end of the main switch M1 off-time are the only times where current is conducted in the active clamp switch M3, this technique limits the current spikes and thus power dissipation experienced by the active clamp switch M3.
Power dissipation in the power converter 100 tends to be less when the power dissipation levels for the switches of the multi-port DC output circuit to each DC output port thereof are equal. This may be achieved by delivering charge to each DC output port of the multi-port DC output circuit at the correct times during the off-time of the main switch M1 such that the I2×R losses to each output are the same. For configurations of the multi-port DC output circuits with three DC outputs, this can be achieved by delivering charge to two out of the three outputs at two different times during the off-time—for example, by delivering charge to the intermediate voltage rail for Vout at the beginning of the off-time of the main switch M1, then to the intermediate voltage rail for Vout2, then to the intermediate voltage rail for Vout3, then to Vout2 again, and then to Vout1 once more at the end of the main switch M1 off-time.
In addition to maintaining an acceptable power dissipation level of the multi-port DC output circuit 230, additional power savings may be achieved by using a low-cost charge-pump 120c to increase the gate control voltage Vgs of the intermediate rail voltage switches SV1-2, generated by the gate drivers 120b, to further reduce their RDS (on) for circuit configurations or conditions in which they remain on and do not need to be switched during the switching cycle. For example, in many common discrete FET switches, increasing the applied gate control signal voltage Vgs from 5V to 10V results in approximately 25% reduction in on-resistance RDS (on).
One example of when the intermediate rail voltage switches SV1-2 stay on all the time rather than switching every switching cycle is in which only a single DC output port is in use; alternatively, for the alternative embodiments in
Thus, in some embodiments, the low-cost charge-pump circuit 120c is part of the secondary side controller circuit 120 or may be part of one or more port controller modules (not shown) that control the multi-port DC output circuits disclosed herein. In some embodiments, the output current from a single charge-pump circuit is selectively routed to two or more gates of the switches used in the multi-port DC output circuits disclosed herein. In other embodiments, multiple charge-pump circuits are used to control the switches used in the multi-port DC output circuits disclosed herein.
The charge-pump circuit 120c can advantageously provide a weak output current for output configurations or conditions where the intermediate rail voltage switches SV1-2 do not switch frequently, and therefore do not need to transition state rapidly. That is, if the intermediate rail voltage switches SV1-2 need to switch during each switching period of the power converter 100, the charge pump output current would have to be much stronger than as disclosed herein in order to achieve a high switching rate, and the switching losses due to driving the gate on to a higher Vgs every switching period could be quite high (more than offsetting the reduction in on resistance). Such switching losses account for why some form of a bootstrap voltage to a lower Vgs is typically used rather than an internal charge pump for switches that are turned on and off every switching cycle. In such embodiments, a first gate terminal of the first intermediate rail voltage switch SV1 is configured to receive the output of a charge pump circuit of the charge pump circuits 120c via the gate driver circuits 120b. Similarly, a second gate terminal of the second intermediate rail voltage switch SV2 is configured to receive the output of a charge pump circuit of the charge pump circuits 120c via the gate driver circuits 120b. As mentioned above, in some embodiments, each of the intermediate rail voltage switches SV1-2 is associated with a dedicated charge pump circuit of the charge pump circuits 120c. In other embodiments, a single charge pump circuit of the charge pump circuits 120c is used to control multiple switches.
As disclosed herein, for some cost-sensitive systems, two intermediate voltage rails are operable to provide power (i.e., Vout1-2) to more than two DC output ports. For example, a popular USB port configuration is to have two USB Type-C ports and one USB Type-A port (i.e., to mostly service older USB devices). For such systems, it is often unlikely that all three ports will be plugged in at the same time, and if they are, it may be acceptable if the port or system's output power capability is not as high and/or some restrictions are placed on voltage levels for one or more of the ports.
As disclosed herein, one technique to provide power to more DC output ports than the number of intermediate rail voltages (e.g., two intermediate rail voltages supplying power to three DC output ports) is to provide power to two DC output ports that have the same voltage with a single intermediate voltage rail. For USB power delivery as an example, two DC output ports having the same output voltage is a relatively common occurrence as many devices will set their output voltage to either 5V, 9V, 15V, or 20V (with a few higher voltages up to 45V also available as part of the newer USB “extended power range”). Since the current delivered to each DC output port is typically monitored using the RDS (on) of one of the bus switches (e.g., SB1-6) or via a resistor in series with those switches, the current can still be monitored and the gate control signal voltage Vgs of those bus switches may be regulated to reduce the current to one DC output port while not affecting the other(s).
This technique can also be utilized if, for example, only two devices that both require the same output voltage are connected to the multi-port DC output circuit. In such instances, both DC output ports could be electrically connected to both of the intermediate rail voltages in order to advantageously leave the intermediate rail voltage switches SV1-2 ON throughout the switching cycle.
Several alternative example embodiments of multi-port DC output circuits for realizing the multi-port DC output circuit 130 are disclosed herein. Each embodiment is operable to work with the same type of port manager chip or chips and with the same type of charge pump circuit as disclosed herein.
In some embodiments of the multi-port DC output circuits disclosed herein, pairs of serially connected intermediate rail voltage switches, such as SV1-2 and SV3-4, are configured for independent control such that one of the serially connected switches within a pair remains on throughout a switching cycle and the other switch may be transitioned more frequently. In such embodiments, a low-cost charge pump circuit (i.e., having a weak output drive) as described above may provide a gate control signal to the intermediate rail voltage switches which remain on, and it can drive those always ON switches Vgs to a higher voltage than other switches, thereby advantageously reducing the RDS (on) of those switches. For example, if the intermediate rail voltage Vout1 is higher than the intermediate rail voltage Vout2, the intermediate rail voltage switches SV2 and SV3 of the multi-port DC output circuit 430 may driven by a low-cost (i.e., having a weak output) charge pump to remain enabled for a duration of the switching cycle while the intermediate rail voltage switches SV1 and SV4 may transition state depending on power deliver requirements to loads of the multi-port DC output circuit 430.
In the example shown, there are a total of nine switches (plus the synchronous rectifier switch M2 shown in
In the example shown, there are a total of nine switches (plus the synchronous rectifier switch M2 shown in
In the example shown, there are a total of eleven switches (plus the synchronous rectifier switch M2 shown in
In the example shown, there are a total of eleven switches (plus the synchronous rectifier switch M2 shown in
In the example shown, there are a total of twelve switches (plus the synchronous rectifier switch M2 shown in
In the example shown, there are a total of sixteen switches (plus the synchronous rectifier switch M2 shown in
The multi-port DC output circuit 1030 is operable to provide power to a USB Type-A port with no voltage restrictions on the other two ports. Some thermal throttling may be implemented to deliver up to 65 W on some output voltage/current combinations.
In the example shown, there are a total of ten switches (plus the synchronous rectifier switch M2) used to deliver power to the DC output ports. The center tap 1129 of the secondary side winding provides significant improvements to the power dissipation of the multi-port DC output circuit 1130 as compared to the multi-port DC output circuit 230 when the intermediate rail voltages Vout1 and Vout2 are far apart in voltage levels.
In the example shown, there are a total of 11 switches (plus the synchronous rectifier switch M2) used to deliver power to the DC output ports, but only the intermediate rail voltage switches, SV1-4, plus the synchronous rectifier switch M2 need to be implemented as low RDS (on) switches to reduce power dissipation. The center tap 1229 of the secondary side winding provides significant improvements to the power dissipation of the multi-port DC output circuit 1230 as compared to the multi-port DC output circuit 630 when the intermediate rail voltages Vout1 and Vout2 are far apart in voltage level. If all three DC output ports Port1-3 are used at the same time, VBUS3 must have the same output voltage as either VBUS1 or VBUS2, with the remaining output voltage having the same or higher voltage. If only one USB Type-C and USB Type-A device is connected, the USB Type-A device must be at the same or lower voltage as that of the USB Type-C device.
In the example shown, there are a total of 13 switches (plus the synchronous rectifier switch M2) used to deliver power to the DC output ports, but only two of the intermediate rail voltage switches, SV1-4, plus the synchronous rectifier switch M2 need to be implemented as low RDS (on) switches to reduce power dissipation. The center tap 1329 of the secondary side winding provides significant improvements to the power dissipation of the multi-port DC output circuit 1330 as compared to the multi-port DC output circuit 730 when the intermediate rail voltages Vout1 and Vout2 are far apart in voltage level. If all three ports Port1-3 are used at the same time, VBUS3 must be the same output voltage as either VBUS1 or VBUS2. If only two ports are in use, there are no restrictions on the voltage output thereof.
An example of operation of the power converter 100 configured to use the multi-port DC output circuit 230 when a primary side active clamp circuit is used is illustrated in the simplified plots 1400 shown in
In the example simulation shown, a lower level of power is provided to a first DC output port of the multi-port DC output circuit 230 for four initial switching cycles, and then a higher level of power is provided to a second DC output port of the multi-port DC output circuit 230 for the subsequent two switching cycles.
Reference has been made in detail to embodiments of the disclosed invention, one or more examples of which have been illustrated in the accompanying figures. Each example has been provided by way of an explanation of the present technology, not as a limitation of the present technology. In fact, while the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. For instance, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present subject matter covers all such modifications and variations within the scope of the appended claims and their equivalents. These and other modifications and variations to the present invention may be practiced by those of ordinary skill in the art, without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the invention.
This application claims priority to U.S. Provisional Patent Application No. 63/499,540, filed May 2, 2023, all of which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63499540 | May 2023 | US |
