The subject matter disclosed herein relates to power conversion, and more specifically to precharging circuitry for motor drives and other power converters.
Various aspects of the present disclosure are now summarized to facilitate a basic understanding of the disclosure, wherein this summary is not an extensive overview of the disclosure, and is intended neither to identify certain elements of the disclosure, nor to delineate the scope thereof. Rather, the primary purpose of this summary is to present various concepts of the disclosure in a simplified form prior to the more detailed description that is presented hereinafter. The present disclosure provides precharging systems for limiting inrush current while charging a DC bus capacitance through a normally closed switch and a precharging resistance with a controller to open the precharging switch and enable rectifier switches when the DC bus voltage reaches a threshold. In addition, the disclosure provides circuitry to mitigate voltage spikes in excessive rectifier output voltages to ground.
The following description and drawings set forth certain illustrative implementations of the disclosure in detail, which are indicative of one or more exemplary ways in which the various principles of the disclosure may be carried out. The illustrated examples are not exhaustive of the many possible embodiments of the disclosure. Various objects, advantages and novel features of the disclosure will be set forth in the following detailed description when considered in conjunction with the drawings, in which:
Referring now to the figures, one or more embodiments or implementations are hereinafter described in conjunction with the drawings, wherein the various features are not necessarily drawn to scale.
The system 2 also includes a precharging system 10 with a precharging circuit 11 having diodes D1, D2 and D3 along with a precharging resistance RPC and a normally closed switch circuit 12 operated according to a switching control signal 14 from a precharging controller 16, where the precharging diodes D1-D3 have anodes connected to corresponding AC input lines and cathodes connected to the precharging resistance RPC as shown. The rectifier 18 in the illustrated embodiment includes an upper set of switching rectifiers, which can be SCRs SCR1, SCR2 and SCR3 as shown or other suitable controllable switching devices coupled between a corresponding AC input line and an upper rectifier output node 42, along with rectifier diodes D4, D5 and D6 with anodes coupled to a second (e.g., negative) rectifier output node 44 and cathodes connected to corresponding AC input lines.
The intermediate DC bus circuit 24 includes upper and lower (e.g., positive and negative) DC link inductances LP and LN, respectively, connected between the first and second rectifier outputs 42 and 44 and positive and negative DC bus nodes 46 and 48 respectively forming first and second inverter inputs of the switching inverter 28. A DC bus capacitance C1 is coupled between the inverter input nodes 46 and 48. In operation, the precharging system 10 maintains the precharged switching circuit 12 in the normally closed state and prevents the upper rectifier SCRs SCR1 , SCR2 and SCR3 from conducting using SCR control signals 17 upon system power up until the voltage VDC across the DC bus capacitance C1 meets or exceeds a non-zero threshold voltage VTH1. At this condition, the precharged controller 16 opens the precharging switch circuit 12 to discontinue conduction through the resistance RPC and allows gating of the SCRs of the rectifier 18 for normal rectifier operation to maintain the DC bus voltage across the capacitance C1. The DC bus voltage VDC is provided across the inverter inputs 46 and 48, with the inverter 28 including switches (e.g., IGBTs, FETs, or other suitable form of electrical switches) operated by suitable control signals from an inverter controller 30 to provide a controlled AC output through the cable 32 to operate the motor load 6 according to one or more desired output operating parameters, such as output speed or frequency, torque, etc.
The precharge controller 16 and the inverter controller 30 and the components thereof may be implemented as any suitable hardware, processor-executed software, processor-executed firmware, logic, and/or combinations thereof wherein the illustrated controllers 16 and 30 can be implemented using processor-executed software or firmware providing various control functions by which the inverter controller 30 receives feedback and/or input signals and/or values (e.g., setpoint(s)) and provides inverter switching control signals to provide AC output power to drive the load 6. Furthermore, the precharged controller 16 in certain embodiments operates according to DC bus voltage feedback (VDC) in order to perform the precharged and rectifier control functionality as set forth herein. In addition, the controllers 16 and 30 and the components thereof can be implemented in a single processor-based device, such as a microprocessor, microcontroller, FPGA, etc., or one or more of these can be separately implemented in unitary or distributed fashion by two or more processors.
As discussed further hereinafter, moreover, the system 2 includes a second capacitance C4 coupled between the first and second rectifier outputs 42 and 44, as well as a third capacitance C5 coupled between the first rectifier output 42 and the ground node 8, as well as a fourth capacitance C6 coupled between the second rectifier output 44 and the ground node. A switchable capacitor bank 20 is coupled with the AC input, and a switch 22 is provided for selectively coupling the input capacitor bank 20 with a ground or other constant voltage node 8, such as the grounded neutral of the external source 4 in the illustrated embodiment. In addition, the illustrated system 2 includes a DC bus capacitor circuit including DC bus common mode capacitances C2 and C3 connected in series between the inverter input nodes 46 and 48, with a center node joining C2 and C3 being selectively coupled to the ground node by a switch 26. The common mode capacitances C2 and C3 may be connected in the circuit by closing the switch 26 to provide a low impedance path for return of common mode currents to avoid having those currents return to the power source 4 for systems in which the neutral of the source 4 is grounded to the ground node 8 as shown in
The inventors have appreciated that opening the switches 22 and 26 for grounded source systems allows undesirable, mode currents to return to the power source neutral through the ground connection 8. However, other system configurations are possible, such as high resistance grounding (HRG) connections, floating system configurations, etc., in which the DC bus capacitors C2 and C3 are removed from the circuit by opening the switch 26. In this situation, particularly for low motor speeds, long cables 32 and relatively high inverter operating frequencies, the AC input line currents are typically low, and may not be enough to latch the upper rectifier SCRs in the on state. In this condition, moreover, if the common mode current returns back through the power source 4 or to the AC input lines through the AC input capacitors 20 with switch 22 closed, and the upper rectifier SCRs SCR1, SCR2 and SCR3 are not latched on, the common mode current returns through the precharge circuit diodes D1-D3 and conducts through the precharged resistance RPC, which can lead to overheating of the precharged resistance RPC absent opening of the switch 12.
In addition, since the intermediate DC bus circuit 24 includes the DC link choke LP, LN connected between the rectifier output nodes 42, 44 and the inverter input nodes 46, 48, without the capacitance C4, the voltage at the rectifier output can be significantly different than the DC bus voltage across C1 because common mode currents flow across the inductances LP, LN, and the rectifier output node voltages can deviate significantly from ground without the use of capacitances C5 and C6. For example, the nominal DC bus level across C1 for a three-phase 480 V input source 4 may be around 650 V, and the rectifier output voltage may spike to about 1300 V in certain conditions absent the use of the third capacitor C4. In certain embodiments, therefore, the third capacitor C4 dampens voltage spikes at the output of the rectifier 18, wherein C4 is about 0.1 μF in one non-limiting embodiment. Moreover, the common mode capacitors C5 and C6 in one embodiment can be relatively low capacitances, such as about 10 nF in one implementation, to limit the peak rectifier output voltages to ground 8.
In order to mitigate undesirable overheating of RPC during normal operation, therefore, the precharging system 10 provides a normally closed switching circuit 12 operated according to the control signal 14 from the precharge controller 16 in order to open the switch 12 when the DC bus voltage VDC exceeds a threshold, and concurrently the upper rectifier SCRs SCR1, SCR2 and SCR3 are allowed to operate by switching control signals 17 from the controller 16 to be selectively activated to begin normal rectifier operation. Furthermore, the use of a normally closed switch 12 advantageously maintains the precharging conduction path through RPC at power up before the precharge controller 16 is fully operational. In certain embodiments, moreover, the same signal 14 that gates the SCRs of the rectifier can be used to open the switch 12.
As discussed in the incorporated U.S. Pat. No. 8,154,895, the upper rectifier SCRs are individually actuated via the control signals 17 when the switching control signal 14 is active (e.g. HI in one example) and when the corresponding AC input phase voltage is the highest positive between the three input phase voltages during the positive portion of the pulse signal provided by the pulse generator 46. In this manner, the control signal 14 enables operation of one or more of the SCRs of the rectifier 18 and opens the switch 12 when activated. As shown in
The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon reading and understanding this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, systems, circuits, and the like), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component, such as hardware, processor-executed software, or combinations thereof, which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the illustrated implementations of the disclosure. In addition, although a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Also, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in the detailed description and/or in the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”. This description uses examples to disclose various embodiments and also to enable any person skilled in the art to practice the disclosed subject matter, including making and using any devices or systems and performing any incorporated methods. It will be evident that various modifications and changes may be made, and additional embodiments may be implemented, without departing from the broader scope of the present disclosure as set forth in the following claims, wherein the specification and drawings are to be regarded in an illustrative rather than restrictive sense.