BRIEF DESCRIPTION OF THE DRAWINGS
In the Figures, the left-most digit of a component reference number identifies the particular Figure in which the component first appears.
FIG. 1 illustrates an exemplary system for accelerated video encoding, according to one embodiment.
FIG. 2 shows an exemplary embodiment of a video encoding pipeline configuration, wherein some of the encoding processes are accelerated in hardware.
FIG. 3 shows an exemplary procedure for accelerated video encoding, according to one embodiment.
FIG. 4 in the Appendix shows an exemplary video encoder application to illustrate the manner in which video encoding acceleration application programming interfaces can be utilized, according to one embodiment.
FIG. 5 in the Appendix shows an exemplary video encoding pipeline configuration, wherein acceleration hardware accelerates motion estimation, transform, quantization, and the inverse process to produce encoded images, according to one embodiment.
FIG. 6 in the Appendix shows an exemplary video encoding pipeline configuration in which hardware accelerates only motion estimation, according to one embodiment.
FIG. 7 in the Appendix shows several exemplary motion estimation parameters, according to one embodiment.
FIG. 8 in the Appendix shows exemplary motion vector data stored in a Display 3-Dimensional (D3D) surface, according to one embodiment.
FIG. 9 in the Appendix shows an exemplary diagram indicating that width of a luma surface matches an original YCbCr image, according to one embodiment.
FIG. 10 in the Appendix shows an exemplary diagram indicating that the number of residue value per line of video is ½ width of the original video image, according to one embodiment.
FIG. 11 in the Appendix shows an exemplary diagram indicating that the width of the residue surface is ¼ the width of the original progressive frame, according to one embodiment.