Patent Grant
11822966
This application is a National Stage application under 35 U.S.C. § 371 of International Application No. PCT/JP2019/032770, having an International Filing Date of Aug. 22, 2019. The disclosure of the prior application is considered part of the disclosure of this application, and is incorporated in its entirety into this application.
The present invention relates to an accelerator control system and an accelerator control method.
There are an increasing number of cases where a part of processing of a software application (hereinafter referred to as APL) is offloaded to an accelerator such as a graphics processing unit (GPU) or a field programmable gate array (FPGA) to achieve a performance and power efficiency that cannot be achieved by software (CPU processing) alone.
A case of applying an accelerator as described above in a large-scale server cluster such as a data center constituting Network Functions Virtualization (NFV) or a Software Defined Network (SDN) is assumed (see NPL 1).
Offloading of a server load factor in the related art will be described.
The left diagram of
The arithmetic system 10A illustrated in the left diagram of
An arithmetic system 10B illustrated in the right diagram of
However, there is a concern in the technology of the related art that there is a possibility of a person who can operate a server (such as a system operator or a person making unauthorized access) unintentionally or maliciously rewriting the content of an accelerator, which may hinder proper management of the accelerator. There is a problem that the accelerator performs an unintended operation when functions of the accelerator are rewritten due to an operation error made by a system operator or a malicious user.
For example, as indicated by reference sign b in
In addition, a malicious user 22 may arbitrarily rewrite the FPGA function unit 41 of the accelerator board 40 as indicated by reference sign d in
The present invention has been made in view of this background, and an object of the present invention is to prevent an accelerator function from being rewritten and prevent an unintended operation.
To solve the above-described problems, the present invention is an accelerator control system that offloads application-specific processing of a general-purpose server to an accelerator function unit on an accelerator board, in which the general-purpose server includes an accelerator rewriting unit configured to rewrite an accelerator function of the accelerator function unit, a server-side digest information generating unit configured to binarize the accelerator function to generate first digest information of the accelerator function, and a server management unit configured to compare the first digest information created before the accelerator function is implemented on the accelerator function unit with second digest information notified from the accelerator board and determine whether the accelerator function is rewritten, and the accelerator board includes an accelerator-side digest information generating unit configured to generate the second digest information of the accelerator function written in the accelerator function unit, and an accelerator management unit configured to notify the general-purpose server serving as a rewriting source of the second digest information generated.
According to the present invention, it is possible to prevent an accelerator function from being rewritten and prevent an unintended operation.
Hereinafter, a network system and the like in a mode for implementing the present invention (hereinafter referred to as “the present embodiment”) will be described with reference to the diagrams.
Description of Principle
The accelerator control system 100 includes a general-purpose server 110 and an accelerator board 120 as illustrated in
In the accelerator control system 100, application-specific processing of the general-purpose server 110 is offloaded to the FPGA function unit 122 (an accelerator function unit) on the accelerator board 120.
General Purpose Server 110
The general-purpose server 110 is a computer apparatus (hardware) or software that functions to provide information and processing results in response to a request from a client (a system operator 20).
The general-purpose server 110 includes a server management unit 111 provided in one set with an FPGA management unit 121 (an accelerator management unit) of the accelerator board 120. The server management unit 111 creates and retains digest information 130 (described below in
Accelerator Board 120
The accelerator board 120 is equipped with an accelerator such as an FPGA that offloads a load-intensive processing to mitigate the load of the general-purpose server 110.
The accelerator board 120 includes the FPGA management unit 121 and an FPGA function unit 122 (an accelerator function unit).
The FPGA management unit 121 is provided in one set with the server management unit 111 of the general-purpose server 110. The FPGA management unit 121 creates the digest information 130 of the FPGA function unit 122 and periodically notifies the server management unit 111 of the general-purpose server 110 of the digest information.
The FPGA function unit 122 is an accelerator provided in the accelerator board 120, and any accelerator is applicable.
System Operator 20
The system operator 20 offloads an accelerator file 50 (see <function 1> of
In the configuration described above, the server management unit 111 of the general-purpose server 110 creates and retains digest information 130 of an accelerator function in accordance with the accelerator file 50 from the system operator 20 (see reference sign fin
The system operator 20 implements the accelerator function on the FPGA function unit 122 of the accelerator board 120 (see step S2). Here, the system operator 20 offloads the accelerator file 50 (see <function 1> of
The FPGA management unit 121 of the accelerator board 120 creates and retains digest information 130 of the accelerator function in accordance with the accelerator file 50 (see reference sign g in
The server management unit 111 of the general-purpose server 110 compares the previously created and retained digest information 130 with the digest information 130 notified by the FPGA management unit 121 of the accelerator board 120 to determine rewriting of the accelerator function (see step S5). When two pieces of the digest information 130 match, the server management unit 111 determines that the accelerator function has not been rewritten. When “implementation of the accelerator” of step S2 described above is performed without passing through “creation of digest information” in step S1 described above, two pieces of the digest information 130 do not match in “determination of rewriting of the accelerator function” in step S5 described above.
The server management unit 111 of the general-purpose server 110 determines that the acceleration function has been rewritten when two pieces of the digest information 130 do not match or the notification of the digest information 130 is stopped and instructs the FPGA management unit 121 of the accelerator board 120 to stop the accelerator function (see step S6).
The FPGA management unit 121 of the accelerator board 120 receives the instruction to stop the accelerator function from the server management unit 111 of the general-purpose server 110 and issues a command to stop the accelerator function of the FPGA function unit 122 (see step S7). The FPGA management unit 121 may stop the accelerator function until the function of the accelerator is normalized.
When a user has a malicious intention, the user may falsify the digest information 130 to make it look as if the acceleration function has not been rewritten.
The following is added to deal with the above case.
The server management unit 111 of the general-purpose server 110 uses a public key to decrypt the digest information 130. In addition, the server management unit 111 compares the previously created and retained digest information 130 with the digest information 130 notified by the FPGA management unit 121 of the accelerator board 120 to determine rewriting of the accelerator function (see step S5). When two pieces of the digest information 130 match, the server management unit 111 determines that the accelerator function has not been rewritten.
The present embodiment takes an FPGA as an example of an accelerator and the general-purpose server 110 equipped with the accelerator board 120 as an example.
Configuration of Accelerator Control System 100
The accelerator control system 100 illustrated in
The general-purpose server 110 includes the server management unit 111 and an FPGA rewriting unit 112 (an accelerator rewriting unit).
The server management unit 111 creates and retains digest information 130 of an accelerator function before the accelerator function is implemented on the FPGA function unit 122 of the accelerator board 120. The server management unit 111 compares the previously created digest information 130 with digest information 130 notified by the FPGA management unit 121 of the accelerator board 120 and determines that the accelerator function has not been rewritten when two pieces of the digest information 130 match. The server management unit 111 determines that the accelerator function is rewritten when two pieces of the digest information 130 do not match or the notification of the digest information 130 is stopped and requests reimplementation of the accelerator.
The FPGA rewriting unit 112 (the accelerator rewriting unit) rewrites the FPGA function to be offloaded to the FPGA function unit 122 of the accelerator board 120.
The accelerator board 120 includes the FPGA management unit 121 and the FPGA function unit 122.
The FPGA management unit 121 creates the digest information 130 of the FPGA function unit 122 and periodically notifies the server management unit 111 of the general-purpose server 110 of the digest information.
The FPGA function unit 122 is an accelerator provided in the accelerator board 120.
The accelerator control system 100 illustrated in
In addition, an accelerator control system 100A illustrated in
The general-purpose server 110A has the FPGA rewriting unit 112 illustrated in
The accelerator board 120A is provided with the FPGA management unit 121 illustrated in
The accelerator control system 100A illustrated in
Although the accelerator control system 100A illustrated in
The accelerator control system 100 illustrated in
Detailed Configuration of Accelerator Control System 100
General Purpose Server 110
The general-purpose server 110 includes the server management unit 111 and the FPGA rewriting unit 112 (an accelerator rewriting unit).
The server management unit 111 includes a server management control unit 1111, a digest information generation unit 1112 (a server-side digest information generation unit), a digest DB 1113, a key management unit 1114 (a public key management unit), and an FPGA communication unit 1115.
The FPGA rewriting unit 112 rewrites an FPGA of the FPGA function unit 122 (an accelerator function unit) (which has a restoration function in rewriting failure).
The server management control unit 1111 compares two pieces of the digest information 130 (see
When the digest information 130 created before the accelerator function is implemented on the FPGA function unit 122 (see the digest information 130A in
When the digest information 130 created before the accelerator function is implemented on the FPGA function unit 122 (see the digest information 130A in
The server management control unit 1111 decrypts, with a public key, the digest information 130 (see the digest information 130B in
The digest information generation unit 1112 binarizes the accelerator function to generate digest information of the accelerator function. Specifically, the digest information generation unit 1112 generates the digest information 130 in accordance with a binary file 140A (see
The digest DB 1113 retains an identifier of the binary file 140A and its digest information 130 for implementation on the FPGA.
The key management unit 1114 manages the public key of the FPGA management unit 121 to be used for communication.
The FPGA communication unit 1115 communicates with a server communication unit 1214 of the FPGA management unit 121.
Accelerator Board 120
The accelerator board 120 includes the FPGA management unit 121 and the FPGA function unit 122.
The FPGA management unit 121 includes an FPGA management control unit 1211, a digest information generation unit 1212 (an accelerator-side digest information generation unit), a key management unit 1213 (a private key management unit), and the server communication unit 1214. The FPGA function unit 122 is an FPGA body serving as a rewriting target.
The FPGA management control unit 1211 creates the digest information 130 of the FPGA function unit 122 on the accelerator board 120 and periodically notifies the server management control unit 1111 of the general-purpose server 110 serving as a rewriting source of the generated digest information 130 (see the digest information 130B in
The FPGA management control unit 1211 encrypts the generated digest information 130 with a private key that only the server management control unit 1111 knows and then notifies the server management control unit of the encrypted digest information.
The FPGA management control unit 1211 stores the function written in the FPGA function unit 122 and the server management unit 111 serving as the rewriting source and transmits the digest information 130 (see the digest information 130B in
The digest information generation unit 1212 generates the digest information 130 of the accelerator function written to the FPGA function unit 122.
The digest information generation unit 1212 has the same function as the digest information generation unit 1112 of the server management unit 111 of the general-purpose server 110, and binarizes the accelerator function to generate the digest information 130 of the accelerator function.
The key management unit 1213 manages a private key of the FPGA management unit 121 to be used for communication.
The server communication unit 1214 communicates with the FPGA communication unit 1115 of the server management unit 111 of the general-purpose server 110.
Digest Information 130
Next, the digest information 130 will be described.
The digest information 130 is generated by the digest information generation unit 1112 of the general-purpose server 110 (see
The same digest information 130 is generated on the general-purpose server 110 side and the accelerator board 120 side. Thus, the digest information generation unit 1112 of the general-purpose server 110 and the digest information generation unit 1212 of the accelerator board 120 use the same algorithm for generating digest information. In other words, the digest information generation unit 1112 of the general-purpose server 110 and the digest information generation unit 1212 of the accelerator board 120 adopt the same configuration.
After converting <function 1> to the binary file 140A, the digest information generation unit 1112 calculates the hash value using a hash function algorithm such as the message digest algorithm 5 (MD5) or Secure Hash Algorithm (SHA) (see step S8). This hash value is set as the digest information 130. The hash value (bit sequence) is, for example, 8da75b24 0f3c196e . . . .
As described above, both the general-purpose server 110 and the accelerator board 120 need to use the same hash algorithm.
As illustrated in
In addition, the digest information 130B illustrated in
The server management unit 111 of the general-purpose server 110 determines match/mismatch in accordance with the digest information (hash values) generated in each of the general-purpose server 110 and the accelerator board 120. In the example of
Hereinafter, an accelerator control method of the accelerator control system 100 configured as described above will be described.
Flowchart
The flow starts with a rewriting command issued from a user terminal to the FPGA rewriting unit 112 of the general-purpose server 110 (see
In step S11, the FPGA rewriting unit 112 (see
In step S12, the FPGA rewriting unit 112 of the general-purpose server 110 requests FPGA rewriting from the digest information generation unit 1112 of the server management unit 111.
In step S13, the digest information generation unit 1112 (see
In step S14, the server management control unit 1111 (see
In step S15, the server management control unit 1111 of the server management unit 111 rewrites the digest information 130 stored in the digest DB 1113 with the identifier of the binary file 140A and the new digest information 130.
In step S16, the server management control unit 1111 of the server management unit 111 performs FPGA rewriting using the FPGA rewriting unit 112 (see
Here, basic control is that FPGA rewriting is permitted when the digest information 130 has been updated. In addition, permitting rewriting may be controlled in accordance with the history, units of users, units of files, timings, and the like.
At step S17, after the FPGA rewriting is performed, the FPGA function unit 122 of the accelerator board 120 notifies the FPGA rewriting unit 112 of the general-purpose server 110 of the fact that the FPGA rewriting has been completed and notifies the digest information generation unit 1112 of the FPGA management unit 121 of the fact that the FPGA rewriting has been completed with the binary file 140A.
In step S18, the digest information generation unit 1112 of the FPGA management unit 121 of the accelerator board 120 generates the digest information 130 in accordance with the received binary file 140A. Then, the FPGA management unit 121 sends the identifier of the binary file 140A and the generated digest information 130 to the FPGA management control unit 1211.
In step S19, the FPGA management control unit 1211 of the accelerator board 120 sends the identifier of the binary file 140A and its digest information 130 to the server management control unit 1111 by using the FPGA communication unit 1115. Specifically, the FPGA management control unit 1211 stores the function written on the FPGA function (the identifier of the binary file 140A) and requests communication with the server management unit 111 from the server communication unit 1214. The server communication unit 1214 requests a private key necessary for cryptographic communication from the key management unit 1114 and sends the identifier of the encrypted binary file 140A and its digest information 130 to the FPGA communication unit 1115. The FPGA communication unit 1115 receives the identifier of the encrypted binary file 140A and its digest information 130 and requests a public key from the key management unit 1114. After decryption, the identifier of the binary file 140A and its digest information 130 are sent to the server management control unit 1111.
As indicated by reference sign j in
In step S20, the server management control unit 1111 of the server management unit 111 determines whether two pieces of the digest information 130 match. Specifically, the server management control unit 1111 requests the existing digest information 130 for the identifier of the binary file 140A from the digest DB 1113 and compares the digest information 130 rewritten in step S15 described above with the digest information 130 received in step S19 described above. When two pieces of the digest information 130 do not match, the server management control unit 1111 determines that unexpected rewriting has occurred and returns to step S12 to rewrite the FPGA to the original content in accordance with the backup of the FPGA function unit 122. When two pieces of the digest information 130 match, the processing proceeds to step S21.
In step S21, the server management control unit 1111 of the server management unit 111 notifies the FPGA rewriting unit 112 of the comparison result of two pieces of the digest information 130 through the digest information generation unit 1112. When the notification of the successful rewriting is received, the FPGA rewriting unit 112 deletes the backup of the FPGA function unit 122 and terminates the processing of the flow.
Control Sequence
The FPGA rewriting unit 112 (see
The binary file DB 140 transmits the binary file 140A to the FPGA rewriting unit 112 (see step S102).
The FPGA rewriting unit 112 of the general-purpose server 110 requests FPGA rewriting (an FPGA rewriting request using the binary file 140A) from the digest information generation unit 1112 of the server management unit 111 (see step S103).
The digest information generation unit 1112 of the server management unit 111 transmits the digest information 130 to the server management control unit 1111 (see step S104).
The server management control unit 1111 requests reading of the digest information from the digest DB 1113 (see step S105).
The digest DB 1113 transmits the read digest information 130 to the server management control unit 1111 (see step S106).
The server management control unit 1111 requests storage of the digest information in the digest DB 1113 (see step S107).
The digest DB 1113 notifies the server management control unit 1111 of the storage of the digest information (see step S108).
The server management control unit 1111 receives the notification on the storage of the digest information from the digest DB 1113 and issues an FPGA rewriting permission to the digest information generation unit 1112 (see step S109).
The digest information generation unit 1112 of the server management unit 111 receives the FPGA rewriting permission and issues the FPGA rewriting permission to the FPGA rewriting unit 112 of the general-purpose server 110 (see step S110).
The FPGA rewriting unit 112 of the general-purpose server 110 requests FPGA rewriting from the FPGA function unit 122 (see
On the other hand, the FPGA function unit 122 of the accelerator board 120 notifies the digest information generation unit 1212 of the FPGA management unit 121 of FPGA rewriting (notification on FPGA rewriting using the binary file 140A) (see step S113).
The digest information generation unit 1212 of the FPGA management unit 121 sends the digest information 130 to the FPGA management control unit 1211 (see step S114).
The FPGA management control unit 1211 of the FPGA management unit 121 makes a request for communication with the server management unit 111 to the server communication unit 1214 (see step S115).
The server communication unit 1214 makes a request for a key to the key management unit 1213 (see step S116), and the key management unit 1213 sends a private key to the server communication unit 1214 (see step S117).
The server communication unit 1214 performs communication with the server management unit 111 to the FPGA communication unit 1115 of the server management unit 111 (see step S118).
The FPGA communication unit 1115 of the server management unit 111 makes a request for a key to the key management unit 1114 (see step S119), and the key management unit 1114 sends a public key to the FPGA communication unit 1115 (see step S120).
The FPGA communication unit 1115 of the server management unit 111 notifies the server management control unit 1111 of the communication (see step S121).
The server management control unit 1111 issues a request for reading the digest information from the digest DB 1113 (see step S122), and the digest DB 1113 sends the digest information 130 to the server management control unit 1111 (see step S123).
The server management control unit 1111 sends the comparison result of the digest information to the digest information generation unit 1112 (see step S124).
The digest information generation unit 1112 sends the received comparison result of the digest information to the FPGA rewriting unit 112 of the general-purpose server 110 (see step S125).
Further, although the FPGA function unit 122 of the accelerator board 120 actively performs the notification of the FPGA rewriting in step S113 described above, the digest information generation unit 1112 of the server management unit 111 may perform polling for the notification. The control sequence of the accelerator control processing is terminated with the above operation.
Hardware Configuration
The general-purpose server 110 of the accelerator control system 100 according to the present embodiment is achieved, for example, by a computer 900 configured as illustrated in
Hereinafter, the general-purpose server 110 will be described as an example.
The computer 900 includes a CPU 910, a RAM 920, a ROM 930 storing a basic input/output system (BIS), or the like, an HDD 940, a communication interface (I/F: Interface) 950, an input/output interface (I/F) 960, and a media interface (I/F) 970.
The CPU 910 operates in accordance with programs stored in the ROM 930 or the HDD 940 and performs control of each unit. The ROM 930 stores a boot program executed by the CPU 910 when the computer 900 is activated, a program dependent on the hardware of the computer 900, and the like.
The HDD 940 stores programs executed by the CPU 910, data used by the programs, and the like. The HDD 940 may store, for example, the digest DB 1113 and the binary file DB 140 (see
The CPU 910 controls, via the input/output interface 960, an output device such as a display and a printer, and an input device such as a keyboard and a mouse. The CPU 910 acquires data from the input device via the input/output interface 960. The CPU 910 also outputs the generated data to the output device via the input/output interface 960.
The media interface 970 reads a program or data stored in a recording medium 980 and provides the read program or data to the CPU 910 via the RAM 920. The CPU 910 loads such a program from the recording medium 980 onto the RAM 920 via the media interface 970 to execute the loaded program. The recording medium 980 is, for example, an optical recording medium such as a digital versatile disc (DVD) and a phase change rewritable disk (PD), a magneto-optical recording medium such as a magneto optical disk (MO), a tape medium, a magnetic recording medium, a semiconductor memory, or the like.
For example, when the computer 900 functions as the general-purpose server 110 according to the present embodiment, the CPU 910 of the computer 900 achieves the functions of the respective units of the general-purpose server 110 by executing the programs loaded on the RAM 920. In addition, the HDD 940 stores data of the inside of the respective units of the general-purpose server 110. Although the CPU 910 of the computer 900 reads these programs from the recording medium 980 and executes them, these programs may be acquired from another device via the communication network 80 as another example.
In addition, the accelerator board 120 may be installed in a different general-purpose server 110 or may be in the same general-purpose server 110. Here, encryption is helpful when the server management unit 111 and the FPGA management unit 121 illustrated in
Advantages
As described above, in the accelerator control system 100 in which application-specific processing of the general-purpose server 110 is offloaded to the accelerator function unit (the FPGA function unit 122) of the accelerator board 120, the general-purpose server 110 includes an accelerator rewriting unit (the FPGA rewriting unit 112) that rewrites an accelerator function of the accelerator function unit, the digest information generation unit 1112 that binarizes the accelerator function to generate digest information 130 of the accelerator function, and a server management control unit 1111 that compares the digest information 130 created before the accelerator function is implemented on the accelerator function unit with digest information 130 notified from the accelerator board 120 and determines whether the accelerator function has been rewritten, and the accelerator board 120 includes the accelerator function unit (the FPGA function unit 122), the digest information generation unit 1212 that generates the digest information 130 of the accelerator function written in the accelerator function unit, and the accelerator management control unit (the FPGA management control unit 1211) that notifies the general-purpose server 110 serving as a rewriting source of the generated digest information 130.
With this configuration, rewriting of the accelerator function caused by an operation mistake made by a system operator or rewriting of the accelerator function by a malicious user can be prevented, and an unintended operation can be prevented in advance. In particular, there are an increasing number of cases in which a plurality of users uses an accelerator, such as a case in which a plurality of functions used by a plurality of users coexists on the same server by virtualization. In such a case, the accelerator control system 100 can achieve proper management of the functions implemented on the accelerator board, enabling the accelerator to be effectively utilized in a cloud environment in which a plurality of users is intermixed.
When the digest information 130 created before the accelerator function is implemented does not match the digest information 130 notified by the accelerator board 120, the server management control unit 1111 of the general-purpose server 110 of the accelerator control system 100 determines that the accelerator function has been rewritten and requests the accelerator management control unit (the FPGA management control unit 1211) to reimplement the accelerator function.
With this configuration, if it is determined that the accelerator function has been rewritten, the server management control unit 1111 of the server management unit 111 of the general-purpose server 110 requests the accelerator management control unit (the FPGA management control unit 1211) to reimplement the accelerator function, thereby preventing an unintended operation from being started.
When the digest information 130 created before the accelerator function is implemented on the accelerator function unit (the FPGA function unit 122) does not match the digest information 130 notified by the accelerator board 120, the server management control unit 1111 of the server management unit 111 of the general-purpose server 110 of the accelerator control system 100 may instruct the FPGA management control unit 1211 to stop the accelerator function unit until the accelerator function is normalized.
With this configuration, if it is determined that the accelerator function has been rewritten, the server management control unit 1111 of the server management unit 111 of the general-purpose server 110 can prevent an unintended operation from being performed until the accelerator function is normalized.
The accelerator board 120 of the accelerator control system 100 includes the private key management unit (the key management unit 1213) that manages a private key of the FPGA management control unit 1211 to be used for communication, the accelerator management control unit (the FPGA management control unit 1211) notifies the general-purpose server 110 of the generated digest information 130 by encrypting the generated digest information 130 with a private key that only the server management unit 111 knows, the general-purpose server 110 of the accelerator control system 100 includes the public key management unit (the key management unit 1114) that manages a public key of the server management control unit 1111 to be used for communication, and the public key management unit decrypts, with the public key, the digest information 130 encrypted and notified by the accelerator board 120.
With this configuration, rewriting of an accelerator function by a malicious user can be prevented even in an attack of the malicious user falsifying digest information to make it be believed that the acceleration function has not been rewritten.
Others
Among processing operations described for the principle and described in the embodiments, all or some of the processing operations described as being automatically performed can be manually performed, or all or some of the processing operations described as being manually performed can be automatically performed by using a well-known method. In addition, the processing procedures, the control procedures, the specific names, and information including various types of data, and various parameters described in the aforementioned document and diagrams can be modified as desired unless otherwise specified.
In addition, constituent components of the devices illustrated in the diagrams are functionally conceptual and are not necessarily physically configured as illustrated in the diagrams. That is, the specific aspects of distribution and integration of the devices are not limited to those illustrated in the diagrams, and all or some of the devices may be distributed or integrated functionally or physically in desired units depending on various kinds of loads, states of use, and the like.
In addition, some or all of the configurations, the functions, the processing units, the processing mechanisms, and the like may be achieved in hardware by being designed, for example, in an integrated circuit. In addition, each of the configurations, the functions, and the like described above may be achieved in software for a processor to interpret and execute a program that implements the functions. Information of programs, tables, files, and the like, which are for achieving the functions can be retained in a recording device such as a memory, a hard disk, and a solid-state drive (SSD), or a recording medium such as an integrated circuit (IC) card, a secure digital (SD) card, and an optical disc. In addition, in the present specification, processing steps for describing the time-series processing include not only processing performed in a time-series manner in described order not also parallel or individually performed processing (for example, parallel processing or object processing), rather than processing necessarily performed in a time-series manner.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2019/032770 | 8/22/2019 | WO |
| Publishing Document | Publishing Date | Country | Kind |
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| WO2021/033306 | 2/25/2021 | WO | A |
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| Number | Date | Country | |
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| 20220283868 A1 | Sep 2022 | US |
