Claims
- 1. An accelerator for use in mounting and interfacing a second CPU which functionally replaces a first CPU on a motherboard, said first CPU intended to be driven by a first clock signal having a first period and a first frequency, said accelerator comprising:
- mounting means for mounting said second CPU on said motherboard;
- clock signal output means for generating a second clock signal from said first clock signal, said clock signal output means being operative to generate a plurality of delayed signals that take the form of a series of consecutively delayed waveform copies of said first clock signal wherein each copy is delayed by a corresponding time period that is less than or equal to one-half of said first period, said clock signal output means being further operative to combine said plurality of delayed signals to generate said second clock signal, wherein the second clock signal has a second frequency that is a non-integral multiple of said first frequency, said clock signal output means also being operative to output said second clock signal to said second CPU; and
- timing signal generating means for generating a timing signal for access of said second CPU in response to an address control signal generated by said second CPU and a synchronous combination of said first clock signal and said second clock signal,
- whereby said first clock signal and said second clock signal will automatically synchronize at said synchronous combination without further adjustment.
- 2. An accelerator in accordance with claim 1, wherein said second frequency is 1.5 times said first frequency.
- 3. An accelerator in accordance with claim 1, wherein said second CPU comprises a double-speed CPU having an internal operation clock running at a frequency 2 times said second frequency.
- 4. An accelerator in accordance with claim 1, wherein said mounting means is arranged for converting a pin arrangement of said second CPU to a pin arrangement of a co-processor of said first CPU, whereby said second CPU may be mounted on said accelerator and said accelerator may be inserted into a co-processor socket present on said motherboard which is arranged to accept said co-processor.
- 5. An accelerator in accordance with claim 1, wherein said mounting means is arranged for converting a pin arrangement of said second CPU to a pin arrangement of said first CPU, whereby said second CPU may be mounted on said accelerator and said accelerator may be inserted into a first CPU socket present on said mother board which is arranged to accept said first CPU.
- 6. An accelerator in accordance with claim 1 further comprising:
- data reading and writing means for reading and writing data while synchronizing with said second clock signal, said data reading and writing means reading and writing data in a read/write cycle based on said second clock signal after read/write based on said first clock signal becomes possible.
- 7. An accelerator for use in mounting and interfacing a second CPU which functionally replaces a first CPU on a mother board, said accelerator comprising:
- mounting means for mounting said second CPU on said motherboard;
- clock signal output means for generating a second clock signal from a first clock signal intended for said first CPU, said first clock signal having a first frequency, said second clock signal having a second frequency being a non-integral multiple of said first frequency, wherein said first clock signal and said second clock signal have a finite number of combinations being equal to a lowest common multiple of said first frequency and said second frequency; and
- timing signal generating means for generating a timing signal for said second CPU to read a memory in response to an address control signal generated by said second CPU and a present combination of said first clock signal and said second clock signal, said timing signal being generated as a function of the present combination of said first clock signal and said second clock signal such that the time necessary for reading said memory by said second CPU is minimized.
- 8. An accelerator in accordance with claim 7, wherein said second frequency is 1.5 times said first frequency and thus said lowest common multiple of said first frequency and said second frequency is 3.
- 9. An accelerator in accordance with claim 7, wherein said second CPU comprises a double-speed CPU having an internal operation clock running at a frequency 2 times said second frequency.
- 10. An accelerator in accordance with claim 7, wherein said mounting means is arranged for converting a pin arrangement of said second CPU to a pin arrangement of a co-processor of said first CPU, whereby said second CPU may be mounted on said accelerator and said accelerator may be inserted into a co-processor socket present on said motherboard which is arranged to accept said co-processor.
- 11. An accelerator in accordance with claim 7, wherein said mounting means is arranged for converting a pin arrangement of said second CPU to a pin arrangement of said first CPU, whereby said second CPU may be mounted on said accelerator and said accelerator may be inserted into a first CPU socket present on said mother board which is arranged to accept said first CPU.
- 12. An accelerator in accordance with claim 7, wherein said memory is selected from the group including read only memory (ROM) and random access memory (RAM).
- 13. An accelerator in accordance with claim 7 further comprising:
- data reading and writing means for reading and writing data while synchronizing with said second clock signal, said data reading and writing means reading and writing data in a read/write cycle based on said second signal after read/write based on said first clock signal becomes possible.
Parent Case Info
This is a continuation of application Ser. No. 08/284,201 filed Aug. 2, 1994, now abandoned.
US Referenced Citations (8)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0142440 |
May 1985 |
EPX |
Continuations (1)
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Number |
Date |
Country |
Parent |
284201 |
Aug 1994 |
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