The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
In the past, the electronics industry utilized various methods and structures to build voltage reference circuits. The voltage reference circuits generally were used to supply a stable reference voltage for use by other circuits such as a comparator circuit. One commonly used design technique to form the voltage reference circuits used a bandgap reference as a portion of the voltage reference circuit. One design parameter for the prior voltage reference circuits was to reduce variations in the reference voltage that resulted from variations in the value of the input voltage that was used to operate the voltage reference circuit. This is sometimes referred to as power supply rejection. The ratio of the change of the input voltage to the change on reference voltage was referred to as the power supply rejection ratio (PSSR). One example of a prior voltage reference circuit was disclosed in U.S. Pat. No. 6,972,549 that issued to Brass et al. on Dec. 6, 2005. However, such prior voltage reference circuits did not provide sufficient power supply rejection.
Accordingly, it is desirable to have a voltage reference circuit that has improved power supply rejection.
For simplicity and clarity of the illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-Channel devices, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action.
Amplifier 36 receives the value of the collector voltage of transistors 17 and 28 that are formed at respective nodes 14 and 15. The control loop of amplifier 36 and transistor 33 are configured to regulate the value of the voltage at nodes 14 and 15 to be substantially equal. In the preferred embodiment, resistors 27 and 29 have equal values so that the value of respective currents 26 and 30 through resistors 27 and 29 are substantially equal. Those skilled in the art will appreciate that the value of resistors 27 and 29 are also chosen to provide the desired open loop gain for amplifier 36 and transistor 33. Thus, the value of currents 26 and 30 through respective transistors 28 and 17 are also equal.
Transistors 17 and 28 are formed to have active areas that have different sizes so that the Vbe of transistors 17 and 28 are not the same value. In the preferred embodiment, transistor 17 has an active area that is about eight (8) times larger than the active area of transistor 28 so that in operation the value of the Vbe of transistor 17 is approximately ten percent (10%) less than the value of the Vbe of transistor 28. Also, since transistors 17 and 28 have substantially equal current values but different active area sizes the Vbe of transistor 17 has to be less than the Vbe of transistor 28. Current source 32 causes the sum of currents 26 and 30 to be substantially constant. Resistor 18 is connected between the base of transistor 28 and the base of transistor 17 to receive a voltage that is approximately the difference between the Vbe of transistor 28 and the Vbe of transistor 17. This voltage difference is often referred to as the delta Vbe of the bandgap reference circuit formed by transistors 17 and 28. Thus, a voltage 21 that is developed across resistor 18 is equal to the delta Vbe. The delta Vbe received by resistor 18 causes a current 22 to flow through resistor 18. Thus, the value of current 22 is representative of the delta Vbe. The current mirror configuration between transistors 16 and 17 set the polarity and the value of the voltage at a node 31.
Current 22 flows through transistor 16, resistor 24, and resistors 25 and 18. Consequently, the value of the reference voltage formed on output 13 is substantially equal to:
where;
Configuring amplifier 36 to receive the collector voltage of transistors 17 and 28 that form the delta Vbe minimizes the variations of delta Vbe that result from variations of the input signals to amplifier 36 as the value of the input voltage on input terminal 11 varies. This minimizes variations in the output voltage as the input voltage varies. If the input voltage changes, any changes in the value of the input signals received by amplifier 36 has little effect on the delta Vbe value. Additionally, connecting the inputs of amplifier 36 to the collectors of transistors 17 and 28 improves the accuracy of the reference voltage formed on output 13. For example, if amplifier 36 has some input offset, the offset is reflected on the collectors of transistors 17 and 28 but has very little effect on the value of the delta Vbe formed across resistor 21. It is believed that this configuration improves the accuracy of the value of the reference voltage by two to three (2-3) times over the prior art.
The parasitic base-collector junction capacitance of transistor 39 forms a zero in the PSRR transfer function that can cause high variations in the output voltage resulting from high frequency changes in the input voltage received on input 11. The zero is related to the impedance seen by the collector of transistor 39 when output 41 of differential amplifier 36 and inputs 38 and 40 are grounded which is given by:
Z39=2*Ri47*gm47*Ro47.
where;
The frequency of the zero is given by:
Fz=½π*Z39*Ccb
Where;
Capacitor 56 is chosen to form a pole in the PSRR transfer function that cancels the effect of the zero formed by the parasitic base-collector junction capacitance of transistor 39 and the impedance Z39. The pole is related to the impedance seen by the collector of transistor 37 when power supply 11 and inputs 38 and 40 of differential amplifier are grounded. The impedance is given by:
P37=Ri47*gm47*Ro47
where;
Where;
As shown by the above equations, the value of capacitor 56 is chosen to as close a possible to twice the value of the parasitic collector-base capacitance of transistor 39. Capacitor 56 may also be formed as a junction capacitor so that the capacitances track over temperature and process variations. Resistor 57 is optional and may be omitted. Resistor 57 may be used to improve the PSRR for at or above about one hundred kilo-hertz (100 KHz). If resistor 57 is included, the value of resistor 57 is chosen to about 200 KOhm. The signal rejection circuit of capacitor 56 and an optional resistor 57 improves the PSRR by a factor of about one hundred to one thousand (100-1000) for frequencies between about one hundred Hertz to about one hundred Kilo-Hertz (100 Hz-100 KHz). In one example embodiment, the PSRR was improved by about forty decibels (40 db).
Capacitor 55 is used to form a pole in the open loop gain transfer function for the reference voltage on output 13. Capacitor 55 does not appear in the transfer function for the PSRR because capacitor 55 does not affect the collector of either of transistors 37 or 39. Capacitor 54 functions as an output filter that improves the PSRR at frequencies greater than about one hundred Kilo-Hertz (100 KHz).
The value of the current supplied by transistor 33 to a load (not shown) on output 13 depends on the size of transistor 33 and the value of the input voltage on input terminal 11. The load connected to output 13 may be a passive load or an active load such as a transistor that is a portion of another electrical circuit. If transistor 33 is large, transistor 33 can provide a large current at low values of the input voltage. In one example embodiment, transistor 33 could supply up to seven hundred milli-amperes (700 ma.) at input voltage values as low as about 2.0 volts.
In order to facilitate this functionality for circuit 10, a collector of transistor 17 is commonly connected to node 15 and a first terminal of resistor 29 which has a second terminal connected to output 13. An emitter of transistor 17 is commonly connected to a first terminal of current source 32 and an emitter of transistor 28. A collector of transistor 28 is commonly connected to node 14 and a first terminal of resistor 27 which has a second terminal connected to output 13. A base of transistor 17 is commonly connected to a base and a collector of transistor 16. An emitter of transistor 16 is connected to a first terminal of resistor 24 which has a second terminal connected to return terminal 12. A second terminal of current source 32 is connected to return terminal 12. The collector of transistor 16 is connected to node 19 and to a first terminal of resistor 18. A second terminal of resistor 18 is commonly connected to a node 20, the base of transistor 28, and a first terminal of resistor 25. Resistor 25 has a second terminal connected to output 13. Input 38 of amplifier 36 is connected to node 14 and input 40 of amplifier 36 is connected to node 15. Output 41 of amplifier 36 is connected to a gate of transistor 33. A base of transistor 39 is connected to input 40 and to a first terminal of capacitor 55, and an emitter is connected to a first terminal of current source 42. A second terminal of capacitor 55 is connected to output 41. A second terminal of source 42 is connected to return terminal 12. A collector and a base of a transistor 43 are connected to a collector of transistor 39, and an emitter is connected to input terminal 11. A base of transistor 37 is connected to input 38, and an emitter is connected to the first terminal of current source 42. A base of a transistor 44 is connected to the base of transistor 43, a collector is connected to the collector of transistor 37, and an emitter is connected to input terminal 11. A base of a transistor 47 is connected to the collector of transistor 44, an emitter is connected to input terminal 11, and a collector is connected to output 41 and a first terminal of a resistor 46. A second terminal of resistor 46 is connected to return terminal 12. A source of transistor 33 is connected to output 13 and a drain is connected to input terminal 11. A first terminal of resistor 57 is connected to output 41 and a second terminal is connected to a first terminal of capacitor 56. A second terminal of capacitor 56 is connected to the collector of transistor 37.
In view of all of the above, it is evident that a novel device and method is disclosed. Included, among other features, is using a pair of differentially coupled transistors to form a delta Vbe generation circuit. Using the differentially coupled transistors improves the power supply rejection of the voltage reference circuit. Using capacitor 56 improves the PSRR of the voltage reference circuit.
While the subject matter of the invention is described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. For example, current sources 32 and 42 may be each be replaced by a resistor. Additionally, resistors 27 and 29 may be replaced by current sources. Additionally, transistors 37 and 39 may be MOS transistors and amplifier 36 may be an MOS or CMOS amplifier instead of a bipolar amplifier. Additionally, the word “connected” is used throughout for clarity of the description, however, it is intended to have the same meaning as the word “coupled”. Accordingly, “connected” should be interpreted as including either a direct connection or an indirect connection.
The present application is a continuation-in-part of prior U.S. application Ser. No. 11/613,589, filed on 20 Dec. 2006 having a common inventor and common assignee, which is hereby incorporated by reference, and priority thereto for common subject matter is hereby claimed.
Number | Name | Date | Kind |
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6060874 | Doorenbos | May 2000 | A |
6400213 | Shih et al. | Jun 2002 | B2 |
6946825 | Tesi | Sep 2005 | B2 |
6972549 | Brass et al. | Dec 2005 | B2 |
Number | Date | Country | |
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20080150511 A1 | Jun 2008 | US |
Number | Date | Country | |
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Parent | 11613589 | Dec 2006 | US |
Child | 11688136 | US |