The present invention relates to AC/DC converters and the processes for making the same.
A conventional high voltage AC/DC converter using BIPOLAR CMOS DMOS (BCD) technology typically requires at least 18˜20 lithographic masks to manufacture and generally must withstand voltage higher than 450 V. As known in the art, more lithographic masks and associating processes significantly increase production costs of a chip. Using more lithographical processes also mean that the structure tends to be more complicated and therefore more error-prone. Therefore, what is needed in the art is a novel method of manufacturing high voltage AC/DC converter using as few lithographic masks as possible.
Furthermore, in a conventional design of the integrated AC/DC converter, low-voltage PWM-controller and external components such as start-up circuitries and output MOSFET, etc are typically included. Some other conventional designs of the AC/DC converters may include integrating a high-voltage input MOSFET component into the same chip with the PWM-controller. However, the size of the conventional integrated AC/DC converter is still relatively large. Integrating these many different components in a single chip will require complicated process and results in a manufacturing cost increase. Therefore, what is needed in the art is an integrated AC/DC converter with more efficient components and simplified circuits so as to reduce the product size and lower manufacturing costs.
Additionally, when starting up a conventional AC/DC converter device, an overcharge voltage is generally undesirable.
It is an object of the present invention to provide a method of manufacturing a semiconductor structure. The method includes providing a substrate; forming an oxide layer on a top surface of the substrate; applying a photo-resist layer on the oxide layer to define a well region; performing an ion-implantation in the well region using a dopant; and driving in atoms of the dopant to a depth in the well region through a thermal treatment, wherein the driving in process provides a concentration profile of the dopant in the well region such that the semiconductor structure has a high breakdown voltage.
It is another object of the present invention to provide a method of manufacturing a semiconductor structure. The method includes providing a substrate having a first section and a second section; forming a first oxide layer on a top surface of the substrate; applying a first photo-resist layer on the first oxide layer to define a first well region; performing a first ion-implantation in the first well region using a first dopant; driving in atoms of the first dopant to a first depth in the first well region through a thermal treatment; stripping the first oxide layer, forming a second oxide layer on the top surface of the substrate; applying a second photo-resist layer on the second oxide layer to define a second well region; performing a second ion-implantation in the second well region using a second dopant; driving in atoms of the second dopant to a second depth in said second well region through the thermal treatment, wherein the thermal treatment is at least 6,000 degree-C.·hour, the first depth is greater than 5.5 micron, and the second depth is greater than 3 micron.
It is yet another object of the present invention to provide an integrated circuit manufactured in the steps of the method as above. The integrated circuit includes: a single start-up and supply voltage controller for integrating a start-up source and a supply voltage; a first transistor electrically connected to the single start-up and supply voltage controller for converting high input voltage to internal supply voltage of the single start-up and supply voltage controller, wherein the first transistor is a DMOS transistor.
Other objects of the present invention can be readily ascertained by one of ordinary skilled in the arts upon review of the detailed descriptions of the preferred embodiments.
Reference will now be made in detail to the embodiments of the present invention. Examples of embodiments are illustrated in the accompanying drawings, wherein like reference numbers refer to like elements throughout the specification.
In one preferred embodiment of the present invention, the AC/DC converter is a high voltage AC/DC converter that may be in as few as 11 lithographic masks. According to one preferred embodiment of the present invention, high voltage NLDMOS and HVNMOS structures are manufactured. However, it is to be noted that this manufacturing process can also be used to produce other structures such as low voltage CMOS transistors, bipolar transistors and passive components.
In accordance with the present invention, the formation of N-Wells may be achieved by first performing an N-well oxidation to form a thin oxide layer at the top surface of the substrate 102. Then, an application of a photo-resist layer and lithographical procedure may be followed to define the positions where the N-wells are to be formed. Next, N-well implantation may be carried out, for example, using phosphorus as a dopant with a proper concentration and energy. After the implantation, plasma chemical treatment and photo-resist stripping may then be performed respectively, and the photo-resist layer may be removed from the surface of the substrate. Subsequently, the dopant phosphorus atoms may be driven in to a preferential depth through thermal treatment under atmosphere. Given that the depth of the N-well junction will increase as the applied thermal energy increases, the total thermal energy applied during the thermal treatment may be, for example, at least 6,000 degree-C.·hour.
In one preferred embodiment of the present invention, the N-well drive-in procedure provides a concentration profile of the dopant in the N-well such that the final MOS structure may have desirable high breakdown voltage characteristics. For example, a desirable high breakdown voltage may be 700V in operation. The junction depth d1 of the N-wells 112, 121, 122 in
Turning now to
In one preferred embodiment of the present invention, the P-well drive-in procedure provides a concentration profile of the boron atoms in the P-well such that the final MOS structure may have desirable high breakdown voltage characteristics. For example, a desirable high breakdown voltage may be 700V in operation. The depth d2 of the P-wells 123, 125 in
According to the present invention, P-fields within the P-well region may then be formed so as to increase the parasitic threshold voltage of the final device. To form the P-fields, a photo-resist layer with a predetermined pattern may be first formed through a conventional lithography process, in which the predetermined pattern exposes only the areas where the P-fields are to be formed. Afterwards, a P-field implantation may be carried out using, for example, boron as an implant. The photo-resist layer may then be stripped off, followed by a P-field drive-in so that the boron ions may reach a deeper depth in the substrate. As shown in
Turning now to
According to the present invention, the GATE may then be formed. A layer of poly-silicon may be deposited first on the structure shown in
As shown in
Turning now to
According to the present invention, contacts may then be formed in order to form the vias that may be filled with conductive materials later so as to provide electrical connection between the NLDMOS/HVNMOS and external circuitry. Referring to
According to the present invention, metallization in the contact vias 142 as well as on top of the CVD film 140 may be formed so that proper electrical connection may be made to these MOS devices. The material for metallization is not limited, as long as the material can sustain the conventional manufacturing process while achieving desirable electrical and physical properties.
In accordance with one embodiment, metallization may be carried out first by metal sputtering until a metal layer (not shown) may be formed on the CVD film 140. A lithography process may then be performed on the metal layer so as to define appropriate metal line patterns. As can be seen in
According to the present invention, one additional step may be the addition of a PAD layer. A passivated layer 150 may first be formed on the top surface of the structure shown in
In addition to the novel NLDMOS/HVNMOS structure as well as the manufacturing process for making the same, the present application also provides a novel IC design regarding the start-up and internal voltage regulation block for an AC/DC converter. The novel AC/DC converter has a smaller PCB size, resulting in smaller product size and lower cost.
In the novel design, the input high-voltage MOSFET is replaced by a more efficient DMOS, which is the same as the output DMOS transistor M2. This is desirable since a DMOS transistor is more effective as compared to the conventional MOSFET. Because of this novel design, the overall chip size can be further reduced. As a result, not only will the cost of the chip be reduced, but the product will also be more competitive because broader applications can be achieved with smaller IC chip size. For illustration purposes, block 310 in
In another embodiment of the present invention, the output DMOS M2 in
In yet another embodiment of the present invention, an AC/DC converter that enables a soft-start function is disclosed. Referring to
The advantage of this novel IC design lies in that no external capacitor is required for the soft-start purpose, because an internal capacitor C1 is used. In other words, no extra capacitor is required. Furthermore, the internal soft-start block 330 can be switched to work with the phase compensation unit so that fewer components are required in the chip design, thereby reducing the PCB size and the cost.
Although the invention has been described in considerable detail with reference to the preferred version thereof, other versions are within the scope of the present invention. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred version contained herein.
This application is related to and claims priority to U.S. provisional patent application, U.S. Provisional Application No. 61/029,924, filed on Feb. 20, 2008, by the applicants Siarhei Kalodka, Sergey Gaitukevich, Vitali Maziarkin, Alan Wang, and Chen-Hui Tsay, entitled “AC/DC converters and methods of manufacturing same.”
Number | Date | Country | |
---|---|---|---|
61029924 | Feb 2008 | US |