The present disclosure relates to acoustic wave devices each including a piezoelectric layer including lithium niobate or lithium tantalate, and methods of manufacturing acoustic wave devices.
Japanese Unexamined Patent Application Publication No. 2012-257019 describes an acoustic wave device.
In the case where the acoustic wave device is in wafer-level packaging by covering an electrode with a substrate (second substrate), a through-via penetrating the substrate (second substrate) is provided. The substrate (second substrate) has a first surface facing the electrode and a second surface facing the opposite side. Conventionally, a through-hole is formed from the second surface by dry etching. The through-hole is tapered such that the hole diameter decreases from the second surface towards the first surface. That is, the opening of the through-hole formed in the second surface is larger than the opening of the through-hole formed in the first surface. Therefore, in the second surface of the substrate (second substrate), the area occupied by the through-via (area where the bump is placed) is increased in size, and the layout of the second surface of the substrate is impaired.
Example embodiments of the present invention provide acoustic wave devices in each of which an area occupied by a through-via on a second surface of a substrate (second substrate) is reduced in size, and methods for manufacturing such acoustic wave devices.
An acoustic wave device according to an example embodiment of the present invention includes a first substrate, a piezoelectric layer including one main surface facing the first substrate in a thickness direction of the first substrate and another main surface facing a direction opposite to the one main surface in the thickness direction, a functional electrode on at least one of the one main surface and the other main surface of the piezoelectric layer, and a second substrate including a first main surface facing the other main surface of the piezoelectric layer, a second main surface facing a direction opposite to the first main surface in the thickness direction, and a through-hole penetrating from the first main surface to the second main surface. An angle at which a side surface of the through-hole is inclined from the second main surface toward the first main surface is equal to or more than about 0° and equal to or less than about 5° based on a normal line with respect to the second main surface.
A method of manufacturing an acoustic wave device according to an example embodiment of the present invention includes a through-hole forming step of forming a through-hole in an object. The object includes a first substrate, a piezoelectric layer including one main surface facing the first substrate in a thickness direction of the first substrate and another main surface facing a direction opposite to the one main surface in the thickness direction, a functional electrode on at least one of the one main surface and the other main surface of the piezoelectric layer, a second substrate including a first main surface facing the other main surface of the piezoelectric layer and a second main surface facing a direction opposite to the first main surface in the thickness direction, and a wiring layer between the piezoelectric layer and the second substrate and bonding the piezoelectric layer and the second substrate. In the through-hole forming step, a through-hole is formed in the second main surface of the second substrate by repeatedly performing a step of performing isotropic etching, a step of depositing a protective film on a side surface and a bottom surface of a hole formed by the isotropic etching, and a step of etching the protective film on the bottom surface.
According to each of example embodiments of the present invention, an area occupied by a through-via on a second surface of a substrate (second substrate) is reduced in size. Therefore, the layout property of the second surface of the substrate is improved.
The above and other elements, features, steps, characteristics and advantages of the present invention will become more apparent from the following detailed description of the example embodiments with reference to the attached drawings.
Hereinafter, example embodiments of the present invention will be described in detail with reference to the drawings. The present disclosure is not limited to the example embodiments. Each example embodiment described in the present invention is merely an example, and in modifications and second and subsequent example embodiments in which partial replacement or combination of configurations is possible between different example embodiments, description of matters common to the first example embodiment will be omitted, and only different points will be described. In particular, the same or similar advantageous effects of similar configurations will not be described in each example embodiment.
In detail, as illustrated in
Here, the electrode 3 is an example of a “first electrode”, and the electrode 4 is an example of a “second electrode”. In
The electrode 3 and the electrode 4 have a rectangular shape and a length direction. The electrode 3 and the electrode 4 adjacent to the electrode 3 face each other in a direction orthogonal to the length direction. The electrodes 3 and 4 and the first and second busbars 5 and 6 constitute interdigital transducer (IDT) electrodes.
The length direction of the electrodes 3 and 4 and the direction orthogonal or substantially orthogonal to the length direction of the electrodes 3 and 4 are each directions intersecting the thickness direction of the piezoelectric layer 2. Therefore, it can be said that the electrode 3 and the electrode 4 adjacent to the electrode 3 face each other in a direction intersecting the thickness direction of the piezoelectric layer 2. In addition, the length direction of the electrodes 3 and 4 may be exchanged with the direction orthogonal or substantially orthogonal to the length direction of the electrodes 3 and 4 illustrated in
A plurality of pairs of structures each including the electrode 3 connected to one potential and the electrode 4 connected to the other potential adjacent to each other is provided in a direction orthogonal or substantially orthogonal to the length direction of the electrode 3 and the electrode 4. Here, the electrode 3 and the electrode 4 being adjacent to each other does not mean the case where the electrode 3 and the electrode 4 are arranged so as to be in direct contact with each other, but means the case where the electrode 3 and the electrode 4 are arranged with a gap therebetween. In addition, when the electrode 3 and the electrode 4 are adjacent to each other, no electrode connected to a hot electrode or a ground electrode, including the other electrodes 3 and 4, is arranged between the electrode 3 and the electrode 4. The number of pairs is not necessary an integer pair, and may be 1.5 pairs, 2.5 pairs, or the like.
The center-to-center distance between the electrode 3 and the electrode 4, that is, the pitch is, for example, preferably in the range of equal to or more than about 1 μm and equal to or less than about 10 μm. In addition, the center-to-center distance between the electrode 3 and the electrode 4 is a distance between the center of the width dimension of the electrode 3 in the direction orthogonal to the length direction of the electrode 3 and the center of the width dimension of the electrode 4 in the direction orthogonal or substantially orthogonal to the length direction of the electrode 4.
Further, when at least one of the electrode 3 and the electrode 4 is plural in number (there are 1.5 or more pairs of electrode sets when the electrodes 3 and 4 are provided as a pair of electrode sets), the center-to-center distance between the electrode 3 and the electrode 4 refers to the average value of the center-to-center distances between the adjacent electrodes 3 and 4 among the 1.5 or more pairs of electrodes 3 and 4.
In addition, the widths of the electrodes 3 and 4, that is, the dimensions of the electrodes 3 and 4 in a facing direction are, for example, preferably in the range of equal to or more than about 150 nm and equal to or less than about 1000 nm. The center-to-center distance between the electrode 3 and the electrode 4 is a distance between the center of the dimension (width dimension) of the electrode 3 in the direction orthogonal or substantially orthogonal to the length direction of the electrode 3 and the center of the dimension (width dimension) of the electrode 4 in the direction orthogonal or substantially orthogonal to the length direction of the electrode 4.
Additionally, in the present example embodiment, since the Z-cut piezoelectric layer is used, the direction orthogonal or substantially orthogonal to the length direction of the electrode 3 and the electrode 4 is a direction orthogonal or substantially orthogonal to a polarization direction of the piezoelectric layer 2. This is not the case when a piezoelectric material having a different cut angle is used as the piezoelectric layer 2. Here, the term “orthogonal” is not limited to the case of being strictly orthogonal, and may be substantially orthogonal (the angle formed by the direction orthogonal to the length direction of the electrodes 3 and 4 and the polarization direction is, for example, about 90°±10°).
A support 8 is laminated on the one main surface 2b side of the piezoelectric layer 2 via an insulating layer 7. The insulating layer 7 and the support 8 have a frame shape, and include opening portions 7a and 8a as illustrated in
The cavity portion 9 is provided so as not to hinder the vibration of an excitation region C of the piezoelectric layer 2. Therefore, the above support 8 is laminated on the one main surface 2b via the insulating layer 7 at a position not overlapping the portion where at least the pair of electrodes 3 and 4 are provided. The insulating layer 7 need not be provided. Therefore, the support 8 can be laminated directly or indirectly on the one main surface 2b of the piezoelectric layer 2.
The insulating layer 7 is made of silicon oxide, for example. However, in addition to silicon oxide, an appropriate insulating material such as, for example, silicon oxynitride or alumina can be used. The support 8 is made of Si, for example. The plane orientation of Si in the surface on the piezoelectric layer 2 side may be (100), (110), or (111). Preferably, Si having a high resistance of, for example, equal to or more than about 4 kΩ is used.
However, the support 8 may be made of an appropriate insulating material or semiconductor material. As the material of the support 8, for example, a piezoelectric material such as aluminum oxide, lithium tantalate, lithium niobate, or quartz, various ceramics such as alumina, magnesia, sapphire, silicon nitride, aluminum nitride, silicon carbide, zirconia, cordierite, mullite, steatite, or forsterite, a dielectric material such as diamond or glass, or a semiconductor such as gallium nitride can be used.
The plurality of electrodes 3 and 4, the first busbar 5, and the second busbar 6 described above are made of an appropriate metal or alloy such as, for example, Al or an AlCu alloy. In the present example embodiment, the electrodes 3 and 4, the first busbar 5, and the second busbar 6 have a structure including an Al film laminated on a Ti film. An adhesion layer other than the Ti film may be used.
During driving, an AC voltage is applied between the plurality of electrodes 3 and the plurality of electrodes 4. More specifically, an AC voltage is applied between the first busbar 5 and the second busbar 6. Thus, it is possible to obtain resonance characteristics using a bulk wave in the first-order thickness-shear mode excited in the piezoelectric layer 2.
Additionally, in the acoustic wave device 1, d/p is, for example, equal to or less than about 0.5, when d is the thickness of the piezoelectric layer 2, and p is the center-to-center distance between any adjacent electrodes 3 and 4 among the plurality of pairs of electrodes 3 and 4. Therefore, the above bulk wave of the first-order thickness-shear mode is effectively excited, and favorable resonance characteristics can be obtained. More preferably, for example, d/p is equal to or less than about 0.24, and in this case, even more favorable resonance characteristics can be obtained.
In the case where at least one of the electrodes 3 and 4 is plural in number as in the present example embodiment, that is, there are 1.5 or more pairs of electrodes 3 and 4 sets when the electrodes 3 and 4 are provided as a pair of electrode sets, the center-to-center distance p between the adjacent electrodes 3 and 4 is the average distance of the center-to-center distances between the respective adjacent electrodes 3 and 4.
Since the acoustic wave device 1 of the present example embodiment has the above-described configuration, even when the number of pairs of the electrodes 3 and 4 is reduced in order to achieve miniaturization, the Q value is unlikely to be reduced. This is because the resonator does not require reflectors on both sides and has a small propagation loss. In addition, the reflector is not required because the bulk wave in the first-order thickness-shear mode is used. The difference between the Lamb wave used in the existing acoustic wave device and the bulk wave in the first-order thickness-shear mode will be described with reference to
In contrast, as illustrated in
As illustrated in
As described above, in the acoustic wave device 1, at least one pair of electrodes including the electrode 3 and the electrode 4 is arranged, but since the acoustic wave device 1 does not propagate a wave in the X direction, the number of pairs of electrodes including the electrodes 3 and 4 is not necessary plural. That is, it is sufficient that at least one pair of electrodes is provided.
For example, the electrode 3 is an electrode connected to a hot potential, and the electrode 4 is an electrode connected to a ground potential. However, the electrode 3 may be connected to the ground potential, and the electrode 4 may be connected to the hot potential. In the present example embodiment, as described above, at least one pair of electrodes includes an electrode connected to the hot potential or an electrode connected to the ground potential, and no floating electrode is provided.
The length of the excitation region C is a dimension of the excitation region C along the length direction of the electrode 3 and the electrode 4. In the present example embodiment, the inter-electrode distances of the electrode pairs each including the electrode 3 and the electrode 4 were made all equal or substantially equal in the plurality of pairs. That is, the electrodes 3 and the electrodes 4 were arranged at an equal or substantially equal pitch.
As is clear from
As described above, in the present example embodiment, d/p is, for example, equal to or less than about 0.5, and more preferably equal to or less than about 0.24, when d is the thickness of the piezoelectric layer 2 and p is the center-to-center distance between the electrode 3 and the electrode 4. This will be described with reference to
A plurality of acoustic wave devices were obtained in the same or substantially the same manner as the acoustic wave device having the resonance characteristics illustrated in
As is clear from
As described above, at least one pair of electrodes may be one pair, and the above p is defined as the center-to-center distance between the adjacent electrodes 3 and 4 in the case of one pair of electrodes. Additionally, in the case of equal to or more than 1.5 pairs of electrodes, the average distance of the center-to-center distances between the adjacent electrodes 3 and 4 may be p. In addition, when the piezoelectric layer 2 has a variation in thickness, the thickness d of the piezoelectric layer may be obtained from the average value of the thicknesses.
In the acoustic wave device 1, preferably, the metallization ratio MR of the adjacent electrodes 3 and 4 with respect to the excitation region, which is a region where any adjacent electrodes 3 and 4 among the plurality of electrodes 3 and 4 overlap each other when viewed in a direction in which the adjacent electrodes 3 and 4 face each other, satisfy MR about 1.75 (d/p)+0.075, for example. In this case, spurious emission can be effectively reduced. This will be described with reference to
The metallization ratio MR will be explained with reference to
The area of the electrodes 3 and 4 in the excitation region C with respect to the area of the excitation region is the metallization ratio MR. That is, the metallization ratio MR is the ratio of the area of the metallization portion with respect to the area of the excitation region. When a plurality of pairs of electrodes are provided, the ratio of the metallization portions included in the entire excitation region with respect to the total area of the excitation regions may be defined as MR.
In the region surrounded by an ellipse J in
Therefore, the fractional bandwidth can be sufficiently increased when the Euler angles satisfy the above Expression (1), Expression (2), or Expression (3), which is preferable. The basic configuration of the acoustic wave device has been described above, but the present invention may be applied to an acoustic wave device 81 according to the following modification.
In
In the acoustic wave device 81, an alternating electric field is applied to the IDT electrode 84 on the cavity portion 9, and thus a Lamb wave as a plate wave is excited. Since the reflector 85 and the reflector 86 are provided on both sides, the resonance characteristics by the Lamb wave can be obtained. As described above, an acoustic wave device according to an example embodiment of the present invention may use a plate wave. Next, the acoustic wave device of the present example embodiment will be described in detail.
As illustrated in
The first substrate 8A is obtained by cutting the support 8 (see
In the present example embodiment, the opening portion 7a is provided in a center portion of the insulating layer 7. On the other hand, the opening portion 8a (see
The functional electrode 84A is the IDT electrode 84 (see
The second wiring layer 22 is, for example, an Au layer. The first wiring layer 23 includes a plurality of layers made of different metals, and in the present example embodiment, the first wiring layer 23 includes, for example, a Ti layer, a Pt layer, and an Au layer that are laminated in this order from the via electrode side (the second thickness direction Z2). In addition, the second wiring layer 22 is provided on the first substrate 8A side, and the first wiring layer 23 is provided on the second substrate 50 side. When the first substrate 8A and the second substrate 50 are bonded to each other, the Au layer of the second wiring layer 22 and the Au layer of the first wiring layer 23 are bonded to each other (Au—Au bonding).
In addition, a frame portion 40 surrounding the functional electrode 84A and the wiring layer 20 is provided between the piezoelectric layer 2 and the second substrate 50. The frame portion 40 seals portions between the piezoelectric layer 2 and the second substrate 50. The frame portion 40 includes a first frame layer 41, a second frame layer 42, a third frame layer 43, and a fourth frame layer 44 that are laminated in this order from the second thickness direction Z2. The first frame layer 41 is made of the same material as the first wiring layer 23. That is, the first frame layer 41 is formed on the second substrate 50 simultaneously with the first wiring layer 23. Similarly, the second frame layer 42 is made of the same material as the second wiring layer 22, and is formed on the first substrate 8A simultaneously with the second wiring layer 22. Thus, the first frame layer 41 and the second frame layer 42 are bonded to each other by Au—Au bonding, as in the case of the first wiring layer 23 and the second wiring layer 22. A third frame layer 43 is made of the same material as the intermediate wiring layer 21, and is a layer formed simultaneously with the intermediate wiring layer 21. A fourth frame layer 44 is made of the same material as the functional electrode 84A, and is a layer formed simultaneously with the functional electrode 84A.
In the present example embodiment, the second substrate 50 is made of, for example, Si. However, the material of the second substrate 50 is not limited to Si, and the same kind of material as the first substrate 8A can be used. The second substrate 50 includes a first main surface 50a facing the first thickness direction Z1, a second main surface 50b facing the second thickness direction Z2, and the through-hole 51 penetrating from the first main surface 50a to the second main surface. The first main surface 50a faces the other main surface 2b of the piezoelectric layer 2. The second main surface 50b faces the direction opposite to the first main surface 50a in the thickness direction.
The through-hole 51 penetrates the second substrate 50 in the thickness direction. The first wiring layer 23 is arranged on the bottom portion of the through-hole 51 in the first thickness direction Z1. The first wiring layer 23 (wiring layer 20) is provided with a recess 25 recessed from the through-hole 51 toward the first thickness direction Z1 (see
As illustrated in
As illustrated in
The via electrode 52 is provided in the through-hole 51 and on the inner peripheral side of the seed layer 55. That is, the seed layer 55 is arranged between the via electrode 52 and the insulating layer (silicon oxide film) 54. In addition, the end portion of the via electrode 52 in the first thickness direction Z1 is electrically connected to the first wiring layer 23 via the seed layer 55. In addition, as illustrated in
As described above, according to the present example embodiment, since the opening of the through-hole 51 in the second thickness direction Z2 is small, the region occupied by the via electrode 52 on the second main surface 50b of the second substrate 50 is also small. Therefore, the layout of the second main surface 50b of the second substrate 50 is improved. Next, the inside of the through-hole 51 will be described in detail.
In addition, a thickness L2 of the insulating layer 54 is, for example, equal to or more than about 50 nm and equal to or less than about 3 μm. Preferably, the thickness L2 of the insulating layer 54 is, for example, greater than about 100 nm and equal to or less than about 1 μm. This is because the height (surface roughness) L1 of the convex portion of the side surface 51a is equal to or less than about 100 nm, and thus, when the thickness L2 of the insulating layer 54 is greater than about 100 nm, the disconnection does not occur. In an example embodiment of the present invention, the thicknesses L2 of the insulating layers 54 may, for example, exceed about 50 nm or be less than about 3 μm.
In addition, a thickness L3 of the seed layer 55 is larger than the height L1 (surface roughness) of the convex portion of the side surface 51a and is, for example, equal to or less than about 300 μm. When the seed layer is formed by laminating the Ti layer and the Cu layer in this order, the Ti layer and the Cu layer are laminated in this order on the insulating layer (silicon oxide film) 54. In addition, when the seed layer 55 is a single layer of, for example, the Ti layer, the Ti layer is laminated on the insulating layer (silicon oxide film) 54. The thickness of the Ti layer of the seed layer 55 is larger than the height L1 (surface roughness) of the convex portion of the side surface 51a and is, for example, equal to or less than about 300 μm. This avoids disconnection of the seed layer 55 (Ti layer). In an example embodiment of the present invention, the thickness L3 of the seed layer 55 (Ti layer) may be, for example, equal to or less than the height L1 (surface roughness) of the convex portion of the side surface 51a or may exceed about 300 μm. In an example embodiment of the present invention, when the seed layer 55 is formed of a single Cu layer, the thickness of the Cu layer may be larger than the height L1 (surface roughness) of the convex portion of the side surface and may be, for example, equal to or less than about 300 μm. This is because the disconnection of the Cu layer can be avoided also by this.
Next, an example of a method of manufacturing the acoustic wave device according to the present example embodiment will be described. The method of manufacturing the acoustic wave device includes a bonding step S1, a through-hole forming step S2, an insulating film forming step S3, a dry etching step S4, a seed layer laminating/resist film forming/plate processing step S5, a resist film removing/window forming step S6, a dicing step S7, a soldering step S8, and a singulation/polishing step S9.
In the bonding step S1, the second wiring layer 22 (Au layer) and the Au layer of the first wiring layer 23 are bonded by Au—Au bonding. In addition, the second frame layer 42 (Au layer) and the Au layer of the first frame layer 41 are bonded by Au—Au bonding. Thus, as illustrated in
Additionally, in the present example embodiment, the insulating layer 54 is provided on the second main surface 50b of the second substrate 50. Therefore, in the present example embodiment, a portion of the insulating layer 54 provided on the second main surface 50b is also removed by the through-hole forming step S2. In addition, unevenness is formed on the side surface 51a of the through-hole 51 (see
A gas used in the dry etching step S4 is, for example, any one of C4F8 gas, CF4 gas, CHF3 gas, and SF6 gas. In addition, the dry etching step S4 is performed to meet an over-edge condition. Thus, the recess 25 is formed in the wiring layer 20 arranged at the insulating layer 54 in the first thickness direction Z1. The recess 25 is formed in the first wiring layer 23 of the wiring layer 20 arranged in the second thickness direction Z2.
Here, the first wiring layer 23 is formed by laminating the Ti layer, the Pt layer, and the Au layer in this order from the second thickness direction Z2. Therefore, when the amount of depth of the recess 25 is to the extent that a portion of the Ti layer in the thickness direction is removed, the bottom surface of the recess 25 is the Ti layer. In addition, when the amount of depth of the recess 25 is to the extent that the Ti layer is removed entirely in the thickness direction, the bottom surface of the recess 25 is the Pt layer. In addition, when the depth size of the recess 25 is to the extent that the Ti layer and the Pt layer are removed, the bottom surface of the recess 25 is the Au layer. As described above, in the present example embodiment, the bottom surface of the recess 25 may be any of the Ti layer, the Pt layer, and the Au layer.
In an example embodiment of the present invention, the first wiring layer 23 may be formed of a material other than the Ti layer, the Pt layer, and the Au layer. In such a case (the case where the first wiring layer 23 includes the first layer, . . . , the (n−1)-th layer, and the n-th layer laminated in order from the second thickness direction Z2), the bottom surface of the recess may be the (n−1)-th layer. Note that n is an integer of 2 or more.
To be specific, portions where the seed layer 55 is laminated are the insulating layer 54 provided on the second main surface 50b of the second substrate 50, the side surface 51a of the through-hole 51, and the recess 25. Here, the seed layer 55 laminated in the recess 25 is laminated on any one of the Ti layer, the Pt layer, and the Au layer in the first wiring layer 23. In addition, in the case where the seed layer 55 is formed of lamination of the Ti layer and the Cu layer, when the layer in contact with the seed layer 55 is a single layer of the Ti layer or the Pt layer, the Ti layer and the Cu layer are laminated in this order on the first wiring layer 23. The step of laminating the seed layer 55 in the seed layer laminating/resist film forming/plate processing step S5 may be referred to as a seed layer laminating step.
A resist film 60 is laminated on the seed layer 55 laminated on the second main surface 50b in the second thickness direction Z2. In addition, the resist film 60 is provided with an opening portion 61. The opening portion 61 exposes the through-hole 51 and the periphery of the opening of the through-hole 51 in the second thickness direction Z2.
The plate processing is performed on the portion exposed from the opening portion 61 of the resist film 60. Further, before the plate processing, it is preferable to perform surface treatment on the portion exposed from the opening portion 61 of the resist film 60 by, for example, a PR method. The plate processing is performed in the order of Au, Ti, and Cu. As a result, the via electrode 52 is formed in the through-hole 51. In addition, the under bump metal 56 is formed in the opening portion 61.
The forming the bump window 63 and the dicing window 64 includes providing a resist layer (not illustrated) at portions where the bump window 63 and the dicing window 64 are to be formed, and forming an insulating film on the resist layer. Thereafter, the resist layer is removed. According to this, the portion where the resist layer is provided becomes an opening portion which is not covered with the insulating layer. In addition, the central portion of the under bump metal 56 in the second thickness direction Z2 is exposed by the bump window 63. Further, the boundary, on the second main surface 50b of the second substrate 50, between the plurality of intermediate products 90 is exposed by the dicing window 64.
While example embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.
This application claims the benefit of priority to Provisional Application No. 63/253,593 filed on Oct. 8, 2021 and is a Continuation Application of PCT Application No. PCT/JP2022/037495 filed on Oct. 6, 2022. The entire contents of each application are hereby incorporated herein by reference.
Number | Date | Country | |
---|---|---|---|
63253593 | Oct 2021 | US |
Number | Date | Country | |
---|---|---|---|
Parent | PCT/JP2022/037495 | Oct 2022 | WO |
Child | 18627897 | US |