Active auto zero circuit for programmable time continuous open loop amplifiers

Abstract

An active offset cancellation circuit for an open loop differential amplifier having programmable gain is disclosed. The amplifier is operated on a two-phase clock where the normal operation occurs on the first phase and offset detection and cancellation occurs on the second phase. On the first phase, the programmable gain of the amplifier is set according to the application of the amplifier. On the second phase, the programmable gain of the amplifier is set to the maximum value and the offset cancellation circuit measures the offset created by the amplifier when both differential inputs are connected to a common source. The circuit then adjusts a bias current and stores this adjustment to cancel offset during the operational phase of the amplifier. During the operational phase, the first phase of the clock, the programmable gain is again returned to a value according to the application and the stored adjustment is used to bias the current in one of the two input stages of the amplifier, canceling any offset imparted by the amplifier circuitry. One each clock cycle, any additional offset is similarly detected and canceled. Further, by varying the gain as described, residual offset is reduced.

Description

BACKGROUND

[0002] Computer hard disk drives, also known as fixed disk drives or hard drives, have become a de facto standard data storage component of modern computer systems and are making further inroads into modern consumer electronics as well. Their proliferation can be directly attributed to their low cost, high storage capacity and high reliability, in addition to wide availability, low power consumption, high data transfer speeds and decreasing physical size.

[0003] These disk drives typically consist of one or more rotating magnetic platters encased within an environmentally controlled housing that further includes all of the electronics and mechanics to read and write data and interface with other devices. Read/write heads are positioned above each of the platters, and typically on each face, to record and read data. The electronics of a hard disk drive are coupled with these read/write heads and include numerous components to control the position of the heads and generate or sense the electromagnetic fields representing data. These components receive data from a host device, such as a personal computer, and translate that data into magnetic encodings written onto the disk platters by the heads. Further, when a host device requests data from the drive, the electronics locates the desired data, senses the magnetic encodings which represent that data and translates those encodings back into the binary digital information which the host device can understand. Further, error detection and correction algorithms are applied to ensure accurate storage and retrieval of data.

[0004] One area in which significant advancements have been made has been in the area of read/write head technology and the methods of interpreting the magnetic fluctuations sensed by these heads. The read/write head, of which a typical hard disk has several, is the interface between magnetic platters and the disk drive electronics. The read/write head actually reads and writes the magnetically encoded data as areas of magnetic flux on the platters. Data, consisting of binary 1's and 0's, are encoded by sequences of the presence or absence of flux reversals recorded or detected by the read/write head. A flux reversal is a change in the magnetic flux in two contiguous areas of the disk platter. Traditional hard drives read data off the platters by detecting the voltage peak imparted in the read/write head when a flux reversal passes underneath the read/write head as the platters rotate. This is known as “peak detection.”However, increasing storage densities require reduced peak amplitudes and better signal discrimination and higher platter rotational speeds are pushing the peaks closer together thus making peak detection more difficult to accomplish.

[0005] Magneto-resistive (“MR”) read/write heads have been developed with increased sensitivity to sense smaller amplitude magnetic signals and with increased signal discrimination to address some of the problems with increasing storage densities. In addition, another technology, known as Partial Response Maximum Likelihood (“PRML”), has been developed to further address the problems with peak detection as densities and rotational speeds increase. Borrowed from communications technology, PRML is an algorithm implemented in the disk drive electronics to interpret the magnetic signals sensed by the read/write heads. PRML-based disk drives read the analog waveforms generated by the magnetic flux reversals stored on the disk. However, instead of looking for peak values to indicate flux reversals, PRML-based drives digitally sample this analog waveform (the “Partial Response”) and use advanced signal processing technologies to determine the bit pattern represented by that wave form (the “Maximum Likelihood”). This technology, in conjunction with magneto-resistive (“MR”) heads, have permitted manufacturers to further increase data storage densities. PRML technology further tolerates more noise in the sensed magnetic signals permitting the use of lower quality platters and read/write heads which increases manufacturing yields and lowers costs.

[0006] With many different drives available from multiple manufacturers, hard disk drives are typically differentiated by factors such as cost/megabyte of storage, data transfer rate, power requirements and form factor (physical dimensions) with the bulk of competition based on cost. With most competition between hard disk drive manufacturers coming in the area of cost, there is a need for enhanced hard disk drive components which prove cost effective in increasing supplies and driving down manufacturing costs all while increasing storage capacity, operating speed, reliability and power efficiency.

SUMMARY

[0007] The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims. By way of introduction, the preferred embodiments described below relate to a differential amplifier. The differential amplifier comprises a first input stage operative to receive a first input signal and a second input stage operative to receive a second input signal. The differential amplifier also includes a programmable gain input operative to set a gain of the differential amplifier, an output stage operative to produce an output signal equal to the amplification of the difference between the first signal and the second signal according to the gain, and an offset cancellation circuit operative to actively cancel offset voltage in the output signal added by the differential amplifier and vary the gain to reduce residual offset.

[0008] The preferred embodiments further relate to a method of canceling offset between first and second stages of an open loop differential amplifier having a variable gain. In one embodiment, the method comprises disconnecting inputs to the first and second stages from an input source, setting the variable gain to a maximum value, connecting the inputs to a common voltage source; detecting output offset voltage on outputs of the amplifier, computing an adjusted bias current to cancel the output offset voltage, disconnecting the inputs from the common voltage source, reconnecting the inputs to the input source, setting the variable gain to an application value, and applying the adjusted bias current to cancel the output offset voltage.

[0009] Further aspects and advantages of the invention are discussed below in conjunction with the preferred embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1A depicts a block diagram of an exemplary hard disk drive coupled with a host device.

[0011] FIG. 1B depicts a block diagram of read/write channel for use with the disk drive of FIG. 1A.

[0012] FIG. 2 depicts a gain cell based open loop amplifier stage according to a first embodiment.

[0013] FIG. 3 depicts a timing diagram showing the operation of the amplifier stage of FIG. 2 according to a first embodiment.

[0014] FIG. 4 depicts a timing diagram showing the operation of the amplifier stage of FIG. 2 according to a second embodiment.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

[0015] The embodiments described herein relate to a PRML-based read/write channel device for hard disk drive controllers. The read/write channel is a device coupled with the read/write heads of the hard disk drive. Herein, the phrase “coupled with” is defined to mean directly connected to or indirectly connected with through one or more intermediate components. Such intermediate components may include both hardware and software based components. The read/write channel converts binary/digital data from the host device into the electrical impulses which drive the read/write head to magnetically record the data to the disk drive platters. Further, the read/write channel receives the analog waveform magnetically sensed by the read/write heads and converts that waveform back into the binary/digital data stored on the drive.

[0016] Referring to FIG. 1A, there is shown a block diagram of an exemplary hard disk drive 100 coupled with a host device 112. For clarity, some components, such as the servo/actuator motor control, are not shown. The drive 100 includes the magnetic platters and spindle motor 102, the read/write heads and actuator assembly 104, pre-amplifiers 106, a read/write channel 108 and a controller 110. The pre-amplifiers 106 are coupled with the read/write channel 108 via interfaces 114, 116. The controller 110 interfaces with the read/write channel 108 via interfaces 118, 120.

[0017] For reads from the hard disk 100, the host device 112 provides a location identifier which identifies the location of the data on the disk drive, e.g. a cylinder and sector address. The controller 110 receives this address and determines the physical location of the data on the platters 102. The controller 110 then moves the read/write heads into the proper position for the data to spin underneath the read/write heads 104. As the data spins underneath the read/write head 104, the read/write head 104 senses the presence or absence of flux reversals, generating a stream of analog signal data. This data is passed to the pre-amplifiers 106 which amplifies the signal and passes it to the read/write channel 108 via the interface 114. As will be discussed below, the read/write channel receives the amplified analog waveform from the pre-amplifiers 106 and decodes this waveform into the digital binary data that it represents. This digital binary data is then passed to the controller 110 via the interface 118. The controller 110 interfaces the hard drive 100 with the host device 112 and may contain additional functionality, such as caching or error detection/correction functionality, intended to increase the operating speed and/or reliability of the hard drive 100.

[0018] For write operations, the host device 112 provides the controller 110 with the binary digital data to be written and the location, e.g. cylinder and sector address, of where to write it. The controller 110 moves the read/write heads 104 to the proper location and sends the binary digital data to be written to the read/write channel 108 via interface 120. The read/write channel 108 receives the binary digital data, encodes it and generates analog signals which are used to drive the read/write head 104 to impart the proper magnetic flux reversals onto the magnetic platters 102 representing the binary digital data. The generated signals are passed to the pre-amplifiers 106 via interface 116 which drive the read/write heads 104.

[0019] Referring to FIG. 1B, there is shown an exemplary read/write channel 108 supporting Partial Response Maximum Likelihood (“PRML”) encoding technology for use with the hard disk drive 100 of FIG. 1A. For clarity, some components have been omitted. The read/write channel 108 is implemented as an integrated circuit using a complementary metal oxide semiconductor (“CMOS”) process at 0.18 micron. It will be appreciated that CMOS processes include processes which use metal gates as well as polysilicon gates. It will further be appreciated that other process technologies and feature sizes may used and that the circuitry disclosed herein may be further integrated with other circuitry comprising the hard disk electronics such as the hard disk controller logic. As was described, the read/write channel 108 converts between binary digital information and the analog signals representing the magnetic flux on the platters 102. The read/write channel 108 is divided into two main sections, the read path 156 and the write path 158.

[0020] The write path 158 includes a parallel-to-serial converter 144, a run-length-limited (“RLL”) encoder 146, a parity encoder 148, a write pre-compensation circuit 150 and a driver circuit 152. The parallel-to-serial converter 144 receives data from the host device 112 via interface 120 eight bits at a time. The converter 144 serializes the input data and sends the serial bit stream to the RLL encoder 146. The RLL encoder 146 encodes the serial bit stream into symbolic binary sequences according to a known run-length limited algorithm for recording on the platters 102. The exemplary RLL encoder uses a 32/33 bit symbol code to ensure that flux reversals are properly spaced and that long runs of data without flux reversals are not recorded. The RLL encoded data is then passed to the parity encoder 148 which adds a parity bit to the data. In the exemplary parity encoder 148, odd parity is used to ensure that long run's of 0's and 1's are not recorded due to the magnetic properties of such recorded data. The parity encoded data is subsequently treated as an analog signal rather than a digital signal. The analog signal is passed to a write pre-compensation circuit 150 which dynamically adjusts the pulse widths of the bit stream to account for magnetic distortions in the recording process. The adjusted analog signal is passed to a driver circuit 152 which drives the signal to the pre-amplifiers 106 via interface 116 to drive the read/write heads 104 and record the data. The exemplary driver circuit 152 includes a pseudo emitter coupled logic (“PECL”) driver circuit which generates a differential output to the pre-amplifiers 106.

[0021] The read path 156 includes an attenuation circuit/input resistance 122, a variable gain amplifier (“VGA”) 124, a magneto-resistive asymmetry linearizer (“MRA”) 126, a continuous time filter (“CTF”) 128, a buffer 130, an analog to digital converter (“ADC”) 132, a finite impulse response (“FIR”) filter 134, an interpolated timing recovery (“ITR”) circuit 136, a Viterbi algorithm detector 138, a parity decoder 140 and a run-length-limited (“RLL”) decoder 142. The amplified magnetic signals sensed from the platters 102 by the read/write head 104 are received by the read/write channel 108 via interface 114. The analog signal waveform representing the sensed magnetic signals is first passed through an input resistance 122 which is a switching circuit to attenuate the signal and account for any input resistance. The attenuated signal is then passed to a VGA 124 which amplifies the signal. The amplified signal is then passed to the MRA 126 which adjusts the signal for any distortion created by the recording process. Essentially, the MRA 126 performs the opposite function of the write-pre-compensation circuit 150 in the write path 158. The signal is next passed through the CTF 128, which is essentially a low pass filter, to filter out noise. The filtered signal is then passed to the ADC 132 via the buffer 130 which samples the analog signal and converts it to a digital form. The digital signal is then passed to a FIR filter 134 and then to a timing recovery circuit 136. The timing recovery circuit 136 is connected (not shown in the figure) to the FIR filter 134, the MRA 126 and the VGA 124 in a feedback orientation to adjust these circuits according to the signals received to provide timing compensation. The exemplary FIR filter 134 is a 10 tap FIR filter. The digital signal is then passed to the Viterbi algorithm detector 138 which determines the binary bit pattern represented by the digital signal using digital signal processing techniques. The exemplary Viterbi algorithm detector 138 uses a 32 state Viterbi processor. The binary data represented by the digital signal is then passed to the parity decoder 140 which removes the parity bit and then to the RLL decoder 142 which decodes the binary RLL encoding symbols back into the actual binary data that they represents This data is then passed to the controller 110 via the interface 118.

[0022] The read/write channel 108 further includes a clock synthesizer 154. The clock synthesizer 154 generates the clock signals required for operating the read/write channel 108. The exemplary clock synthesizer 154 includes a phased lock look (“PLL”) (not shown) with a voltage controlled oscillator and various clock dividers to generate the necessary frequencies.

[0023] In particular, the voltage gain amplifier 124 includes a continuous open loop differential amplifier which receives and amplifies a differential signal. Signals that are represented by the difference between two voltages or currents are referred to as differential signals. In effect, differential inputs subtract two input signals, a positive and a negative, from each other. A positive signal is represented when the positive input is greater than the negative input and a negative signal is represented when the negative signal is greater than the positive. When the positive input is equal to the negative input, the signal represented is zero. The result is lower noise as noise will be present on both inputs and will be subtracted away, leaving just the signal. Differential signals also offer the advantage of a requiring a lower voltage swing to represent binary values, allowing for faster switching. Further differential signals simplify grounding in a system as the signal is not derived from comparing one input with a ground reference.

[0024] One problem that can occur with differential signals is known as offsetting. Offsetting is a difference in the input offset current or voltage. In particular, input offset current or voltage is the difference in bias current or voltage when measured between two differential inputs, such as the positive and negative inputs of an amplifier. The offset is essentially a difference in one of the two differential signals that is not due to the actual signal represented and is not mirrored in the other input as with noise. CMOS based amplifiers typically suffer from offset voltages introduced by mismatches of the input stage or other components of the amplifier.

[0025] Offset cancellation has been performed using output offset storage. In this method, an serial capacitive circuit is placed on each of the outputs of the amplifier. The circuit is operated on a two-phase non-overlapping clock. On the first phase, the input signal is connected to the amplifier and the output of the amplifier is generated as normal. On the second phase of the clock, the signal inputs are disconnected from the amplifier and an offset compensation reference voltage is applied to both inputs of the amplifier. Similarly, the amplifier outputs are also coupled to a second offset compensation reference voltage. The reference voltages differentially charge the capacitors connected with each amplifier output according to the offset imparted by the amplifier. The different voltages stored in the capacitors then compensate for the offset imparted by the amplifier during normal operation.

[0026] Unfortunately, the addition of capacitors on the amplifier outputs also adds parasitic capacitance to the overall circuit reducing the bandwidth of the amplifier. Further, the output capacitors together with the input capacitance of a building block, i.e. another circuit, connected to the output of the amplifier form a voltage divider which reduces the effective output swing of the amplifier.

[0027] Herein is disclosed a technique for active offset cancellation by injecting an asymmetric bias current in the output stage of the amplifier during an auto-zero period. The auto-zero period is defined as a phase of amplifier operation where the signal inputs and outputs are disconnected. The amplifier operates in two phases, normal operation where the inputs are amplified to the outputs and the auto-zero period as described below. The disclosed technique cancels any statistical offsets generated within the amplifier. Since no capacitive coupling is used in the signal path, the bandwidth and effective output swing of the amplifier are maintained. In addition to eliminating additional active or passive components in the signal path, the bias current of the input stage and current mirrors does not have to be varied.

[0028] Referring now to FIG. 2, there is shown a first embodiment of a gain cell based open loop amplifier stage 200 for use in a variable gain amplifier. The amplifier stage 200 includes inputs 234, 236 (labeled “INP” & “INN”), positive and negative input stages 202, 204, (labeled “N1P” & “N1N”), bias current sources 206, 208 for each input stage (labeled “I1P” & “I1N”), current mirrors 210, 212 for each input stage (labeled “CMP” & “CMN”), gain setting resistors 214, 216, 218 (labeled “R1”, “R2P” & “R2N”), an output common mode loop 220 (consisting of components labeled “N2P”, “N2N”, “N3P”, “R3P”, “R3N” & “OP1”) and outputs 238, 240 (labeled “OUTP” & “OUTN”). Further, the amplifier stage 200 includes switches 222, 224, 226, 228 (labeled “S1P”, “S1N”, “S2P”, “S2N”) and control loop 232 (consisting of components labeled “OP2”, “CAZ” & “N3N” and switch 230 labeled “S3”).

[0029] The switches 222, 224, 226, 228, 230 and the control loop 232 can be used to generate an asymmetric variation of the bias current of the output stage in order to detect and cancel the output offset voltage. The op-amp 242 acts as a offset detector controlling the compensation circuit consisting of transistor 244 and capacitor 246 which acts as an offset compensator.

[0030] Referring to FIG. 3, there is shown a timing diagram 300 of the operation of a first embodiment of the amplifier stage 200. The amplifier stage 200 operates on a two phase non-overlapping clock with phase 1 labeled “Φ1” and phase 2 labeled “Φ2.” The differential input signal seen at the gates of the input transistors 202, 204 is labeled as “X1-X2”. The differential output signal of the amplifier 200 which contains a differential offset component is labeled “OUTP-OUTN” and represents the signal measured at outputs 238, 240. Relevant portions of the timing diagram are labeled “A”, “B1”, “B2”, “C” and “D”.

[0031] In operation, during timing portion A, switches 222, 224 are closed and switches 226, 228, 230 are open. This is the regular operation of the amplifier. For the given input differential X1-X2 at A, the OUTP-OUTN amplified differential output containing a differential offset component is shown.

[0032] At timing portion B1, switches 222, 224 are opened and switches 226, 228, 230 are closed. This disconnects the inputs 234, 236 of the amplifier 200 from the input transistors 202, 204 and at the same time connects the gates of transistors 202, 204 to an input common mode voltage, labeled “VCMIN”. With the differential input voltage being zero (because both inputs are connected to the same voltage source), the output voltage OUTP-OUTN at the amplifier 200 outputs 238, 240 should be zero. Any non-zero voltage is due to offsets of one or more amplifier components. With switch 230 closed, the control loop 232 operates such that the offset at the outputs 238, 240 is reduced by means of reducing or increasing the current through resistor 218 using transistor 244 which eventually reduces the differential voltage OUTP-OUTN to zero. This is shown at timing portion B2. This happens because the op amp 242 (labeled “OP2”) compares the outputs 238, 240 and places a control voltage on the gate of transistor 244 (labeled “N3N”). If the voltage at output 240 is higher than the voltage at output 238 then the output of the op-amp 242 is increased causing the gate to source voltage of transistor 244 to be increased which in turn increases the current drawn by transistor 244 from output 240 to ground. This reduces the current flowing across resistor 218 and therefore the voltage at output 240 drops. This process continues until the voltage of the output 240 is equal to the voltage at output 238. The process works opposite for the voltage at output 238 being higher than the voltage at output 240. The control voltage generated by the op-amp 242 is stored in the capacitor 246 (labeled “CAZ”).

[0033] At timing portion C, switches 222, 224 are again closed and switches 226, 228, 230 are opened. These switch setting cause resumption of regular operation of the amplifier 200 except that any differential offset in OUTP-OUTN has been cancelled. The offset is cancelled because the control voltage for transistor 244 is stored in capacitor 246 maintaining the offset cancellation effect of transistor 244. Essentially timing portion C is the same as timing portion A, except that the offset has been cancelled.

[0034] Timing portion D is the same as portion B1/B2 except that only additional offset incurred during the previous operational cycle need be cancelled.

[0035] The operation of the amplifier stage 200 continues as described, alternating between operational and offset cancellation phases.

[0036] Referring now to FIG. 4, there is shown a second timing diagram 400 depicting operation of a second embodiment of the amplifier of FIG. 2 wherein the amplifier has programmable gain. Referring back to FIG. 2, the gain of the amplifier 200 as shown is determined by the ratio of the input and output resistor networks. Given that the value of R2P 216 equals R2N 218 equals a particular value, R2, the gain A of the amplifier 200 can be described as A=(N·2·R2/R1 214), with N being the mirror ratio of the current mirrors, CMP 210 and CMN 212. By adjusting the values of R1 214, R2P 216 and R2N 218 the gain of the amplifier 200 can be programmed and varied e.g. by a micro controller. For example, resistors R1 214 and R2P 216 and R2N 218 may be replaced by digital busses allowing variance of the resistance values, and therefore the amplifier 200 gain, in discrete steps. For a more detailed description of a programmable gain amplifier, refer to U.S. patent application Ser. No. 09/866,147, entitled “REGULATED MOS RESISTOR IN OPEN LOOP AMPLIFIER” filed May 25, 2001, herein incorporated by reference.

[0037] In this embodiment, operation of the amplifier 200 is similar to that described above except that the resistance values of the resistors, R1 214 and R2P 216 & R2N 218, are capable of being varied, programmatically or otherwise. For example, R1 214 and R2P 216 & R2N 218 may each be varied from 100 to 10,000 Ohms. This allows the gain of the amplifier 200 to be varied during the operational and offset cancellation phases. Assuming that the source of offset voltage of the amplifier 200 is concentrated in the input transistors NIP 202 and N1N 204 it will be appreciated that this offset voltage gets amplified by the gain A of the amplifier 200.

[0038] Assuming that the open loop gain of the auto zero control loop, consisting of OP2 242, S3 230, CAZ 246 and N3N 244 is not infinite there will be some residual offset remaining at the end of the auto zero phase (Φ2=1 in FIGS. 3 and 4). If the gain A of an amplifier 200 with variable resistances 214, 216, 218 would be increased after the end of the auto zero phase, then the residual offset would be increased as well. In order to avoid this increase of residual offset, this embodiment uses the highest available gain setting when Φ2=1, i.e. during the offset cancellation phase. If the gain remains the same or is reduced after the end of the offset cancellation phase, Φ2=1, the residual offset will similarly be maintained the same or reduced. The reduction of the residual offset is related to the reduction of the gain setting from the offset cancellation phase to what is used after offset cancellation. This relationship is a linear relationship, i.e. a ½ reduction in the gain setting results in ½ reduction in the residual offset.

[0039] Referring to FIG. 4, the operational phases are the same as described for FIG. 3 except that the gain of the amplifier 200 is varied during each phase by varying the values of the resistances R1 214 and R2P 216 and R2N 218. For the purposes of the auto zero function, any combination of values of R1 214 and R2P 216 and R2N 218 which achieve the desired gain values may be used. In timing portion A, normal operation, the amplifier gain is set to a value of gain1. The value of gain1 is dependent upon the application in which the amplifier 200 is being used and the desired gain required by that application. For example, gain1 may be set to a value between 0 and a maximum of 40 dB. During timing portions B1 and B2, the offset cancellation operational phases, the highest gain setting available for the amplifier is used. The highest gain setting is equal to the maximum setting of gain1, i.e., the maximum gain available in the given application/implementation of the amplifier 200. For example, in an amplifier with a maximum gain1 of 40 dB, the highest gain setting is 40 dB. During timing portion C, normal operation, after the offset cancellation phase is completed another gain setting, gain2, is used which may be the same as gain1 or anything other gain setting equal to or below the highest gain setting depending, again, upon the application in which the amplifier is being used.

[0040] The advantage of varying the gain in this way is that by applying the maximum available gain during the offset cancellation phase, it is assured that after the auto zero, the gain will be set to at most the maximum gain or any value below that. This means that the residual offset after the offset cancellation phase was completed and gain2 is applied, i.e. timing portion C, is equal to or lower than the residual offset at the end of the offset cancellation phase itself, i.e. timing portion B2.

[0041] It is to be noted that suitable transistor sizes specifying channel width-to-length ratios (measured in micrometers or microns) for the transistors which make up the depicted circuits have been omitted from the figures. It will be appreciated that suitable ratios may be chosen depending on the design requirements and the capabilities and limitations of the particular integrated circuit fabrication process used for implementation of the circuit as well as the performance requirements of the specific embodiment.

[0042] It is therefore intended that the foregoing detailed description be regarded as illustrative rather than limiting, and that it be understood that it is the following claims, including all equivalents, that are intended to define the spirit and scope of this invention.

Claims

1. A differential amplifier comprising: a first input stage operative to receive a first input signal; a second input stage operative to receive a second input signal; a programmable gain input operative to set a gain of said differential amplifier; an output stage operative to produce an output signal equal to the amplification of the difference between the first signal and the second signal according to said gain; and an offset cancellation circuit operative to actively cancel offset voltage in said output signal added by said differential amplifier and vary said gain to reduce residual offset.

2. The differential amplifier of claim 1, further being responsive to a two-phase clock, wherein said first input stage is further operative to receive said first input signal on a first phase of said two-phase clock and receive a common signal on a second phase of said two-phase clock, said second input stage is further operative to receive said second input signal on said first phase and said common signal on said second phase and further wherein said offset cancellation circuit is further operative to set said gain to a maximum value and compute an adjusted bias current on said second phase and apply said adjusted bias current on said first phase to cancel said offset voltage.

3. The differential amplifier of claim 1, wherein said offset cancellation circuit further comprises an offset voltage detector operative to measure said offset voltage and an offset voltage compensator operative to substantially zero out any detected offset voltage.

4. The differential amplifier of claim 1, wherein said first input stage, said second input stage and said output stage form a signal path separate from said offset cancellation circuit.

5. A method of canceling offset between first and second stages of an open loop differential amplifier having a variable gain, the method comprising: (a) disconnecting inputs to said first and second stages from an input source; (b) setting said variable gain to a maximum value; (c) connecting said inputs to a common voltage source; (d) detecting output offset voltage on outputs of said amplifier; (e) computing an adjusted bias current to cancel said output offset voltage; (f) disconnecting said inputs from said common voltage source; (g) reconnecting said inputs to said input source; (h) setting said variable gain to an application value; and (i) applying said adjusted bias current to cancel said output offset voltage.

6. The method of claim 5, wherein said input source comprises a differential input source.

7. The method of claim 5, wherein (e) further comprises: adjusting a control voltage on a current biasing transistor; and storing said control voltage.

8. The method of claim 7, wherein said control voltage is stored in a capacitor.

9. The method of claim 5, wherein (e) further comprises computing said adjusted bias current so that said output offset voltage is zeroed out.

10. An apparatus for canceling offset in an open loop differential amplifier having a variable gain comprising: an offset detector operative to connect inputs of said amplifier to a common source, maximize said variable gain and detect offset voltage imparted by said amplifier alone and further operative to determine an appropriate bias current in said amplifier to cancel said detected offset voltage; and an offset compensator operative to return said variable gain to an application based value and apply said appropriate bias current to said amplifier to cancel said offset voltage.

11. The apparatus of claim 10, wherein said amplifier is configured to function in alternating operational and non-operational phases, wherein said offset detector is configured to operate in said non-operational phase and said offset compensator operative is configured to operate in said operational phase.

12. An apparatus for canceling offset in an open loop differential amplifier comprising: means for detecting an offset voltage in an output signal of said amplifier, said offset voltages added by said amplifier, and determining an appropriate bias current in said amplifier to cancel said detected offset voltage; means for reducing residual offset; and means for applying said appropriate bias current to said amplifier to cancel said offset voltage.