Patent Application
20140266376
The present invention relates to clock distribution designs, such as active clock trees. Clock distributors can be used in high speed digital to analog converters (DACs), analog to digital converters (ADCs), and clock distribution circuits which, in turn, are provided in integrated circuits.
High speed clocked circuit systems are often driven by externally supplied clock systems. Although high speed components typically operate in about the 1-20 GHz frequency range, frequencies as low as 100 MHz and higher frequencies are also used. At higher frequencies, timing mismatch requirements become stricter.
Timing mismatch is known to occur between cells in a DAC. As DACs are also used in ADCs, such as sigma-delta ADCs, the timing mismatch problem is known to occur in ADCs as well. Since each cell is spatially separated, it is difficult to provide identically timed clocks to each cell. Performance of DACs, ADCs, and other circuits, such as clock chips, can be impaired by timing mismatch errors. These errors in clock distribution can cause performance degradations such as distortions.
Accordingly, the inventors have identified a need in the art for a clock distributor system that improves clock timing match. Moreover, the inventors have identified a need in the art for a clock distribution system that can support higher speed converters.
The embodiments of the present invention provide a multi-stage clock distribution circuit for an integrated circuit. The clock distribution circuit may route a common clock signal to a plurality of clock receiver circuits. Each stage in the distribution circuit may include a plurality of buffers. Outputs of at least some, perhaps all, of the buffers may be connected to each other by an interconnect. The interconnect may align clock signals that are output by the interconnected buffers and thereby encourage synchronization of those clock signals. Other stages of the clock distribution signal may be connected as well.
The input clock signal can be connected directly to the first stage buffers 110.0-110.n, which distribute the clock signal to the second stage buffers 120.0-120.n. After each buffer stage, clock buffer outputs can be shorted by first and second interconnects 115, 125 to same stage clock buffer outputs. In advance of a subsequent stage, the first interconnect 115 shorts the output of first stage buffers 110.0-110.n. Similarly, the second interconnect 125 shorts the output of second stage buffers in advance of clock signal receivers 130.0-130.n.
Because interconnect 115 shorts buffers 110.0-110.n, clock signals output by buffers 110.0-110.n pull together and align. Similarly, since interconnect 125 shorts buffers 120.0-120.n, clock signals output by buffers 120.0-120.n pull together and align. Accordingly, clock averaging is provided, timing mismatch errors are attenuated, and clock jitter is reduced. After one or more stages, the clock signal aligns. In addition, the power of a clock driver (not shown) and the overall system can be reduced.
In addition, the drive load of each clock signal receiver 130.0-130.n (or other load circuit) may vary, and buffers and corresponding clock receivers may be tuned to each other. For example, buffer sizes can be adapted to match corresponding loads (i.e., clock receiver loads).
The example clock trees can be applied to a variety of clock or signal distribution systems, especially when it is desirable to maintain synchronization between spatially separated portions of a circuit. In some instances, one or more portions of a clock tree can be incorporated into the circuit cells of individual components. For example, one or more portions of a clock tree can be incorporated into a DAC cell. In this example, a clock tree may be implemented by a plurality of DAC cells. A DAC cell is a circuit block that can generate a weighted current/voltage. Cells generally consist of a latch and a current/voltage generating element that will create the analog output. Many cells can be arranged to form a multi-bit DAC/ADC. In a DAC cell, the current/voltage is updated at every clock edge based on the data input into the cell. Here, accurate timing of current/voltage output will achieve low distortion signal generation. Thus, lower distortion can be achieved by attenuating timing error using the clock trees of the present invention. By using a clock tree, the timing across multiple cells will be averaged such that each cell will have identical output timing.
A clock signal may be a system clock signal, or other clock signal provided by a clock generator (not shown), that is provided as a reference to synchronize the various electronic components, such as clock receivers 130.0-130.n. In various implementations, the clock receivers 130.0-130.n may be provided as latches, logic gates, flip-flops, or other circuit that operate in a common clock domain. Other components may employ the example clocking scheme such as, for example, various components of a processor, bus, or memory (e.g., RAM, cache, etc.). In another example, the clocking scheme can be applied to a low-skew data bus that will drive a DAC output.
In the example one-stage configuration shown in
In advance of clock signal receivers 230.0-230.n, interconnect 215 shorts the output of buffers 210.0-210.n. Because interconnect 215 provides an electrical short, the clock signals pull together and align. Accordingly, clock averaging is provided, timing mismatch errors are attenuated, and clock jitter is reduced. Compared to the two-stage example, the one-stage clock tree provides a coarser degree of alignment and error attenuation. In the one-stage example, the power of a clock driver (not shown) and the overall system can also be reduced.
Although one and two-stage configurations have been described, the present invention accommodates various numbers (N) of stages as may be desired.
In the example N-stage configuration shown in
In an N stage configuration, N stages of clock buffers can be used to drive the back-end clock signal receivers 330.0-330.n. Each of the N stage clock buffer outputs may be shorted to the same stage clock buffer outputs. Similar to the one and two stage configurations, clock averaging is used to reduce timing mismatch errors. Accordingly, clock averaging is provided, timing mismatch errors are attenuated, and clock jitter is reduced. As the number of stages increases, a higher degree of alignment and error attenuation can be achieved.
In instances with larger error, additional stages of clock buffers can be used. The resistance, magnetic coupling, or capacitive coupling of the shorting interconnects can vary the number of stages used in a clock tree. For example, when the resistance of interconnects is low, less stages are needed. Low resistance also improves clock phase noise outputted by the clock buffers resulting in an improved signal to noise ratio.
Although interconnects discussed above, such as interconnects 115 and 125, have been depicted as shorting each of buffers 110.0-110.n and 120.0-120.n respectively, interconnects can also be adapted to connect one or more subsets of the buffers in their respective stages.
In an example clock tree 500 shown in
In the example embodiments discussed above, such as clocking tree 100, each buffer can be used to drive a corresponding clock signal receiver. For example, clock buffers 110.2 and 120.2 drive clock receiver 130.2. However, a buffer can also be adapted to drive multiple receiving circuits.
Using embodiments described herein, clocks with higher frequencies can be utilized. As compared to prior architectures, the clock distribution system of the present invention reduces time skew while also reducing power consumption in the clock and maintaining low noise. For example, using the clocking scheme, less than 50 fs of clock skew over 32 bits across 1 mm of wide clock tree at 5 GHz could be achieved. Including the flip-flop, bit skew of under 200 fs was achieved.
It will be apparent to those skilled in the art that various modifications and variations can be made in the clock distribution system of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
This application claims the benefit of U.S. Provisional Patent Application No. 61/792,062 filed on Mar. 15, 2013, which is incorporated herein by reference
| Number | Date | Country | |
|---|---|---|---|
| 61792062 | Mar 2013 | US |
