ACTIVE COMPONENT ARRAY SUBSTRATE

Abstract

Scan lines and data lines are disposed in a display region of a substrate, and multiple pixel regions are divided thereon. Switch components are disposed in the pixel regions, and each switch component is electrically connected to the scan line and data line. Pixel electrodes are disposed in the pixel regions and each pixel electrode is electrically connected to the switch component. Wires are disposed in a non-display region of the substrate, and at least one portion of each wire includes a first and a second conductor layer, wherein the second conductor layer is disposed on the first conductor layer and parallel-connected to the first conductor layer. The first conductor layer and one of the scan lines, data lines, and the pixel electrodes are in the same layer. The second conductor layer and another one of the scan lines, data lines, and the pixel electrodes are in the same layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a top view of a conventional thin film transistor array substrate.

FIG. 2A illustrates a top view of an active component array substrate according to a first preferred embodiment of the present invention.

FIG. 2B illustrates a cross-sectional view along the A-A′ line of FIG. 2A.

FIG. 2C illustrates a cross-sectional view of another first wire according to the first preferred embodiment of the present invention.

FIGS. 3A to 3E illustrate cross-sectional views of the first wire according to a second preferred embodiment of the present invention.

Claims

1. An active component array substrate, comprising: a substrate having a display region and a non-display region;a plurality of scan lines disposed in the display region;a plurality of data lines disposed in the display region, wherein the scan lines and the data lines divide the display region into a plurality of the pixel regions;a plurality of switch components respectively disposed in the pixel regions, and electrically connected to the scan lines and the data lines;a plurality of pixel electrodes respectively disposed in the pixel regions and electrically connected to the corresponding switch components;a plurality of first wires disposed in the non-display region, wherein at least one portion of each of the first wires includes: a first conductor layer disposed on the substrate; anda second conductor layer disposed on the first conductor layer and electrically parallel-connected to the first conductor layer; wherein the first conductor layer and one of the scan lines, the data lines, and the pixel electrodes are in the same layer, and the second conductor layer and another one of the scan lines, the data lines, and the pixel electrodes are in the same layer.

2. The active component array substrate as claimed in claim 1, wherein each of the first wires is connected to one of the scan lines or one of the data lines.

3. The active component array substrate as claimed in claim 1, further comprising a plurality of second wires disposed in the non-display region, wherein each of the second wires and the scan lines or the data lines are in the same layer.

4. The active component array substrate as claimed in claim 3, wherein the length of each first wire is greater than that of each second wire.

5. The active component array substrate as claimed in claim 3, wherein each of the second wires is connected to one of the scan lines or one of the data lines.

6. The active component array substrate as claimed in claim 1, wherein each of the first wires further comprises a first dielectric layer sandwiched between the first conductor layer and the second conductor layer, wherein the first dielectric layer has a plurality of first contact holes for exposing part of the first conductor layer, and the second conductor layer covers the first contact holes and is electrically parallel-connected to the first conductor layer.

7. The active component array substrate as claimed in claim 1, wherein each first wire further comprises a third conductor layer disposed on the second conductor layer; and the first conductor layer, the second conductor layer, and the third conductor layer are electrically connected in parallel, wherein the first conductor layer and the scan lines are in the same layer; the second conductor layer and the data lines are in the same layer; and the third conductor layer and the pixel electrodes are in the same layer.

8. The active component array substrate as claimed in claim 7, wherein each first wire further comprises: a first dielectric layer disposed between the first conductor layer and the second conductor layer; anda second dielectric layer disposed between the second conductor layer and the third conductor layer, and provided with a plurality of second contact holes for exposing part of the second conductor layer, wherein the third conductor layer covers the second contact holes and electrically parallel-connected to the second conductor layer, and there are a plurality of first contact holes within the first dielectric layer and the second dielectric layer to expose part of the first conductor layer, and the third conductor layer covers the first contact holes and is electrically parallel-connected to the first conductor layer.

9. The active component array substrate as claimed in claim 7, wherein each first wire further comprises a first dielectric layer disposed between the first conductor layer and the second conductor layer, and the first dielectric layer has a plurality of first contact holes for exposing part of the first conductor layer, and the second conductor layer covers the first contact holes and is electrically parallel-connected to the first conductor layer.

10. The active component array substrate as claimed in claim 7, wherein each first wire further comprises a second dielectric layer disposed between the second conductor layer and the third conductor layer, and the second dielectric layer has a plurality of second contact holes for exposing part of the second conductor layer, and the third conductor layer covers the second contact holes and is electrically parallel-connected to the second conductor layer.

11. The active component array substrate as claimed in claim 1, further comprising a plurality of pads disposed in the non-display region, wherein one end of each of the first wires is connected to one of the pads respectively.

12. The active component array substrate as claimed in claim 1, wherein the switch components are thin film transistors.